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authorBorja Martinez2016-09-19 11:58:33 -0500
committerBorja Martinez2016-09-19 11:58:33 -0500
commit0c81a258866b3759ef27807fa1115994f4f51464 (patch)
treefe83624ad448cfb390d24c38bef866ff61a6e5b3
parent1944510ab8110d38d88d67bcc5634f9414ef27b0 (diff)
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MSP430 BSL shared RST (JTAG chain)
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd144
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c391
2 files changed, 535 insertions, 0 deletions
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd
new file mode 100644
index 0000000..a0ba06b
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/lnk_msp430g2221.cmd
@@ -0,0 +1,144 @@
1/* ============================================================================ */
2/* Copyright (c) 2016, Texas Instruments Incorporated */
3/* All rights reserved. */
4/* */
5/* Redistribution and use in source and binary forms, with or without */
6/* modification, are permitted provided that the following conditions */
7/* are met: */
8/* */
9/* * Redistributions of source code must retain the above copyright */
10/* notice, this list of conditions and the following disclaimer. */
11/* */
12/* * Redistributions in binary form must reproduce the above copyright */
13/* notice, this list of conditions and the following disclaimer in the */
14/* documentation and/or other materials provided with the distribution. */
15/* */
16/* * Neither the name of Texas Instruments Incorporated nor the names of */
17/* its contributors may be used to endorse or promote products derived */
18/* from this software without specific prior written permission. */
19/* */
20/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
21/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
22/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
23/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
24/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
25/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
26/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
27/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
28/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
29/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
30/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
31/* ============================================================================ */
32
33/******************************************************************************/
34/* lnk_msp430g2221.cmd - LINKER COMMAND FILE FOR LINKING MSP430G2221 PROGRAMS */
35/* */
36/* Usage: lnk430 <obj files...> -o <out file> -m <map file> lnk.cmd */
37/* cl430 <src files...> -z -o <out file> -m <map file> lnk.cmd */
38/* */
39/*----------------------------------------------------------------------------*/
40/* These linker options are for command line linking only. For IDE linking, */
41/* you should set your linker options in Project Properties */
42/* -c LINK USING C CONVENTIONS */
43/* -stack 0x0100 SOFTWARE STACK SIZE */
44/* -heap 0x0100 HEAP AREA SIZE */
45/* */
46/*----------------------------------------------------------------------------*/
47/* Version: 1.191 */
48/*----------------------------------------------------------------------------*/
49
50/****************************************************************************/
51/* Specify the system memory map */
52/****************************************************************************/
53
54MEMORY
55{
56 SFR : origin = 0x0000, length = 0x0010
57 PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
58 PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
59 RAM : origin = 0x0200, length = 0x0080
60 INFOA : origin = 0x10C0, length = 0x0040
61 INFOB : origin = 0x1080, length = 0x0040
62 INFOC : origin = 0x1040, length = 0x0040
63 INFOD : origin = 0x1000, length = 0x0040
64 FLASH : origin = 0xF800, length = 0x07E0
65 INT00 : origin = 0xFFE0, length = 0x0002
66 INT01 : origin = 0xFFE2, length = 0x0002
67 INT02 : origin = 0xFFE4, length = 0x0002
68 INT03 : origin = 0xFFE6, length = 0x0002
69 INT04 : origin = 0xFFE8, length = 0x0002
70 INT05 : origin = 0xFFEA, length = 0x0002
71 INT06 : origin = 0xFFEC, length = 0x0002
72 INT07 : origin = 0xFFEE, length = 0x0002
73 INT08 : origin = 0xFFF0, length = 0x0002
74 INT09 : origin = 0xFFF2, length = 0x0002
75 INT10 : origin = 0xFFF4, length = 0x0002
76 INT11 : origin = 0xFFF6, length = 0x0002
77 INT12 : origin = 0xFFF8, length = 0x0002
78 INT13 : origin = 0xFFFA, length = 0x0002
79 INT14 : origin = 0xFFFC, length = 0x0002
80 RESET : origin = 0xFFFE, length = 0x0002
81}
82
83/****************************************************************************/
84/* Specify the sections allocation into memory */
85/****************************************************************************/
86
87SECTIONS
88{
89 .bss : {} > RAM /* Global & static vars */
90 .data : {} > RAM /* Global & static vars */
91 .TI.noinit : {} > RAM /* For #pragma noinit */
92 .sysmem : {} > RAM /* Dynamic memory allocation area */
93 .stack : {} > RAM (HIGH) /* Software system stack */
94
95 .text : {} > FLASH /* Code */
96 .cinit : {} > FLASH /* Initialization tables */
97 .const : {} > FLASH /* Constant data */
98 .cio : {} > RAM /* C I/O Buffer */
99
100 .pinit : {} > FLASH /* C++ Constructor tables */
101 .binit : {} > FLASH /* Boot-time Initialization tables */
102 .init_array : {} > FLASH /* C++ Constructor tables */
103 .mspabi.exidx : {} > FLASH /* C++ Constructor tables */
104 .mspabi.extab : {} > FLASH /* C++ Constructor tables */
105#ifdef __TI_COMPILER_VERSION
106 #if __TI_COMPILER_VERSION >= 15009000
107 #ifndef __LARGE_DATA_MODEL__
108 .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
109 #else
110 .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
111 #endif
112 #endif
113#endif
114
115 .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */
116 .infoB : {} > INFOB
117 .infoC : {} > INFOC
118 .infoD : {} > INFOD
119
120 /* MSP430 Interrupt vectors */
121 .int00 : {} > INT00
122 .int01 : {} > INT01
123 PORT1 : { * ( .int02 ) } > INT02 type = VECT_INIT
124 PORT2 : { * ( .int03 ) } > INT03 type = VECT_INIT
125 USI : { * ( .int04 ) } > INT04 type = VECT_INIT
126 .int05 : {} > INT05
127 .int06 : {} > INT06
128 .int07 : {} > INT07
129 TIMERA1 : { * ( .int08 ) } > INT08 type = VECT_INIT
130 TIMERA0 : { * ( .int09 ) } > INT09 type = VECT_INIT
131 WDT : { * ( .int10 ) } > INT10 type = VECT_INIT
132 .int11 : {} > INT11
133 .int12 : {} > INT12
134 .int13 : {} > INT13
135 NMI : { * ( .int14 ) } > INT14 type = VECT_INIT
136 .reset : {} > RESET /* MSP430 Reset vector */
137}
138
139/****************************************************************************/
140/* Include peripherals memory map */
141/****************************************************************************/
142
143-l msp430g2221.cmd
144
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c
new file mode 100644
index 0000000..c7e5407
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Chain/main.c
@@ -0,0 +1,391 @@
1/*---------------------------------------------------------------------------*/
2
3#include <msp430.h>
4#include <stdint.h>
5#include <stdbool.h>
6#include <stdio.h>
7
8#define CC2650
9#define MSP432
10
11
12/*---------------------------------------------------------------------------*/
13#define BOOTLOADER_INVERT_LINES
14
15#ifndef BOOTLOADER_INVERT_LINES
16 /* MPS432 */
17 #define RESET_IN1 (BIT0) // RTS - RESET
18 #define BOOT_IN1 (BIT1) // DTR - BOOT
19 #define BOOT_OUT1 (BIT3) // BSL
20
21 #define RESET_IN2 (BIT4) // RTS - RESET
22 #define BOOT_IN2 (BIT5) // DTR - BOOT
23 #define BOOT_OUT2 (BIT7) // BSL
24
25 #define RESET_OUT (BIT2) // RESET
26#else
27 /* MPS432 */
28 #define BOOT_IN1 (BIT0) // RTS - BOOT
29 #define RESET_IN1 (BIT1) // DTR - RESET
30 #define BOOT_OUT1 (BIT3) // BSL
31 /* CC2650 */
32 #define BOOT_IN2 (BIT4) // RTS - BOOT
33 #define RESET_IN2 (BIT5) // DTR - RESET
34 #define BOOT_OUT2 (BIT7) // BSL
35
36 #define RESET_OUT (BIT2) // RESET
37#endif
38
39
40/*---------------------------------------------------------------------------*/
41/* Timer Delays*/
42#define STARTUP_DELAY (750) // ~0.5s @ 1.5 Khz
43#define BOOTLOADER_TIMEOUT (75) // ~50 ms @ 1.5 kHz
44
45/*---------------------------------------------------------------------------*/
46/* Procesor Delays */
47#define MSEC_DELAY (4250) // ~1 ms @ 4.25 MHz
48#define CC2650_BSL_DELAY (8500) // 2 ms @ 4.25 MHz
49#define MSP432_BSL_DELAY (42500) // 10 ms @ 4.25 MHz
50
51
52/*---------------------------------------------------------------------------*/
53static volatile bool bootloader_active = false;
54static volatile bool bootload_enable = false;
55
56
57/*---------------------------------------------------------------------------*/
58int main(void) {
59
60 int i;
61
62 // Disable Watchdog
63 WDTCTL = WDTPW + WDTHOLD;
64
65 // Set DCO operation to 4.25 MHz
66 BCSCTL1 &= ~(BIT2 + BIT1 + BIT0);
67 BCSCTL1 |= (BIT3 + BIT1 + BIT0);
68
69 /*
70 MCLK = DCO / 1 = 4.25 MHz
71 SMCLK = DCO / 1 = 4.25 MHz
72 ACLK = VLOCLK / 8 = 12 kHz / 8 = 1.5 kHz
73 */
74 BCSCTL1 |= (XT2OFF + DIVA_3);
75 BCSCTL3 |= (LFXT1S_2);
76
77 /* Wait Oscillator stable */
78 while (IFG1 & OFIFG) // OSCFault flag still set?
79 {
80 IFG1 &= ~OFIFG; // Clear OSCFault flag
81 for (i = 0xFFF; i > 0; i--); // Time for flag to set
82 }
83
84 // Startup Delay: avoid DTR/RTS glitches on FDTI initialization
85 TACCTL1 = CCIE;
86 TACCR1 = STARTUP_DELAY;
87 TACTL = (TASSEL_1 + MC_2 + TAIE + TACLR);
88 _BIS_SR(LPM3_bits + GIE);
89
90// Configure P1 input and ouput
91 P1DIR &= ~(RESET_OUT);
92
93 #ifdef MSP432
94 P1DIR &= ~(RESET_IN1 + BOOT_IN1);
95 P1DIR |= (BOOT_OUT1);
96 P1OUT |= (BOOT_OUT1);
97#endif
98
99#ifdef CC2650
100 P1DIR &= ~(RESET_IN2 + BOOT_IN2);
101 P1DIR |= (BOOT_OUT2);
102 P1OUT |= (BOOT_OUT2);
103#endif
104
105// Configure P1 ints
106#ifdef MSP432
107 // Configure BOOT_IN1 interrupt high to low
108 P1IFG &=~ (BOOT_IN1);
109 P1IES |= (BOOT_IN1);
110 P1IE |= (BOOT_IN1);
111#endif
112
113#ifdef CC2650
114 // Configure BOOT_IN2 interrupt high to low
115 P1IFG &=~ (BOOT_IN2);
116 P1IES |= (BOOT_IN2);
117 P1IE |= (BOOT_IN2);
118#endif
119
120 // Forever: Go to the lowest LPM
121 while (1) {
122 if (bootloader_active == true) {
123 _BIS_SR(LPM3_bits + GIE);
124 } else {
125 _BIS_SR(LPM4_bits + GIE);
126 }
127 }
128
129 return 0;
130
131}
132/*---------------------------------------------------------------------------*/
133#pragma vector=PORT1_VECTOR
134__interrupt void port1_isr (void) {
135
136 int flag=0;
137
138#ifdef MSP432
139
140 // BOOT_IN2 high to low
141 if (((P1IFG & BOOT_IN1) == BOOT_IN1) &&
142 ((P1IN & BOOT_IN1) == 0) &&
143 ((P1IES & BOOT_IN1) == BOOT_IN1)) {
144
145 // BOOT_IN2 interrupt clear and disable
146 P1IFG &=~ (BOOT_IN1);
147 P1IE &=~ (BOOT_IN1);
148
149 flag=1;
150
151 /* Disable CC2650 BSL */
152 P1IFG &=~(RESET_IN2|BOOT_IN2);
153 P1IE &=~(RESET_IN2|BOOT_IN2);
154
155 /* Enable Reset High to Low */
156 P1IES |= (RESET_IN1);
157 P1IFG &=~ (RESET_IN1);
158 P1IE |= (RESET_IN1);
159
160 // RESET_IN1 should be low
161 if ((P1IN & RESET_IN1) == 0) {
162 bootloader_active = true;
163 }
164 }
165
166
167 // RESET_IN1 high to low
168 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
169 ((P1IN & RESET_IN1) == 0) &&
170 ((P1IES & RESET_IN1) == RESET_IN1)) {
171
172 // RESET_IN1 interrupt clear and disable
173 P1IFG &=~(RESET_IN1);
174 P1IE &=~(RESET_IN1);
175
176 flag=1;
177
178 /* Enable Reset_IN Low to High */
179 P1IES &=~ (RESET_IN1);
180 P1IFG &=~ (RESET_IN1);
181 P1IE |= (RESET_IN1);
182
183 // Enable Bootload
184 bootload_enable = true;
185 }
186
187
188
189 // RESET_IN1 low to high
190 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
191 ((P1IN & RESET_IN1) == RESET_IN1) &&
192 ((P1IES & RESET_IN1) == 0)) {
193
194 // RESET_IN1 interrupt clear and dsiable
195 P1IFG &=~(RESET_IN1);
196 P1IE &= ~(RESET_IN1);
197
198 flag=1;
199
200 // If bootload_enable is set
201 if (bootload_enable == true) {
202
203 // RESET_OUT ouput
204 P1DIR |= (RESET_OUT);
205 P1OUT &= ~(BOOT_OUT1);
206
207 // Reset Pulse
208 __delay_cycles(MSEC_DELAY);
209 P1OUT &=~(RESET_OUT);
210 __delay_cycles(MSEC_DELAY);
211 P1OUT |= (RESET_OUT);
212
213 __delay_cycles(MSP432_BSL_DELAY);
214 // Release Boot Pin
215 P1OUT |= (BOOT_OUT1);
216 P1DIR &= ~(RESET_OUT);
217
218 }
219 }
220#endif
221
222#ifdef CC2650
223
224 // BOOT_IN2 high to low
225 if (((P1IFG & BOOT_IN2) == BOOT_IN2) &&
226 ((P1IN & BOOT_IN2) == 0) &&
227 ((P1IES & BOOT_IN2) == BOOT_IN2)) {
228
229 // BOOT_IN2 interrupt clear and disable
230 P1IFG &=~ (BOOT_IN2);
231 P1IE &=~ (BOOT_IN2);
232
233 flag=1;
234
235 /* Disable MCP432 Boot */
236 P1IFG &=~(RESET_IN1|BOOT_IN1);
237 P1IE &=~(RESET_IN1|BOOT_IN1);
238
239 /* Enable Reset High to Low */
240 P1IES |= (RESET_IN2);
241 P1IFG &=~ (RESET_IN2);
242 P1IE |= (RESET_IN2);
243
244 // RESET_IN2 should be low
245 if ((P1IN & RESET_IN2) == 0) {
246 bootloader_active = true;
247 }
248 }
249
250
251 // RESET_IN1 high to low
252 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
253 ((P1IN & RESET_IN2) == 0) &&
254 ((P1IES & RESET_IN2) == RESET_IN2)) {
255
256 // RESET_IN2 interrupt clear
257 P1IFG &=~(RESET_IN2);
258 P1IE &=~(RESET_IN2);
259
260 flag=1;
261
262 /* Low to High */
263 P1IES &=~ (RESET_IN2);
264 P1IFG &=~ (RESET_IN2);
265 P1IE |= (RESET_IN2);
266
267 // Set bootloader_active
268 bootload_enable = true;
269 }
270
271
272
273 // RESET_IN1 low to high
274 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
275 ((P1IN & RESET_IN2) == RESET_IN2) &&
276 ((P1IES & RESET_IN2) == 0)) {
277
278 // RESET_IN1 interrupt clear
279 P1IFG &=~(RESET_IN2);
280 P1IE &= ~(RESET_IN2);
281
282 flag=1;
283
284 // If bootload_enable is set
285 if (bootload_enable == true) {
286
287 // RESET_OUT1 is now ouput
288 P1DIR |= (RESET_OUT);
289 //__delay_cycles(STARTUP_DELAY);
290 P1OUT &= ~(BOOT_OUT2);
291
292 /* Reset Pulse */
293 __delay_cycles(425);
294 P1OUT &=~(RESET_OUT);
295 __delay_cycles(MSEC_DELAY);
296 P1OUT |= (RESET_OUT);
297 __delay_cycles(CC2650_BSL_DELAY);
298
299 /* Release Boot Pin*/
300 P1OUT |= (BOOT_OUT2);
301 // RESET_OUT2 is now input
302 P1DIR &= ~(RESET_OUT);
303 }
304 }
305#endif
306
307 /* Unknown Sequence: Disable PIOs, Wait Timout */
308 if(flag==0){
309 P1IE &=~ (RESET_IN1|RESET_IN2|BOOT_IN1|BOOT_IN2);
310 P1IFG = 0;
311 }
312
313 // Set TIMER_A-CCR0 Timout
314 TACCR0 = BOOTLOADER_TIMEOUT;
315 TACCTL0 = (CCIE);
316 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
317
318 _BIC_SR_IRQ(LPM4_bits + GIE);
319
320}
321/*---------------------------------------------------------------------------*/
322#pragma vector=TIMERA0_VECTOR
323__interrupt void timera0_isr (void) {
324
325 // TIMERA0 reset
326 TACTL = 0;
327 TACCTL0 &=~(CCIE);
328
329 // Clear variables
330 bootloader_active = false;
331 bootload_enable = false;
332
333 // Ensure RESET_OUT1 and BOOT_OUT1 are high
334 P1OUT |= (RESET_OUT + BOOT_OUT1);
335 P1DIR &=~(RESET_OUT);
336
337#ifdef MSP432
338 // (Re)Enable BOOT_IN1 high to low Int
339 P1IES |= (BOOT_IN1);
340 P1IFG &= ~(RESET_IN1+BOOT_IN1);
341 P1IE &=~ (RESET_IN1);
342 P1IE |= (BOOT_IN1);
343#endif
344
345
346#ifdef CC2650
347 // (Re)Enable RESET_IN2 high to low Int
348 P1IES |= (BOOT_IN2);
349 P1IFG &= ~(RESET_IN2+BOOT_IN2);
350 P1IE &=~ (RESET_IN2);
351 P1IE |= (BOOT_IN2);
352#endif
353
354
355 _BIC_SR_IRQ(LPM3_bits + GIE);
356
357}
358
359#pragma vector=TIMERA1_VECTOR
360__interrupt void timera1_isr (void) {
361
362
363 switch(TAIV)
364 {
365 case TAIV_TACCR1: // CCR1
366 {
367 TACTL = 0;
368 TACCTL1 &=~(CCIE);
369 }
370 break;
371
372 case TAIV_TAIFG: // overflow not used
373 break;
374
375 }
376
377 _BIC_SR_IRQ(LPM3_bits + GIE);
378
379}
380
381
382/*
383#pragma vector=NMI_VECTOR
384__interrupt void nmi_isr (void) {
385 _BIC_SR_IRQ(LPM3_bits + GIE);
386}
387*/
388
389
390
391/*---------------------------------------------------------------------------*/