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authorBorja Martinez2016-09-18 14:31:58 -0500
committerBorja Martinez2016-09-18 14:31:58 -0500
commit1944510ab8110d38d88d67bcc5634f9414ef27b0 (patch)
treefe36c6f894b89a9f1f5b923857e1552ff620bbc1
parent6f7b1bd78f4a486267cd7fe9d1669e37191be872 (diff)
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BSL msp430 Inverted DTR-RTS signals
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c50
1 files changed, 35 insertions, 15 deletions
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
index 43007cb..fe0983e 100644
--- a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
@@ -8,21 +8,39 @@
8#define CC2650 8#define CC2650
9#define MSP432 9#define MSP432
10 10
11
11/*---------------------------------------------------------------------------*/ 12/*---------------------------------------------------------------------------*/
12#define RESET_IN1 (BIT0) // RTS - RESET 13#define BOOTLOADER_INVERT_LINES
13#define BOOT_IN1 (BIT1) // DTR - BOOT 14
14#define RESET_OUT1 (BIT2) // RTS - RESET 15#ifndef BOOTLOADER_INVERT_LINES
15#define BOOT_OUT1 (BIT3) // DTR - BOOT 16 /* MPS432 */
16/*---------------------------------------------------------------------------*/ 17 #define RESET_IN1 (BIT0) // RTS - RESET
17#define RESET_IN2 (BIT4) // RTS - RESET 18 #define BOOT_IN1 (BIT1) // DTR - BOOT
18#define BOOT_IN2 (BIT5) // DTR - BOOT 19 #define RESET_OUT1 (BIT2) // RTS - RESET
19#define RESET_OUT2 (BIT6) // RTS - RESET 20 #define BOOT_OUT1 (BIT3) // DTR - BOOT
20#define BOOT_OUT2 (BIT7) // DTR - BOOT 21 /* CC2650 */
22 #define RESET_IN2 (BIT4) // RTS - RESET
23 #define BOOT_IN2 (BIT5) // DTR - BOOT
24 #define RESET_OUT2 (BIT6) // RTS - RESET
25 #define BOOT_OUT2 (BIT7) // DTR - BOOT
26#else
27 /* MPS432 */
28 #define BOOT_IN1 (BIT0) // RTS - BOOT
29 #define RESET_IN1 (BIT1) // DTR - RESET
30 #define RESET_OUT1 (BIT2) // RTS - RESET
31 #define BOOT_OUT1 (BIT3) // DTR - BOOT
32 /* CC2650 */
33 #define BOOT_IN2 (BIT4) // RTS - BOOT
34 #define RESET_IN2 (BIT5) // DTR - RESET
35 #define RESET_OUT2 (BIT6) // RTS - RESET
36 #define BOOT_OUT2 (BIT7) // DTR - BOOT
37#endif
38
21 39
22/*---------------------------------------------------------------------------*/ 40/*---------------------------------------------------------------------------*/
23/* Timer Delays*/ 41/* Timer Delays*/
24#define STARTUP_DELAY (5*1500) // ~5s @ 1.5 Khz 42#define STARTUP_DELAY (750) // ~0.5s @ 1.5 Khz
25#define BOOTLOADER_TIMEOUT (50) // ~100 ms @ 1.5 kHz 43#define BOOTLOADER_TIMEOUT (75) // ~50 ms @ 1.5 kHz
26 44
27/*---------------------------------------------------------------------------*/ 45/*---------------------------------------------------------------------------*/
28/* Procesor Delays */ 46/* Procesor Delays */
@@ -286,15 +304,17 @@ __interrupt void port1_isr (void) {
286 } 304 }
287#endif 305#endif
288 306
307 /* Unknown Sequence: Disable PIOs, Wait Timout */
308 if(flag==0){
309 P1IE &=~ (RESET_IN1|RESET_IN2|BOOT_IN1|BOOT_IN2);
310 P1IFG = 0;
311 }
312
289 // Set TIMER_A-CCR0 Timout 313 // Set TIMER_A-CCR0 Timout
290 TACCR0 = BOOTLOADER_TIMEOUT; 314 TACCR0 = BOOTLOADER_TIMEOUT;
291 TACCTL0 = (CCIE); 315 TACCTL0 = (CCIE);
292 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR); 316 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
293 317
294 if(flag==0){
295 P1IFG = 0;
296 }
297
298 _BIC_SR_IRQ(LPM4_bits + GIE); 318 _BIC_SR_IRQ(LPM4_bits + GIE);
299 319
300} 320}