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authorBorja Martinez2016-12-16 10:39:22 -0600
committerBorja Martinez2016-12-16 10:39:22 -0600
commit199cad64eb7f25e2263049ca41c349ceb16e7db5 (patch)
tree80bb91cc1ac2616bc013a42bc51e88d849414684
parent444105ac3e09205bf148123a9634f6935313d946 (diff)
downloadi3-mote-199cad64eb7f25e2263049ca41c349ceb16e7db5.tar.gz
i3-mote-199cad64eb7f25e2263049ca41c349ceb16e7db5.tar.xz
i3-mote-199cad64eb7f25e2263049ca41c349ceb16e7db5.zip
Removed aold version MSP432
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c191
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c189
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c435
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c247
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c189
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c435
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c80
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c254
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c369
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c123
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c254
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/system_msp432p401r.c434
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c146
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c255
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c434
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c202
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h48
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c91
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd104
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c219
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c399
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.c250
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/HAL_I2C.h50
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/i3mote.h62
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/main.c266
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/startup_msp432p401r_ccs.c255
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_Sensors/system_msp432p401r.c434
39 files changed, 0 insertions, 7291 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h
deleted file mode 100644
index e27c845..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* HID Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7/* Rev.A
8#define HID_PORT GPIO_PORT_P8
9#define LEDR GPIO_PIN5
10#define LEDG GPIO_PIN6
11#define BUTTON GPIO_PIN7
12*/
13
14/* Power Control */
15#define CTL_PWR_PORT GPIO_PORT_P2
16#define GPS_PWR_nEN_PIN GPIO_PIN4
17#define SSM_PWR_nEN_PIN GPIO_PIN5
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
26/* Flash SPI */
27#define FLASH_SPI_PORT GPIO_PORT_P3
28#define FLASH_SPI_CSN_PIN GPIO_PIN0
29#define FLASH_SPI_CLK_PIN GPIO_PIN1
30#define FLASH_SPI_MISO_PIN GPIO_PIN2
31#define FLASH_SPI_MOSI_PIN GPIO_PIN3
32
33
34/* CC2650 SPI */
35#define CC2650_SPI_PORT GPIO_PORT_P2
36#define CC2650_SPI_CSN_PIN GPIO_PIN0
37#define CC2650_SPI_CLK_PIN GPIO_PIN1
38#define CC2650_SPI_MISO_PIN GPIO_PIN2
39#define CC2650_SPI_MOSI_PIN GPIO_PIN3
40
41#define CC2650_IRQ_PORT GPIO_PORT_P4
42#define CC2650_IRQ_PIN GPIO_PIN0
43
44/* On Board EEPROM 25xx256*/
45#define EEPROM_SLAVE_ADDRESS 0x50
46
47
48/* On Board Sensors */
49#define IN219
50#define OPT3001
51#define HDC1080
52#define BMP280
53#define MPU9250
54#define TMP007
55
56#define Board_HDC1080_ADDR 0x40
57#define Board_INA219_ADDR 0x41
58#define Board_TMP007_ADDR 0x44
59#define Board_OPT3001_ADDR 0x45
60#define Board_MPU9250_ADDR 0x68
61#define Board_BMP280_ADDR 0x77
62
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c
deleted file mode 100644
index 6240674..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/******************************************************************************
2 * MSP432 SPI - 3-wire Master Interface to on-board M24P40
3 *
4 * Reads M25P40 Chip ID:
5 *
6 * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 12MHz
7 *
8 *
9 * MSP432P401
10 * -----------------
11 * | |
12 * | P1.4|-> FLASH_SPI_CSN (GPIO)
13 * | |
14 * | P1.5|-> FLASH_SPI_CLK (UCB0CLK)
15 * | |
16 * | P1.6|-> FLASH_SPI_MOSI_PIN (UCB0SIMO)
17 * | |
18 * | P1.7|<- FLASH_SPI_MISO_PIN (UCB0SOMI)
19 * | |
20 *
21 * Author: B.Martinez
22*******************************************************************************/
23#include "i3mote.h"
24
25
26/* DriverLib Includes */
27#include "driverlib.h"
28
29/* Standard Includes */
30#include <stdint.h>
31#include <stdlib.h>
32#include <stdbool.h>
33#include <stdio.h>
34
35/* Statics */
36static volatile uint8_t RXData = 0;
37static volatile uint8_t RXDataCnt = 0;
38static uint8_t TXData = 0;
39
40#define SYSFREQ 12000000
41
42/* SPI Master Configuration Parameter */
43const eUSCI_SPI_MasterConfig spiMasterConfig =
44{
45 EUSCI_A_SPI_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
46 SYSFREQ, // SMCLK = DCO = 12MHZ
47 100000, // SPICLK = 100kbps
48 EUSCI_A_SPI_MSB_FIRST, // MSB First
49 EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase (Default)
50 EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // High polarity
51 EUSCI_A_SPI_3PIN
52};
53
54
55int main(void)
56{
57 volatile uint32_t ii;
58
59 /* Halting WDT */
60 WDT_A_holdTimer();
61
62 /* Initializes Clock System */
63 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
64 MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
65 MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
66 MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
67 MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
68
69
70 /* LEDS as output */
71 MAP_GPIO_setAsOutputPin(HID_PORT,LEDR|LEDG);
72 MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDR|LEDG);
73
74
75 /* CS Configuring P3.0 as output */
76 MAP_GPIO_setAsOutputPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN);
77 MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN);
78
79 /* SPI */
80 GPIO_setAsPeripheralModuleFunctionInputPin(FLASH_SPI_PORT,
81 FLASH_SPI_CLK_PIN | FLASH_SPI_MISO_PIN | FLASH_SPI_MOSI_PIN, GPIO_PRIMARY_MODULE_FUNCTION);
82
83
84 /* Configuring SPI in 3wire master mode */
85 SPI_initMaster(EUSCI_A2_BASE, &spiMasterConfig);
86
87 /* Enable SPI module */
88 SPI_enableModule(EUSCI_A2_BASE);
89
90 /* Enabling interrupts */
91 SPI_enableInterrupt(EUSCI_A2_BASE, EUSCI_A_SPI_RECEIVE_INTERRUPT);
92 Interrupt_enableInterrupt(INT_EUSCIA2);
93 Interrupt_enableSleepOnIsrExit();
94
95 /* Polling to see if the TX buffer is ready */
96 while (!(SPI_getInterruptStatus(EUSCI_A2_BASE,EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
97
98 // CS
99 MAP_GPIO_setOutputLowOnPin(FLASH_SPI_PORT,FLASH_SPI_CSN_PIN);
100
101 /* Transmitting first command to slave */
102 TXData=0x9E;
103 SPI_transmitData(EUSCI_A2_BASE, TXData);
104
105 //P6OUT |= BIT0;
106 //MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6, LEDG);
107 /* Enabling MASTER interrupts */
108 // MAP_Interrupt_enableMaster();
109
110 while(1)
111 {
112 MAP_PCM_gotoLPM0();
113 }
114
115}
116
117//******************************************************************************
118//
119//This is the EUSCI_A2 interrupt vector service routine.
120//
121//******************************************************************************
122void EUSCIA2_IRQHandler(void)
123{
124 uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_A2_BASE);
125 uint32_t jj;
126
127 SPI_clearInterruptFlag(EUSCI_A2_BASE, status);
128
129 if(status & EUSCI_A_SPI_RECEIVE_INTERRUPT)
130 {
131
132 /* USCI_B0 TX buffer ready? */
133 while (!(SPI_getInterruptStatus(EUSCI_A2_BASE, EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
134
135 RXData = SPI_receiveData(EUSCI_A2_BASE);
136 printf("%i %02X\n",RXDataCnt,RXData);
137
138 switch(RXDataCnt){
139 case 1:
140 if(RXData!=0x20){
141 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
142 exit(-1);
143 }
144 break;
145 case 2:
146 if(RXData!=0x71){
147 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
148 exit(-1);
149 }
150 break;
151 case 3:
152 if(RXData!=0x15){
153 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
154 exit(-1);
155 }
156 break;
157 case 4:
158 if(RXData!=0x10){
159 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
160 exit(-1);
161 }
162 break;
163 }
164
165 RXDataCnt++;
166
167 if(RXDataCnt==5){
168
169 MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_CSN_PIN);
170
171 /* Enable SysTick and Blink Forever */
172 MAP_SysTick_enableModule();
173 MAP_SysTick_setPeriod(SYSFREQ/4);
174 MAP_Interrupt_enableSleepOnIsrExit();
175 MAP_SysTick_enableInterrupt();
176
177 }
178 else{
179 /* Send the next data packet */
180 SPI_transmitData(EUSCI_A2_BASE, ++TXData);
181 }
182
183 /* Delay between transmissions for slave to process information */
184 for(jj=50;jj<50;jj++);
185 }
186}
187
188void SysTick_Handler(void)
189{
190 MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG);
191}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd
deleted file mode 100644
index 346c191..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd
+++ /dev/null
@@ -1,84 +0,0 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c
deleted file mode 100644
index c168bfa..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5*/
6
7#include <stdint.h>
8
9/* Forward declaration of the default fault handlers. */
10static void resetISR(void);
11static void nmiISR(void);
12static void faultISR(void);
13static void defaultISR(void);
14
15
16/* External declaration for the reset handler that is to be called when the */
17/* processor is started */
18extern void _c_int00(void);
19
20/* External declaration for system initialization function */
21extern void SystemInit(void);
22
23/* Linker variable that marks the top of the stack. */
24extern unsigned long __STACK_END;
25
26
27/* External declarations for the interrupt handlers used by the application. */
28// extern void EUSCIB0_IRQHandler (void);
29extern void EUSCIA2_IRQHandler (void);
30extern void SysTick_Handler(void);
31
32/* Interrupt vector table. Note that the proper constructs must be placed on this to */
33/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
34/* the program if located at a start address other than 0. */
35#pragma RETAIN(interruptVectors)
36#pragma DATA_SECTION(interruptVectors, ".intvecs")
37void (* const interruptVectors[])(void) =
38{
39 (void (*)(void))((uint32_t)&__STACK_END),
40 /* The initial stack pointer */
41 resetISR, /* The reset handler */
42 nmiISR, /* The NMI handler */
43 faultISR, /* The hard fault handler */
44 defaultISR, /* The MPU fault handler */
45 defaultISR, /* The bus fault handler */
46 defaultISR, /* The usage fault handler */
47 0, /* Reserved */
48 0, /* Reserved */
49 0, /* Reserved */
50 0, /* Reserved */
51 defaultISR, /* SVCall handler */
52 defaultISR, /* Debug monitor handler */
53 0, /* Reserved */
54 defaultISR, /* The PendSV handler */
55 SysTick_Handler, /* The SysTick handler */
56 defaultISR, /* PSS ISR */
57 defaultISR, /* CS ISR */
58 defaultISR, /* PCM ISR */
59 defaultISR, /* WDT ISR */
60 defaultISR, /* FPU ISR */
61 defaultISR, /* FLCTL ISR */
62 defaultISR, /* COMP0 ISR */
63 defaultISR, /* COMP1 ISR */
64 defaultISR, /* TA0_0 ISR */
65 defaultISR, /* TA0_N ISR */
66 defaultISR, /* TA1_0 ISR */
67 defaultISR, /* TA1_N ISR */
68 defaultISR, /* TA2_0 ISR */
69 defaultISR, /* TA2_N ISR */
70 defaultISR, /* TA3_0 ISR */
71 defaultISR, /* TA3_N ISR */
72 defaultISR, /* EUSCIA0 ISR */
73 defaultISR, /* EUSCIA1 ISR */
74 EUSCIA2_IRQHandler, /* EUSCIA2 ISR */
75 defaultISR, /* EUSCIA3 ISR */
76 defaultISR, /* EUSCIB0 ISR */
77 defaultISR, /* EUSCIB1 ISR */
78 defaultISR, /* EUSCIB2 ISR */
79 defaultISR, /* EUSCIB3 ISR */
80 defaultISR, /* ADC14 ISR */
81 defaultISR, /* T32_INT1 ISR */
82 defaultISR, /* T32_INT2 ISR */
83 defaultISR, /* T32_INTC ISR */
84 defaultISR, /* AES ISR */
85 defaultISR, /* RTC ISR */
86 defaultISR, /* DMA_ERR ISR */
87 defaultISR, /* DMA_INT3 ISR */
88 defaultISR, /* DMA_INT2 ISR */
89 defaultISR, /* DMA_INT1 ISR */
90 defaultISR, /* DMA_INT0 ISR */
91 defaultISR, /* PORT1 ISR */
92 defaultISR, /* PORT2 ISR */
93 defaultISR, /* PORT3 ISR */
94 defaultISR, /* PORT4 ISR */
95 defaultISR, /* PORT5 ISR */
96 defaultISR, /* PORT6 ISR */
97 defaultISR, /* Reserved 41 */
98 defaultISR, /* Reserved 42 */
99 defaultISR, /* Reserved 43 */
100 defaultISR, /* Reserved 44 */
101 defaultISR, /* Reserved 45 */
102 defaultISR, /* Reserved 46 */
103 defaultISR, /* Reserved 47 */
104 defaultISR, /* Reserved 48 */
105 defaultISR, /* Reserved 49 */
106 defaultISR, /* Reserved 50 */
107 defaultISR, /* Reserved 51 */
108 defaultISR, /* Reserved 52 */
109 defaultISR, /* Reserved 53 */
110 defaultISR, /* Reserved 54 */
111 defaultISR, /* Reserved 55 */
112 defaultISR, /* Reserved 56 */
113 defaultISR, /* Reserved 57 */
114 defaultISR, /* Reserved 58 */
115 defaultISR, /* Reserved 59 */
116 defaultISR, /* Reserved 60 */
117 defaultISR, /* Reserved 61 */
118 defaultISR, /* Reserved 62 */
119 defaultISR /* Reserved 63 */
120};
121
122
123/* This is the code that gets called when the processor first starts execution */
124/* following a reset event. Only the absolutely necessary set is performed, */
125/* after which the application supplied entry() routine is called. Any fancy */
126/* actions (such as making decisions based on the reset cause register, and */
127/* resetting the bits in that register) are left solely in the hands of the */
128/* application. */
129void resetISR(void)
130{
131 SystemInit();
132
133 /* Jump to the CCS C Initialization Routine. */
134 __asm(" .global _c_int00\n"
135 " b.w _c_int00");
136}
137
138/* This is the code that gets called when the processor receives a NMI. This */
139/* simply enters an infinite loop, preserving the system state for examination */
140/* by a debugger. */
141static void nmiISR(void)
142{
143 /* Fault trap exempt from ULP advisor */
144 #pragma diag_push
145 #pragma CHECK_ULP("-2.1")
146
147 /* Enter an infinite loop. */
148 while(1)
149 {
150 }
151
152 #pragma diag_pop
153}
154
155
156/* This is the code that gets called when the processor receives a fault */
157/* interrupt. This simply enters an infinite loop, preserving the system state */
158/* for examination by a debugger. */
159static void faultISR(void)
160{
161 /* Fault trap exempt from ULP advisor */
162 #pragma diag_push
163 #pragma CHECK_ULP("-2.1")
164
165 /* Enter an infinite loop. */
166 while(1)
167 {
168 }
169
170 #pragma diag_pop
171}
172
173
174/* This is the code that gets called when the processor receives an unexpected */
175/* interrupt. This simply enters an infinite loop, preserving the system state */
176/* for examination by a debugger. */
177static void defaultISR(void)
178{
179 /* Fault trap exempt from ULP advisor */
180 #pragma diag_push
181 #pragma CHECK_ULP("-2.1")
182
183 /* Enter an infinite loop. */
184 while(1)
185 {
186 }
187
188 #pragma diag_pop
189}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c
deleted file mode 100644
index 93b5a72..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c
+++ /dev/null
@@ -1,435 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37/**************************************************************************//**
38* @file system_msp432p401r.c
39* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
40* MSP432P401R
41* @version V1.00
42* @date 20-Oct-2015
43*
44* @note View configuration instructions embedded in comments
45*
46******************************************************************************/
47//*****************************************************************************
48//
49// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
50//
51// Redistribution and use in source and binary forms, with or without
52// modification, are permitted provided that the following conditions
53// are met:
54//
55// Redistributions of source code must retain the above copyright
56// notice, this list of conditions and the following disclaimer.
57//
58// Redistributions in binary form must reproduce the above copyright
59// notice, this list of conditions and the following disclaimer in the
60// documentation and/or other materials provided with the
61// distribution.
62//
63// Neither the name of Texas Instruments Incorporated nor the names of
64// its contributors may be used to endorse or promote products derived
65// from this software without specific prior written permission.
66//
67// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
68// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
69// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
70// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
71// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
72// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
74// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
75// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78//
79//*****************************************************************************
80
81#include <stdint.h>
82
83#include "msp.h"
84
85/*--------------------- Configuration Instructions ----------------------------
86 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
87 #define __HALT_WDT 1
88 2. Insert your desired CPU frequency in Hz at:
89 #define __SYSTEM_CLOCK 3000000
90 3. If you prefer the DC-DC power regulator (more efficient at higher
91 frequencies), set the __REGULATOR to 1:
92 #define __REGULATOR 1
93 *---------------------------------------------------------------------------*/
94
95/*--------------------- Watchdog Timer Configuration ------------------------*/
96// Halt the Watchdog Timer
97// <0> Do not halt the WDT
98// <1> Halt the WDT
99#define __HALT_WDT 1
100
101/*--------------------- CPU Frequency Configuration -------------------------*/
102// CPU Frequency
103// <1500000> 1.5 MHz
104// <3000000> 3 MHz
105// <12000000> 12 MHz
106// <24000000> 24 MHz
107// <48000000> 48 MHz
108#define __SYSTEM_CLOCK 1500000
109
110/*--------------------- Power Regulator Configuration -----------------------*/
111// Power Regulator Mode
112// <0> LDO
113// <1> DC-DC
114#define __REGULATOR 1
115
116/*----------------------------------------------------------------------------
117 Define clocks, used for SystemCoreClockUpdate()
118 *---------------------------------------------------------------------------*/
119#define __VLOCLK 10000
120#define __MODCLK 24000000
121#define __LFXT 32768
122#define __HFXT 48000000
123
124/*----------------------------------------------------------------------------
125 Clock Variable definitions
126 *---------------------------------------------------------------------------*/
127uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
128
129/**
130 * Update SystemCoreClock variable
131 *
132 * @param none
133 * @return none
134 *
135 * @brief Updates the SystemCoreClock with current core Clock
136 * retrieved from cpu registers.
137 */
138void SystemCoreClockUpdate(void)
139{
140 uint32_t source, divider;
141 uint8_t dividerValue;
142
143 float dcoConst;
144 int32_t calVal;
145 uint32_t centeredFreq;
146 int16_t dcoTune;
147
148 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
149 dividerValue = 1 << divider;
150 source = CS->CTL1 & CS_CTL1_SELM_MASK;
151
152 switch(source)
153 {
154 case CS_CTL1_SELM__LFXTCLK:
155 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
156 {
157 // Clear interrupt flag
158 CS->KEY = CS_KEY_VAL;
159 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
160 CS->KEY = 1;
161
162 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
163 {
164 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
165 {
166 SystemCoreClock = (128000 / dividerValue);
167 }
168 else
169 {
170 SystemCoreClock = (32000 / dividerValue);
171 }
172 }
173 else
174 {
175 SystemCoreClock = __LFXT / dividerValue;
176 }
177 }
178 else
179 {
180 SystemCoreClock = __LFXT / dividerValue;
181 }
182 break;
183 case CS_CTL1_SELM__VLOCLK:
184 SystemCoreClock = __VLOCLK / dividerValue;
185 break;
186 case CS_CTL1_SELM__REFOCLK:
187 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
188 {
189 SystemCoreClock = (128000 / dividerValue);
190 }
191 else
192 {
193 SystemCoreClock = (32000 / dividerValue);
194 }
195 break;
196 case CS_CTL1_SELM__DCOCLK:
197 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
198
199 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
200 {
201 case CS_CTL0_DCORSEL_0:
202 centeredFreq = 1500000;
203 break;
204 case CS_CTL0_DCORSEL_1:
205 centeredFreq = 3000000;
206 break;
207 case CS_CTL0_DCORSEL_2:
208 centeredFreq = 6000000;
209 break;
210 case CS_CTL0_DCORSEL_3:
211 centeredFreq = 12000000;
212 break;
213 case CS_CTL0_DCORSEL_4:
214 centeredFreq = 24000000;
215 break;
216 case CS_CTL0_DCORSEL_5:
217 centeredFreq = 48000000;
218 break;
219 }
220
221 if(dcoTune == 0)
222 {
223 SystemCoreClock = centeredFreq;
224 }
225 else
226 {
227
228 if(dcoTune & 0x1000)
229 {
230 dcoTune = dcoTune | 0xF000;
231 }
232
233 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
234 {
235 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
236 calVal = TLV->DCOER_FCAL_RSEL04;
237 }
238 /* Internal Resistor */
239 else
240 {
241 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
242 calVal = TLV->DCOIR_FCAL_RSEL04;
243 }
244
245 SystemCoreClock = (uint32_t) ((centeredFreq)
246 / (1
247 - ((dcoConst * dcoTune)
248 / (8 * (1 + dcoConst * (768 - calVal))))));
249 }
250 break;
251 case CS_CTL1_SELM__MODOSC:
252 SystemCoreClock = __MODCLK / dividerValue;
253 break;
254 case CS_CTL1_SELM__HFXTCLK:
255 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
256 {
257 // Clear interrupt flag
258 CS->KEY = CS_KEY_VAL;
259 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
260 CS->KEY = 1;
261
262 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
263 {
264 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
265 {
266 SystemCoreClock = (128000 / dividerValue);
267 }
268 else
269 {
270 SystemCoreClock = (32000 / dividerValue);
271 }
272 }
273 else
274 {
275 SystemCoreClock = __HFXT / dividerValue;
276 }
277 }
278 else
279 {
280 SystemCoreClock = __HFXT / dividerValue;
281 }
282 break;
283 }
284}
285
286/**
287 * Initialize the system
288 *
289 * @param none
290 * @return none
291 *
292 * @brief Setup the microcontroller system.
293 *
294 * Performs the following initialization steps:
295 * 1. Enables the FPU
296 * 2. Halts the WDT if requested
297 * 3. Enables all SRAM banks
298 * 4. Sets up power regulator and VCORE
299 * 5. Enable Flash wait states if needed
300 * 6. Change MCLK to desired frequency
301 * 7. Enable Flash read buffering
302 */
303void SystemInit(void)
304{
305 // Enable FPU if used
306 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
307 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
308 (3UL << 11 * 2)); /* Set CP11 Full Access */
309 #endif
310
311 #if (__HALT_WDT == 1)
312 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
313 #endif
314
315 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
316
317 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
318 // Default VCORE is LDO VCORE0 so no change necessary
319
320 // Switches LDO VCORE0 to DCDC VCORE0 if requested
321 #if __REGULATOR
322 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
323 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
324 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
325 #endif
326
327 // No flash wait states necessary
328
329 // DCO = 1.5 MHz; MCLK = source
330 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
331 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
332 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
333 CS->KEY = 0;
334
335 // Set Flash Bank read buffering
336 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
337 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
338
339 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
340 // Default VCORE is LDO VCORE0 so no change necessary
341
342 // Switches LDO VCORE0 to DCDC VCORE0 if requested
343 #if __REGULATOR
344 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
345 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
346 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
347 #endif
348
349 // No flash wait states necessary
350
351 // DCO = 3 MHz; MCLK = source
352 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
353 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
354 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
355 CS->KEY = 0;
356
357 // Set Flash Bank read buffering
358 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
359 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
360
361 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
362 // Default VCORE is LDO VCORE0 so no change necessary
363
364 // Switches LDO VCORE0 to DCDC VCORE0 if requested
365 #if __REGULATOR
366 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
367 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
368 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
369 #endif
370
371 // No flash wait states necessary
372
373 // DCO = 12 MHz; MCLK = source
374 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
375 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
376 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
377 CS->KEY = 0;
378
379 // Set Flash Bank read buffering
380 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
381 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
382
383 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
384 // Default VCORE is LDO VCORE0 so no change necessary
385
386 // Switches LDO VCORE0 to DCDC VCORE0 if requested
387 #if __REGULATOR
388 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
389 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
390 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
391 #endif
392
393 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
394 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
395 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
396
397 // DCO = 24 MHz; MCLK = source
398 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
399 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
400 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
401 CS->KEY = 0;
402
403 // Set Flash Bank read buffering
404 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
405 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
406
407 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
408 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
409 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
410 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
411 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
412
413 // Switches LDO VCORE1 to DCDC VCORE1 if requested
414 #if __REGULATOR
415 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
416 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
417 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
418 #endif
419
420 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
421 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
422 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
423
424 // DCO = 48 MHz; MCLK = source
425 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
426 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
427 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
428 CS->KEY = 0;
429
430 // Set Flash Bank read buffering
431 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
432 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
433 #endif
434
435}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h
deleted file mode 100644
index e27c845..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/i3mote.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* HID Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7/* Rev.A
8#define HID_PORT GPIO_PORT_P8
9#define LEDR GPIO_PIN5
10#define LEDG GPIO_PIN6
11#define BUTTON GPIO_PIN7
12*/
13
14/* Power Control */
15#define CTL_PWR_PORT GPIO_PORT_P2
16#define GPS_PWR_nEN_PIN GPIO_PIN4
17#define SSM_PWR_nEN_PIN GPIO_PIN5
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
26/* Flash SPI */
27#define FLASH_SPI_PORT GPIO_PORT_P3
28#define FLASH_SPI_CSN_PIN GPIO_PIN0
29#define FLASH_SPI_CLK_PIN GPIO_PIN1
30#define FLASH_SPI_MISO_PIN GPIO_PIN2
31#define FLASH_SPI_MOSI_PIN GPIO_PIN3
32
33
34/* CC2650 SPI */
35#define CC2650_SPI_PORT GPIO_PORT_P2
36#define CC2650_SPI_CSN_PIN GPIO_PIN0
37#define CC2650_SPI_CLK_PIN GPIO_PIN1
38#define CC2650_SPI_MISO_PIN GPIO_PIN2
39#define CC2650_SPI_MOSI_PIN GPIO_PIN3
40
41#define CC2650_IRQ_PORT GPIO_PORT_P4
42#define CC2650_IRQ_PIN GPIO_PIN0
43
44/* On Board EEPROM 25xx256*/
45#define EEPROM_SLAVE_ADDRESS 0x50
46
47
48/* On Board Sensors */
49#define IN219
50#define OPT3001
51#define HDC1080
52#define BMP280
53#define MPU9250
54#define TMP007
55
56#define Board_HDC1080_ADDR 0x40
57#define Board_INA219_ADDR 0x41
58#define Board_TMP007_ADDR 0x44
59#define Board_OPT3001_ADDR 0x45
60#define Board_MPU9250_ADDR 0x68
61#define Board_BMP280_ADDR 0x77
62
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c
deleted file mode 100644
index a86aee1..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/main.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/******************************************************************************
2 * MSP432 SPI - 3-wire Slave Echo
3 *
4 * This example shows how SPI slave echoes to SPI master using 3-wire mode.
5 *
6 * Incrementing data is sent by the master starting at 0x01. Received data is
7 * expected to be same as the previous transmission. eUSCI RX ISR is used to
8 * handle communication with the CPU, normally in LPM0.
9 *
10 * Transactions are started by the slave (MSP432) through IRQ line.
11 *
12 * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 12MHz
13 *
14 * MSP432P401
15 * -----------------
16 * | |
17 * | P2.3|<- Data In (UCA1SIMO)
18 * | |
19 * | P2.2|-> Data Out (UCA1SOMI)
20 * | |
21 * | P2.1|<- Serial Clock Out (UCA1CLK)
22 * | |
23 * | P2.0|<- CS
24 * | |
25 *
26 * Use with Test_CC2650_3wSPI_Master_MSP432_SlaveIRQ
27 *
28 * I3Mote: B.Martinez
29*******************************************************************************/
30
31#include "i3mote.h"
32
33/* DriverLib Includes */
34#include "driverlib.h"
35
36/* Standard Includes */
37#include <stdint.h>
38#include <stdbool.h>
39#include <stdio.h>
40
41//#define DEBUG_UART
42#define UART_BAUD_115200
43
44/* Statics */
45static volatile uint8_t RXData = 0;
46static volatile uint8_t RXDataCnt = 0;
47
48static volatile uint8_t TXData = 0;
49
50const eUSCI_SPI_SlaveConfig spiSlaveConfig =
51{
52 EUSCI_B_SPI_MSB_FIRST, // MSB First
53 EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase
54 EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // Normal Polarity
55 EUSCI_B_SPI_3PIN // 3wire mode
56};
57
58/* UART Configuration Parameter. These are the configuration parameters to
59 * make the eUSCI A UART module to operate with a 9600 baud rate.
60 * These values were calculated using the online calculator that TI provides at:
61 * http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
62 */
63#ifdef UART_BAUD_9600
64 const eUSCI_UART_Config uartConfig =
65 {
66 EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
67 78, // BRDIV = 78
68 2, // UCxBRF = 2
69 0, // UCxBRS = 0
70 EUSCI_A_UART_NO_PARITY, // No Parity
71 EUSCI_A_UART_LSB_FIRST, // LSB First
72 EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
73 EUSCI_A_UART_MODE, // UART mode
74 EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
75 };
76#endif
77
78#ifdef UART_BAUD_115200
79 const eUSCI_UART_Config uartConfig =
80 {
81 EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
82 6, // BRDIV = 78
83 8, // UCxBRF = 2
84 0, // UCxBRS = 0
85 EUSCI_A_UART_NO_PARITY, // No Parity
86 EUSCI_A_UART_LSB_FIRST, // LSB First
87 EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
88 EUSCI_A_UART_MODE, // UART mode
89 EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
90 };
91#endif
92
93
94int main(void)
95{
96 volatile uint32_t ii;
97
98 /* Halting WDT */
99 WDT_A_holdTimer();
100
101 /* Set LED Pins as Output */
102 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
103 MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDG|LEDR);
104
105 /* Setting DCO to 12MHz */
106 CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
107
108 /******************************************************************************/
109 /******************************************************************************/
110
111 /* Configure INT Pin */
112 MAP_GPIO_setOutputHighOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN);
113 MAP_GPIO_setAsOutputPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN);
114
115 /* CS Configuring P2.0 as Input */
116 MAP_GPIO_setAsInputPin(CC2650_SPI_PORT, CC2650_SPI_CSN_PIN);
117
118 /* Selecting P2.1, P2.2 and P2.3 in SPI mode */
119 GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P2,
120 CC2650_SPI_CLK_PIN | CC2650_SPI_MOSI_PIN | CC2650_SPI_MISO_PIN, GPIO_PRIMARY_MODULE_FUNCTION);
121
122 /* Configuring SPI in 3wire master mode */
123 //SPI_initMaster(EUSCI_A1_BASE, &spiMasterConfig);
124 SPI_initSlave(EUSCI_A1_BASE, &spiSlaveConfig);
125
126 /* Enable SPI module */
127 SPI_enableModule(EUSCI_A1_BASE);
128
129 /* Enabling interrupts */
130 SPI_enableInterrupt(EUSCI_A1_BASE, EUSCI_A_SPI_RECEIVE_INTERRUPT);
131 Interrupt_enableSleepOnIsrExit();
132 Interrupt_enableInterrupt(INT_EUSCIA1);
133 MAP_Interrupt_enableMaster();
134
135 /******************************************************************************/
136 /******************************************************************************/
137
138 MAP_SysTick_enableModule();
139 MAP_SysTick_setPeriod(12000000);
140 MAP_Interrupt_enableSleepOnIsrExit();
141 MAP_SysTick_enableInterrupt();
142
143 /******************************************************************************/
144 /******************************************************************************/
145
146#ifdef DEBUG_UART
147
148 /* Selecting P1.2 and P1.3 in UART mode */
149 MAP_GPIO_setAsPeripheralModuleFunctionInputPin(UART_PORT,
150 UART_RX_PIN | UART_TX_PIN, GPIO_PRIMARY_MODULE_FUNCTION);
151
152 /* Configuring UART Module */
153 MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig);
154
155 /* Enable UART module */
156 MAP_UART_enableModule(EUSCI_A0_BASE);
157
158 /* Enabling UART interrupts */
159 /*
160 * MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT);
161 * MAP_Interrupt_enableInterrupt(INT_EUSCIA0);
162 */
163#endif
164
165 /******************************************************************************/
166 /******************************************************************************/
167
168
169 PCM_gotoLPM0();
170 __no_operation();
171}
172
173//******************************************************************************
174//
175//This is the EUSCI_A1 interrupt vector service routine.
176//
177//******************************************************************************
178void EUSCIA1_IRQHandler(void)
179{
180
181 int i;
182
183 uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_A1_BASE);
184
185 SPI_clearInterruptFlag(EUSCI_A1_BASE, status);
186
187 if(status & EUSCI_A_SPI_RECEIVE_INTERRUPT)
188 {
189
190 MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6,GPIO_PIN3);
191
192 RXData = SPI_receiveData(EUSCI_A1_BASE);
193 RXDataCnt++;
194
195 printf("Cnt: %d Rx: %02X\n",RXDataCnt,RXData);
196
197 /* Extrenal UART Debug */
198 #ifdef DEBUG_UART
199 MAP_UART_transmitData(EUSCI_A0_BASE, TXData);
200 MAP_UART_transmitData(EUSCI_A0_BASE, RXData);
201 #endif
202
203 /* Send the next data packet */
204
205 /* USCI_A1 TX buffer ready? */
206 while (!(SPI_getInterruptStatus(EUSCI_A1_BASE, EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
207
208 SPI_transmitData(EUSCI_A1_BASE, RXData);
209
210 for(i=0;i<20000;i++);
211 MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6,GPIO_PIN3);
212
213 }
214}
215
216
217void SysTick_Handler(void)
218{
219 int i;
220 /* Generate Periodic Interrupt */
221 MAP_GPIO_setOutputLowOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN);
222 for(i=0;i<10000;i++);
223 MAP_GPIO_setOutputHighOnPin(CC2650_IRQ_PORT, CC2650_IRQ_PIN);
224
225 //MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6, GPIO_PIN2);
226
227}
228
229//******************************************************************************
230/* EUSCI A0 UART ISR - Echoes data back to PC host */
231//******************************************************************************
232/*
233 *
234 * void EUSCIA0_IRQHandler(void)
235 * {
236 * uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE);
237 *
238 * MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status);
239 *
240 * if(status & EUSCI_A_UART_RECEIVE_INTERRUPT)
241 * {
242 * MAP_UART_transmitData(EUSCI_A0_BASE, MAP_UART_receiveData(EUSCI_A0_BASE));
243 * }
244 *
245 * }
246 *
247 */
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd
deleted file mode 100644
index 346c191..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/msp432p401r.cmd
+++ /dev/null
@@ -1,84 +0,0 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c
deleted file mode 100644
index 47af010..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/startup_msp432p401r_ccs.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5*/
6
7#include <stdint.h>
8
9/* Forward declaration of the default fault handlers. */
10static void resetISR(void);
11static void nmiISR(void);
12static void faultISR(void);
13static void defaultISR(void);
14
15
16/* External declaration for the reset handler that is to be called when the */
17/* processor is started */
18extern void _c_int00(void);
19
20/* External declaration for system initialization function */
21extern void SystemInit(void);
22
23/* Linker variable that marks the top of the stack. */
24extern unsigned long __STACK_END;
25
26
27/* External declarations for the interrupt handlers used by the application. */
28extern void EUSCIA1_IRQHandler (void);
29extern void EUSCIA0_IRQHandler (void);
30extern void SysTick_Handler (void);
31
32/* Interrupt vector table. Note that the proper constructs must be placed on this to */
33/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
34/* the program if located at a start address other than 0. */
35#pragma RETAIN(interruptVectors)
36#pragma DATA_SECTION(interruptVectors, ".intvecs")
37void (* const interruptVectors[])(void) =
38{
39 (void (*)(void))((uint32_t)&__STACK_END),
40 /* The initial stack pointer */
41 resetISR, /* The reset handler */
42 nmiISR, /* The NMI handler */
43 faultISR, /* The hard fault handler */
44 defaultISR, /* The MPU fault handler */
45 defaultISR, /* The bus fault handler */
46 defaultISR, /* The usage fault handler */
47 0, /* Reserved */
48 0, /* Reserved */
49 0, /* Reserved */
50 0, /* Reserved */
51 defaultISR, /* SVCall handler */
52 defaultISR, /* Debug monitor handler */
53 0, /* Reserved */
54 defaultISR, /* The PendSV handler */
55 SysTick_Handler, /* The SysTick handler */
56 defaultISR, /* PSS ISR */
57 defaultISR, /* CS ISR */
58 defaultISR, /* PCM ISR */
59 defaultISR, /* WDT ISR */
60 defaultISR, /* FPU ISR */
61 defaultISR, /* FLCTL ISR */
62 defaultISR, /* COMP0 ISR */
63 defaultISR, /* COMP1 ISR */
64 defaultISR, /* TA0_0 ISR */
65 defaultISR, /* TA0_N ISR */
66 defaultISR, /* TA1_0 ISR */
67 defaultISR, /* TA1_N ISR */
68 defaultISR, /* TA2_0 ISR */
69 defaultISR, /* TA2_N ISR */
70 defaultISR, /* TA3_0 ISR */
71 defaultISR, /* TA3_N ISR */
72 defaultISR, /* EUSCIA0 ISR */
73 EUSCIA1_IRQHandler, /* EUSCIA1 ISR */
74 defaultISR, /* EUSCIA2 ISR */
75 defaultISR, /* EUSCIA3 ISR */
76 defaultISR, /* EUSCIB0 ISR */
77 defaultISR, /* EUSCIB1 ISR */
78 defaultISR, /* EUSCIB2 ISR */
79 defaultISR, /* EUSCIB3 ISR */
80 defaultISR, /* ADC14 ISR */
81 defaultISR, /* T32_INT1 ISR */
82 defaultISR, /* T32_INT2 ISR */
83 defaultISR, /* T32_INTC ISR */
84 defaultISR, /* AES ISR */
85 defaultISR, /* RTC ISR */
86 defaultISR, /* DMA_ERR ISR */
87 defaultISR, /* DMA_INT3 ISR */
88 defaultISR, /* DMA_INT2 ISR */
89 defaultISR, /* DMA_INT1 ISR */
90 defaultISR, /* DMA_INT0 ISR */
91 defaultISR, /* PORT1 ISR */
92 defaultISR, /* PORT2 ISR */
93 defaultISR, /* PORT3 ISR */
94 defaultISR, /* PORT4 ISR */
95 defaultISR, /* PORT5 ISR */
96 defaultISR, /* PORT6 ISR */
97 defaultISR, /* Reserved 41 */
98 defaultISR, /* Reserved 42 */
99 defaultISR, /* Reserved 43 */
100 defaultISR, /* Reserved 44 */
101 defaultISR, /* Reserved 45 */
102 defaultISR, /* Reserved 46 */
103 defaultISR, /* Reserved 47 */
104 defaultISR, /* Reserved 48 */
105 defaultISR, /* Reserved 49 */
106 defaultISR, /* Reserved 50 */
107 defaultISR, /* Reserved 51 */
108 defaultISR, /* Reserved 52 */
109 defaultISR, /* Reserved 53 */
110 defaultISR, /* Reserved 54 */
111 defaultISR, /* Reserved 55 */
112 defaultISR, /* Reserved 56 */
113 defaultISR, /* Reserved 57 */
114 defaultISR, /* Reserved 58 */
115 defaultISR, /* Reserved 59 */
116 defaultISR, /* Reserved 60 */
117 defaultISR, /* Reserved 61 */
118 defaultISR, /* Reserved 62 */
119 defaultISR /* Reserved 63 */
120};
121
122
123/* This is the code that gets called when the processor first starts execution */
124/* following a reset event. Only the absolutely necessary set is performed, */
125/* after which the application supplied entry() routine is called. Any fancy */
126/* actions (such as making decisions based on the reset cause register, and */
127/* resetting the bits in that register) are left solely in the hands of the */
128/* application. */
129void resetISR(void)
130{
131 SystemInit();
132
133 /* Jump to the CCS C Initialization Routine. */
134 __asm(" .global _c_int00\n"
135 " b.w _c_int00");
136}
137
138/* This is the code that gets called when the processor receives a NMI. This */
139/* simply enters an infinite loop, preserving the system state for examination */
140/* by a debugger. */
141static void nmiISR(void)
142{
143 /* Fault trap exempt from ULP advisor */
144 #pragma diag_push
145 #pragma CHECK_ULP("-2.1")
146
147 /* Enter an infinite loop. */
148 while(1)
149 {
150 }
151
152 #pragma diag_pop
153}
154
155
156/* This is the code that gets called when the processor receives a fault */
157/* interrupt. This simply enters an infinite loop, preserving the system state */
158/* for examination by a debugger. */
159static void faultISR(void)
160{
161 /* Fault trap exempt from ULP advisor */
162 #pragma diag_push
163 #pragma CHECK_ULP("-2.1")
164
165 /* Enter an infinite loop. */
166 while(1)
167 {
168 }
169
170 #pragma diag_pop
171}
172
173
174/* This is the code that gets called when the processor receives an unexpected */
175/* interrupt. This simply enters an infinite loop, preserving the system state */
176/* for examination by a debugger. */
177static void defaultISR(void)
178{
179 /* Fault trap exempt from ULP advisor */
180 #pragma diag_push
181 #pragma CHECK_ULP("-2.1")
182
183 /* Enter an infinite loop. */
184 while(1)
185 {
186 }
187
188 #pragma diag_pop
189}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c
deleted file mode 100644
index 93b5a72..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_SlaveIRQ_CC2650_Master/system_msp432p401r.c
+++ /dev/null
@@ -1,435 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37/**************************************************************************//**
38* @file system_msp432p401r.c
39* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
40* MSP432P401R
41* @version V1.00
42* @date 20-Oct-2015
43*
44* @note View configuration instructions embedded in comments
45*
46******************************************************************************/
47//*****************************************************************************
48//
49// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
50//
51// Redistribution and use in source and binary forms, with or without
52// modification, are permitted provided that the following conditions
53// are met:
54//
55// Redistributions of source code must retain the above copyright
56// notice, this list of conditions and the following disclaimer.
57//
58// Redistributions in binary form must reproduce the above copyright
59// notice, this list of conditions and the following disclaimer in the
60// documentation and/or other materials provided with the
61// distribution.
62//
63// Neither the name of Texas Instruments Incorporated nor the names of
64// its contributors may be used to endorse or promote products derived
65// from this software without specific prior written permission.
66//
67// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
68// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
69// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
70// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
71// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
72// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
74// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
75// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78//
79//*****************************************************************************
80
81#include <stdint.h>
82
83#include "msp.h"
84
85/*--------------------- Configuration Instructions ----------------------------
86 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
87 #define __HALT_WDT 1
88 2. Insert your desired CPU frequency in Hz at:
89 #define __SYSTEM_CLOCK 3000000
90 3. If you prefer the DC-DC power regulator (more efficient at higher
91 frequencies), set the __REGULATOR to 1:
92 #define __REGULATOR 1
93 *---------------------------------------------------------------------------*/
94
95/*--------------------- Watchdog Timer Configuration ------------------------*/
96// Halt the Watchdog Timer
97// <0> Do not halt the WDT
98// <1> Halt the WDT
99#define __HALT_WDT 1
100
101/*--------------------- CPU Frequency Configuration -------------------------*/
102// CPU Frequency
103// <1500000> 1.5 MHz
104// <3000000> 3 MHz
105// <12000000> 12 MHz
106// <24000000> 24 MHz
107// <48000000> 48 MHz
108#define __SYSTEM_CLOCK 1500000
109
110/*--------------------- Power Regulator Configuration -----------------------*/
111// Power Regulator Mode
112// <0> LDO
113// <1> DC-DC
114#define __REGULATOR 1
115
116/*----------------------------------------------------------------------------
117 Define clocks, used for SystemCoreClockUpdate()
118 *---------------------------------------------------------------------------*/
119#define __VLOCLK 10000
120#define __MODCLK 24000000
121#define __LFXT 32768
122#define __HFXT 48000000
123
124/*----------------------------------------------------------------------------
125 Clock Variable definitions
126 *---------------------------------------------------------------------------*/
127uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
128
129/**
130 * Update SystemCoreClock variable
131 *
132 * @param none
133 * @return none
134 *
135 * @brief Updates the SystemCoreClock with current core Clock
136 * retrieved from cpu registers.
137 */
138void SystemCoreClockUpdate(void)
139{
140 uint32_t source, divider;
141 uint8_t dividerValue;
142
143 float dcoConst;
144 int32_t calVal;
145 uint32_t centeredFreq;
146 int16_t dcoTune;
147
148 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
149 dividerValue = 1 << divider;
150 source = CS->CTL1 & CS_CTL1_SELM_MASK;
151
152 switch(source)
153 {
154 case CS_CTL1_SELM__LFXTCLK:
155 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
156 {
157 // Clear interrupt flag
158 CS->KEY = CS_KEY_VAL;
159 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
160 CS->KEY = 1;
161
162 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
163 {
164 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
165 {
166 SystemCoreClock = (128000 / dividerValue);
167 }
168 else
169 {
170 SystemCoreClock = (32000 / dividerValue);
171 }
172 }
173 else
174 {
175 SystemCoreClock = __LFXT / dividerValue;
176 }
177 }
178 else
179 {
180 SystemCoreClock = __LFXT / dividerValue;
181 }
182 break;
183 case CS_CTL1_SELM__VLOCLK:
184 SystemCoreClock = __VLOCLK / dividerValue;
185 break;
186 case CS_CTL1_SELM__REFOCLK:
187 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
188 {
189 SystemCoreClock = (128000 / dividerValue);
190 }
191 else
192 {
193 SystemCoreClock = (32000 / dividerValue);
194 }
195 break;
196 case CS_CTL1_SELM__DCOCLK:
197 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
198
199 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
200 {
201 case CS_CTL0_DCORSEL_0:
202 centeredFreq = 1500000;
203 break;
204 case CS_CTL0_DCORSEL_1:
205 centeredFreq = 3000000;
206 break;
207 case CS_CTL0_DCORSEL_2:
208 centeredFreq = 6000000;
209 break;
210 case CS_CTL0_DCORSEL_3:
211 centeredFreq = 12000000;
212 break;
213 case CS_CTL0_DCORSEL_4:
214 centeredFreq = 24000000;
215 break;
216 case CS_CTL0_DCORSEL_5:
217 centeredFreq = 48000000;
218 break;
219 }
220
221 if(dcoTune == 0)
222 {
223 SystemCoreClock = centeredFreq;
224 }
225 else
226 {
227
228 if(dcoTune & 0x1000)
229 {
230 dcoTune = dcoTune | 0xF000;
231 }
232
233 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
234 {
235 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
236 calVal = TLV->DCOER_FCAL_RSEL04;
237 }
238 /* Internal Resistor */
239 else
240 {
241 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
242 calVal = TLV->DCOIR_FCAL_RSEL04;
243 }
244
245 SystemCoreClock = (uint32_t) ((centeredFreq)
246 / (1
247 - ((dcoConst * dcoTune)
248 / (8 * (1 + dcoConst * (768 - calVal))))));
249 }
250 break;
251 case CS_CTL1_SELM__MODOSC:
252 SystemCoreClock = __MODCLK / dividerValue;
253 break;
254 case CS_CTL1_SELM__HFXTCLK:
255 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
256 {
257 // Clear interrupt flag
258 CS->KEY = CS_KEY_VAL;
259 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
260 CS->KEY = 1;
261
262 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
263 {
264 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
265 {
266 SystemCoreClock = (128000 / dividerValue);
267 }
268 else
269 {
270 SystemCoreClock = (32000 / dividerValue);
271 }
272 }
273 else
274 {
275 SystemCoreClock = __HFXT / dividerValue;
276 }
277 }
278 else
279 {
280 SystemCoreClock = __HFXT / dividerValue;
281 }
282 break;
283 }
284}
285
286/**
287 * Initialize the system
288 *
289 * @param none
290 * @return none
291 *
292 * @brief Setup the microcontroller system.
293 *
294 * Performs the following initialization steps:
295 * 1. Enables the FPU
296 * 2. Halts the WDT if requested
297 * 3. Enables all SRAM banks
298 * 4. Sets up power regulator and VCORE
299 * 5. Enable Flash wait states if needed
300 * 6. Change MCLK to desired frequency
301 * 7. Enable Flash read buffering
302 */
303void SystemInit(void)
304{
305 // Enable FPU if used
306 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
307 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
308 (3UL << 11 * 2)); /* Set CP11 Full Access */
309 #endif
310
311 #if (__HALT_WDT == 1)
312 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
313 #endif
314
315 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
316
317 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
318 // Default VCORE is LDO VCORE0 so no change necessary
319
320 // Switches LDO VCORE0 to DCDC VCORE0 if requested
321 #if __REGULATOR
322 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
323 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
324 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
325 #endif
326
327 // No flash wait states necessary
328
329 // DCO = 1.5 MHz; MCLK = source
330 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
331 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
332 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
333 CS->KEY = 0;
334
335 // Set Flash Bank read buffering
336 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
337 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
338
339 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
340 // Default VCORE is LDO VCORE0 so no change necessary
341
342 // Switches LDO VCORE0 to DCDC VCORE0 if requested
343 #if __REGULATOR
344 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
345 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
346 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
347 #endif
348
349 // No flash wait states necessary
350
351 // DCO = 3 MHz; MCLK = source
352 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
353 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
354 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
355 CS->KEY = 0;
356
357 // Set Flash Bank read buffering
358 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
359 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
360
361 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
362 // Default VCORE is LDO VCORE0 so no change necessary
363
364 // Switches LDO VCORE0 to DCDC VCORE0 if requested
365 #if __REGULATOR
366 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
367 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
368 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
369 #endif
370
371 // No flash wait states necessary
372
373 // DCO = 12 MHz; MCLK = source
374 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
375 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
376 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
377 CS->KEY = 0;
378
379 // Set Flash Bank read buffering
380 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
381 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
382
383 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
384 // Default VCORE is LDO VCORE0 so no change necessary
385
386 // Switches LDO VCORE0 to DCDC VCORE0 if requested
387 #if __REGULATOR
388 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
389 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
390 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
391 #endif
392
393 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
394 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
395 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
396
397 // DCO = 24 MHz; MCLK = source
398 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
399 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
400 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
401 CS->KEY = 0;
402
403 // Set Flash Bank read buffering
404 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
405 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
406
407 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
408 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
409 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
410 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
411 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
412
413 // Switches LDO VCORE1 to DCDC VCORE1 if requested
414 #if __REGULATOR
415 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
416 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
417 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
418 #endif
419
420 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
421 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
422 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
423
424 // DCO = 48 MHz; MCLK = source
425 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
426 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
427 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
428 CS->KEY = 0;
429
430 // Set Flash Bank read buffering
431 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
432 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
433 #endif
434
435}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h
deleted file mode 100644
index e27c845..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* HID Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7/* Rev.A
8#define HID_PORT GPIO_PORT_P8
9#define LEDR GPIO_PIN5
10#define LEDG GPIO_PIN6
11#define BUTTON GPIO_PIN7
12*/
13
14/* Power Control */
15#define CTL_PWR_PORT GPIO_PORT_P2
16#define GPS_PWR_nEN_PIN GPIO_PIN4
17#define SSM_PWR_nEN_PIN GPIO_PIN5
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
26/* Flash SPI */
27#define FLASH_SPI_PORT GPIO_PORT_P3
28#define FLASH_SPI_CSN_PIN GPIO_PIN0
29#define FLASH_SPI_CLK_PIN GPIO_PIN1
30#define FLASH_SPI_MISO_PIN GPIO_PIN2
31#define FLASH_SPI_MOSI_PIN GPIO_PIN3
32
33
34/* CC2650 SPI */
35#define CC2650_SPI_PORT GPIO_PORT_P2
36#define CC2650_SPI_CSN_PIN GPIO_PIN0
37#define CC2650_SPI_CLK_PIN GPIO_PIN1
38#define CC2650_SPI_MISO_PIN GPIO_PIN2
39#define CC2650_SPI_MOSI_PIN GPIO_PIN3
40
41#define CC2650_IRQ_PORT GPIO_PORT_P4
42#define CC2650_IRQ_PIN GPIO_PIN0
43
44/* On Board EEPROM 25xx256*/
45#define EEPROM_SLAVE_ADDRESS 0x50
46
47
48/* On Board Sensors */
49#define IN219
50#define OPT3001
51#define HDC1080
52#define BMP280
53#define MPU9250
54#define TMP007
55
56#define Board_HDC1080_ADDR 0x40
57#define Board_INA219_ADDR 0x41
58#define Board_TMP007_ADDR 0x44
59#define Board_OPT3001_ADDR 0x45
60#define Board_MPU9250_ADDR 0x68
61#define Board_BMP280_ADDR 0x77
62
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c
deleted file mode 100644
index 0ad179c..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*******************************************************************************
2 * MSP432 Blink
3 *
4 * Description:
5 * Blinks two LEDs using SysTick (which is sourced from MCLK).
6 *
7 * Configuration:
8 * Starts the DCO to 12MHz and sources MCLK from it.
9 * BT1 pauses blinking.
10 *
11 *
12 * MSP432P401
13 * ------------------
14 * /|\| |
15 * --|RST |
16 * | |---> LEDG
17 * BT1 --->| |---> LEDR
18 * | |
19 * | < 12Mhz DCO > |
20 * | |
21 *
22 * Author: B.Martinez
23 ******************************************************************************/
24#include "i3mote.h"
25
26/* DriverLib Includes */
27#include "driverlib.h"
28
29/* Standard Includes */
30#include <stdint.h>
31#include <stdbool.h>
32
33
34int main(void)
35{
36 /* Halting the Watchdog */
37 MAP_WDT_A_holdTimer();
38
39 /* Set Button Pin as Input */
40 MAP_GPIO_setAsInputPin(HID_PORT,BUTTON);
41
42 /* Set LED Pins as Output */
43 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
44
45 /* Set LED Initial Value */
46 MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDG);
47 MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDR);
48 //MAP_GPIO_setOutputHighOnPin(HID_PORT, LEDR);
49
50 /* Setting the external clock frequency (This API is optional) */
51 CS_setExternalClockSourceFrequency(32000,12000000);
52
53 /* Initializes MCLK Clocks System with DCO */
54 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
55 MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
56
57 /*
58 * Configuring SysTick to trigger at 6000000
59 * MCLK is 12MHz so this will make it toggle every 0.5s
60 */
61 MAP_SysTick_enableModule();
62 MAP_SysTick_setPeriod(6000000);
63 MAP_Interrupt_enableSleepOnIsrExit();
64 MAP_SysTick_enableInterrupt();
65
66 /* Enabling MASTER interrupts */
67 MAP_Interrupt_enableMaster();
68
69 while (1)
70 {
71 MAP_PCM_gotoLPM0();
72 }
73}
74
75void SysTick_Handler(void)
76{
77 if(MAP_GPIO_getInputPinValue(HID_PORT,BUTTON)){
78 MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6, GPIO_PIN2|GPIO_PIN3);
79 }
80}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd
deleted file mode 100644
index 346c191..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd
+++ /dev/null
@@ -1,84 +0,0 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c
deleted file mode 100644
index d5f9a14..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37//*****************************************************************************
38//
39// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
40//
41// Redistribution and use in source and binary forms, with or without
42// modification, are permitted provided that the following conditions
43// are met:
44//
45// Redistributions of source code must retain the above copyright
46// notice, this list of conditions and the following disclaimer.
47//
48// Redistributions in binary form must reproduce the above copyright
49// notice, this list of conditions and the following disclaimer in the
50// documentation and/or other materials provided with the
51// distribution.
52//
53// Neither the name of Texas Instruments Incorporated nor the names of
54// its contributors may be used to endorse or promote products derived
55// from this software without specific prior written permission.
56//
57// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
60// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
63// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
64// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
67// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68//
69// MSP432 Family Interrupt Vector Table for CGT
70//
71//****************************************************************************
72
73#include <stdint.h>
74
75/* Forward declaration of the default fault handlers. */
76static void resetISR(void);
77static void nmiISR(void);
78static void faultISR(void);
79static void defaultISR(void);
80
81
82/* External declaration for the reset handler that is to be called when the */
83/* processor is started */
84extern void _c_int00(void);
85
86/* External declaration for system initialization function */
87extern void SystemInit(void);
88
89/* Linker variable that marks the top of the stack. */
90extern unsigned long __STACK_END;
91
92
93/* External declarations for the interrupt handlers used by the application. */
94extern void SysTick_Handler(void);
95
96
97/* Interrupt vector table. Note that the proper constructs must be placed on this to */
98/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
99/* the program if located at a start address other than 0. */
100#pragma RETAIN(interruptVectors)
101#pragma DATA_SECTION(interruptVectors, ".intvecs")
102void (* const interruptVectors[])(void) =
103{
104 (void (*)(void))((uint32_t)&__STACK_END),
105 /* The initial stack pointer */
106 resetISR, /* The reset handler */
107 nmiISR, /* The NMI handler */
108 faultISR, /* The hard fault handler */
109 defaultISR, /* The MPU fault handler */
110 defaultISR, /* The bus fault handler */
111 defaultISR, /* The usage fault handler */
112 0, /* Reserved */
113 0, /* Reserved */
114 0, /* Reserved */
115 0, /* Reserved */
116 defaultISR, /* SVCall handler */
117 defaultISR, /* Debug monitor handler */
118 0, /* Reserved */
119 defaultISR, /* The PendSV handler */
120 SysTick_Handler, /* The SysTick handler */
121 defaultISR, /* PSS ISR */
122 defaultISR, /* CS ISR */
123 defaultISR, /* PCM ISR */
124 defaultISR, /* WDT ISR */
125 defaultISR, /* FPU ISR */
126 defaultISR, /* FLCTL ISR */
127 defaultISR, /* COMP0 ISR */
128 defaultISR, /* COMP1 ISR */
129 defaultISR, /* TA0_0 ISR */
130 defaultISR, /* TA0_N ISR */
131 defaultISR, /* TA1_0 ISR */
132 defaultISR, /* TA1_N ISR */
133 defaultISR, /* TA2_0 ISR */
134 defaultISR, /* TA2_N ISR */
135 defaultISR, /* TA3_0 ISR */
136 defaultISR, /* TA3_N ISR */
137 defaultISR, /* EUSCIA0 ISR */
138 defaultISR, /* EUSCIA1 ISR */
139 defaultISR, /* EUSCIA2 ISR */
140 defaultISR, /* EUSCIA3 ISR */
141 defaultISR, /* EUSCIB0 ISR */
142 defaultISR, /* EUSCIB1 ISR */
143 defaultISR, /* EUSCIB2 ISR */
144 defaultISR, /* EUSCIB3 ISR */
145 defaultISR, /* ADC14 ISR */
146 defaultISR, /* T32_INT1 ISR */
147 defaultISR, /* T32_INT2 ISR */
148 defaultISR, /* T32_INTC ISR */
149 defaultISR, /* AES ISR */
150 defaultISR, /* RTC ISR */
151 defaultISR, /* DMA_ERR ISR */
152 defaultISR, /* DMA_INT3 ISR */
153 defaultISR, /* DMA_INT2 ISR */
154 defaultISR, /* DMA_INT1 ISR */
155 defaultISR, /* DMA_INT0 ISR */
156 defaultISR, /* PORT1 ISR */
157 defaultISR, /* PORT2 ISR */
158 defaultISR, /* PORT3 ISR */
159 defaultISR, /* PORT4 ISR */
160 defaultISR, /* PORT5 ISR */
161 defaultISR, /* PORT6 ISR */
162 defaultISR, /* Reserved 41 */
163 defaultISR, /* Reserved 42 */
164 defaultISR, /* Reserved 43 */
165 defaultISR, /* Reserved 44 */
166 defaultISR, /* Reserved 45 */
167 defaultISR, /* Reserved 46 */
168 defaultISR, /* Reserved 47 */
169 defaultISR, /* Reserved 48 */
170 defaultISR, /* Reserved 49 */
171 defaultISR, /* Reserved 50 */
172 defaultISR, /* Reserved 51 */
173 defaultISR, /* Reserved 52 */
174 defaultISR, /* Reserved 53 */
175 defaultISR, /* Reserved 54 */
176 defaultISR, /* Reserved 55 */
177 defaultISR, /* Reserved 56 */
178 defaultISR, /* Reserved 57 */
179 defaultISR, /* Reserved 58 */
180 defaultISR, /* Reserved 59 */
181 defaultISR, /* Reserved 60 */
182 defaultISR, /* Reserved 61 */
183 defaultISR, /* Reserved 62 */
184 defaultISR /* Reserved 63 */
185};
186
187
188/* This is the code that gets called when the processor first starts execution */
189/* following a reset event. Only the absolutely necessary set is performed, */
190/* after which the application supplied entry() routine is called. Any fancy */
191/* actions (such as making decisions based on the reset cause register, and */
192/* resetting the bits in that register) are left solely in the hands of the */
193/* application. */
194void resetISR(void)
195{
196 SystemInit();
197
198 /* Jump to the CCS C Initialization Routine. */
199 __asm(" .global _c_int00\n"
200 " b.w _c_int00");
201}
202
203/* This is the code that gets called when the processor receives a NMI. This */
204/* simply enters an infinite loop, preserving the system state for examination */
205/* by a debugger. */
206static void nmiISR(void)
207{
208 /* Fault trap exempt from ULP advisor */
209 #pragma diag_push
210 #pragma CHECK_ULP("-2.1")
211
212 /* Enter an infinite loop. */
213 while(1)
214 {
215 }
216
217 #pragma diag_pop
218}
219
220
221/* This is the code that gets called when the processor receives a fault */
222/* interrupt. This simply enters an infinite loop, preserving the system state */
223/* for examination by a debugger. */
224static void faultISR(void)
225{
226 /* Fault trap exempt from ULP advisor */
227 #pragma diag_push
228 #pragma CHECK_ULP("-2.1")
229
230 /* Enter an infinite loop. */
231 while(1)
232 {
233 }
234
235 #pragma diag_pop
236}
237
238
239/* This is the code that gets called when the processor receives an unexpected */
240/* interrupt. This simply enters an infinite loop, preserving the system state */
241/* for examination by a debugger. */
242static void defaultISR(void)
243{
244 /* Fault trap exempt from ULP advisor */
245 #pragma diag_push
246 #pragma CHECK_ULP("-2.1")
247
248 /* Enter an infinite loop. */
249 while(1)
250 {
251 }
252
253 #pragma diag_pop
254}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c
deleted file mode 100644
index 4dcf1da..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/*
2
3/**************************************************************************//**
4* @file system_msp432p401r.c
5* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
6* MSP432P401R
7* @version V1.00
8* @date 20-Oct-2015
9*
10* @note View configuration instructions embedded in comments
11*
12******************************************************************************/
13
14//*****************************************************************************
15
16#include <stdint.h>
17#include "msp.h"
18
19/*--------------------- Configuration Instructions ----------------------------
20 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
21 #define __HALT_WDT 1
22 2. Insert your desired CPU frequency in Hz at:
23 #define __SYSTEM_CLOCK 3000000
24 3. If you prefer the DC-DC power regulator (more efficient at higher
25 frequencies), set the __REGULATOR to 1:
26 #define __REGULATOR 1
27 *---------------------------------------------------------------------------*/
28
29/*--------------------- Watchdog Timer Configuration ------------------------*/
30// Halt the Watchdog Timer
31// <0> Do not halt the WDT
32// <1> Halt the WDT
33#define __HALT_WDT 1
34
35/*--------------------- CPU Frequency Configuration -------------------------*/
36// CPU Frequency
37// <1500000> 1.5 MHz
38// <3000000> 3 MHz
39// <12000000> 12 MHz
40// <24000000> 24 MHz
41// <48000000> 48 MHz
42#define __SYSTEM_CLOCK 12000000
43
44/*--------------------- Power Regulator Configuration -----------------------*/
45// Power Regulator Mode
46// <0> LDO
47// <1> DC-DC
48#define __REGULATOR 1
49
50/*----------------------------------------------------------------------------
51 Define clocks, used for SystemCoreClockUpdate()
52 *---------------------------------------------------------------------------*/
53#define __VLOCLK 10000
54#define __MODCLK 24000000
55#define __LFXT 32768
56#define __HFXT 48000000
57
58/*----------------------------------------------------------------------------
59 Clock Variable definitions
60 *---------------------------------------------------------------------------*/
61uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
62
63/**
64 * Update SystemCoreClock variable
65 *
66 * @param none
67 * @return none
68 *
69 * @brief Updates the SystemCoreClock with current core Clock
70 * retrieved from cpu registers.
71 */
72void SystemCoreClockUpdate(void)
73{
74 uint32_t source, divider;
75 uint8_t dividerValue;
76
77 float dcoConst;
78 int32_t calVal;
79 uint32_t centeredFreq;
80 int16_t dcoTune;
81
82 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
83 dividerValue = 1 << divider;
84 source = CS->CTL1 & CS_CTL1_SELM_MASK;
85
86 switch(source)
87 {
88 case CS_CTL1_SELM__LFXTCLK:
89 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
90 {
91 // Clear interrupt flag
92 CS->KEY = CS_KEY_VAL;
93 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
94 CS->KEY = 1;
95
96 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
97 {
98 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
99 {
100 SystemCoreClock = (128000 / dividerValue);
101 }
102 else
103 {
104 SystemCoreClock = (32000 / dividerValue);
105 }
106 }
107 else
108 {
109 SystemCoreClock = __LFXT / dividerValue;
110 }
111 }
112 else
113 {
114 SystemCoreClock = __LFXT / dividerValue;
115 }
116 break;
117 case CS_CTL1_SELM__VLOCLK:
118 SystemCoreClock = __VLOCLK / dividerValue;
119 break;
120 case CS_CTL1_SELM__REFOCLK:
121 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
122 {
123 SystemCoreClock = (128000 / dividerValue);
124 }
125 else
126 {
127 SystemCoreClock = (32000 / dividerValue);
128 }
129 break;
130 case CS_CTL1_SELM__DCOCLK:
131 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
132
133 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
134 {
135 case CS_CTL0_DCORSEL_0:
136 centeredFreq = 1500000;
137 break;
138 case CS_CTL0_DCORSEL_1:
139 centeredFreq = 3000000;
140 break;
141 case CS_CTL0_DCORSEL_2:
142 centeredFreq = 6000000;
143 break;
144 case CS_CTL0_DCORSEL_3:
145 centeredFreq = 12000000;
146 break;
147 case CS_CTL0_DCORSEL_4:
148 centeredFreq = 24000000;
149 break;
150 case CS_CTL0_DCORSEL_5:
151 centeredFreq = 48000000;
152 break;
153 }
154
155 if(dcoTune == 0)
156 {
157 SystemCoreClock = centeredFreq;
158 }
159 else
160 {
161
162 if(dcoTune & 0x1000)
163 {
164 dcoTune = dcoTune | 0xF000;
165 }
166
167 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
168 {
169 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
170 calVal = TLV->DCOER_FCAL_RSEL04;
171 }
172 /* Internal Resistor */
173 else
174 {
175 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
176 calVal = TLV->DCOIR_FCAL_RSEL04;
177 }
178
179 SystemCoreClock = (uint32_t) ((centeredFreq)
180 / (1
181 - ((dcoConst * dcoTune)
182 / (8 * (1 + dcoConst * (768 - calVal))))));
183 }
184 break;
185 case CS_CTL1_SELM__MODOSC:
186 SystemCoreClock = __MODCLK / dividerValue;
187 break;
188 case CS_CTL1_SELM__HFXTCLK:
189 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
190 {
191 // Clear interrupt flag
192 CS->KEY = CS_KEY_VAL;
193 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
194 CS->KEY = 1;
195
196 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
197 {
198 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
199 {
200 SystemCoreClock = (128000 / dividerValue);
201 }
202 else
203 {
204 SystemCoreClock = (32000 / dividerValue);
205 }
206 }
207 else
208 {
209 SystemCoreClock = __HFXT / dividerValue;
210 }
211 }
212 else
213 {
214 SystemCoreClock = __HFXT / dividerValue;
215 }
216 break;
217 }
218}
219
220/**
221 * Initialize the system
222 *
223 * @param none
224 * @return none
225 *
226 * @brief Setup the microcontroller system.
227 *
228 * Performs the following initialization steps:
229 * 1. Enables the FPU
230 * 2. Halts the WDT if requested
231 * 3. Enables all SRAM banks
232 * 4. Sets up power regulator and VCORE
233 * 5. Enable Flash wait states if needed
234 * 6. Change MCLK to desired frequency
235 * 7. Enable Flash read buffering
236 */
237void SystemInit(void)
238{
239 // Enable FPU if used
240 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
241 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
242 (3UL << 11 * 2)); /* Set CP11 Full Access */
243 #endif
244
245 #if (__HALT_WDT == 1)
246 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
247 #endif
248
249 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
250
251 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
252 // Default VCORE is LDO VCORE0 so no change necessary
253
254 // Switches LDO VCORE0 to DCDC VCORE0 if requested
255 #if __REGULATOR
256 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
257 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
258 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
259 #endif
260
261 // No flash wait states necessary
262
263 // DCO = 1.5 MHz; MCLK = source
264 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
265 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
266 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
267 CS->KEY = 0;
268
269 // Set Flash Bank read buffering
270 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
271 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
272
273 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
274 // Default VCORE is LDO VCORE0 so no change necessary
275
276 // Switches LDO VCORE0 to DCDC VCORE0 if requested
277 #if __REGULATOR
278 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
279 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
280 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
281 #endif
282
283 // No flash wait states necessary
284
285 // DCO = 3 MHz; MCLK = source
286 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
287 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
288 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
289 CS->KEY = 0;
290
291 // Set Flash Bank read buffering
292 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
293 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
294
295 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
296 // Default VCORE is LDO VCORE0 so no change necessary
297
298 // Switches LDO VCORE0 to DCDC VCORE0 if requested
299 #if __REGULATOR
300 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
301 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
302 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
303 #endif
304
305 // No flash wait states necessary
306
307 // DCO = 12 MHz; MCLK = source
308 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
309 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
310 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
311 CS->KEY = 0;
312
313 // Set Flash Bank read buffering
314 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
315 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
316
317 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
318 // Default VCORE is LDO VCORE0 so no change necessary
319
320 // Switches LDO VCORE0 to DCDC VCORE0 if requested
321 #if __REGULATOR
322 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
323 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
324 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
325 #endif
326
327 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
328 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
329 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
330
331 // DCO = 24 MHz; MCLK = source
332 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
333 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
334 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
335 CS->KEY = 0;
336
337 // Set Flash Bank read buffering
338 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
339 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
340
341 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
342 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
343 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
344 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
345 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
346
347 // Switches LDO VCORE1 to DCDC VCORE1 if requested
348 #if __REGULATOR
349 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
350 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
351 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
352 #endif
353
354 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
355 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
356 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
357
358 // DCO = 48 MHz; MCLK = source
359 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
360 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
361 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
362 CS->KEY = 0;
363
364 // Set Flash Bank read buffering
365 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
366 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
367 #endif
368
369}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h
deleted file mode 100644
index e27c845..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/i3mote.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* HID Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7/* Rev.A
8#define HID_PORT GPIO_PORT_P8
9#define LEDR GPIO_PIN5
10#define LEDG GPIO_PIN6
11#define BUTTON GPIO_PIN7
12*/
13
14/* Power Control */
15#define CTL_PWR_PORT GPIO_PORT_P2
16#define GPS_PWR_nEN_PIN GPIO_PIN4
17#define SSM_PWR_nEN_PIN GPIO_PIN5
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
26/* Flash SPI */
27#define FLASH_SPI_PORT GPIO_PORT_P3
28#define FLASH_SPI_CSN_PIN GPIO_PIN0
29#define FLASH_SPI_CLK_PIN GPIO_PIN1
30#define FLASH_SPI_MISO_PIN GPIO_PIN2
31#define FLASH_SPI_MOSI_PIN GPIO_PIN3
32
33
34/* CC2650 SPI */
35#define CC2650_SPI_PORT GPIO_PORT_P2
36#define CC2650_SPI_CSN_PIN GPIO_PIN0
37#define CC2650_SPI_CLK_PIN GPIO_PIN1
38#define CC2650_SPI_MISO_PIN GPIO_PIN2
39#define CC2650_SPI_MOSI_PIN GPIO_PIN3
40
41#define CC2650_IRQ_PORT GPIO_PORT_P4
42#define CC2650_IRQ_PIN GPIO_PIN0
43
44/* On Board EEPROM 25xx256*/
45#define EEPROM_SLAVE_ADDRESS 0x50
46
47
48/* On Board Sensors */
49#define IN219
50#define OPT3001
51#define HDC1080
52#define BMP280
53#define MPU9250
54#define TMP007
55
56#define Board_HDC1080_ADDR 0x40
57#define Board_INA219_ADDR 0x41
58#define Board_TMP007_ADDR 0x44
59#define Board_OPT3001_ADDR 0x45
60#define Board_MPU9250_ADDR 0x68
61#define Board_BMP280_ADDR 0x77
62
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c
deleted file mode 100644
index e4df695..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/main.c
+++ /dev/null
@@ -1,123 +0,0 @@
1/*******************************************************************************
2 * MSP432 Clock System - HFXT Startup
3 *
4 * Description:
5 *
6 * HFXTAL:
7 * Starts the 48MHz crystal attached to HFXTIN/HFXTOUT
8 * Sources MCLK from the crystal
9 *
10 * LFXTL:
11 * Starts the 32khz crystal attached to LFXTIN/LFXTOUT
12 * Sources AMCLK from crystal
13 *
14 * Internal DCO:
15 * Starts the DCO
16 * Sources SMCLK from DCO
17 *
18 * Blinks LEDs using SysTick (which is sourced from MCLK).
19 *
20 *
21 *
22 * MSP432P401
23 * ------------------
24 * /|\| |
25 * | | |
26 * --|RST P8.5 |---> LED
27 * | |
28 * | PJ.3 HFXTIN |<--------
29 * | | < 48Mhz xTal >
30 * | PJ.2 HFXTOUT |<--------
31 * | |
32 * | PJ.0 LFXIN |<--------
33 * | | < 32khz xTal >
34 * | PJ.1 LFXOUT |<--------
35 * | |
36 * | P4.2 |--> ACLK - 32.768 KHz
37 * | P4.3 |--> MCLK - 12.000 MHz
38 * | P4.4 |--> HSMCLK - 6.000 MHz
39 * | P7.0 |--> SMCLK
40 * | |
41 *
42 * Author: Timothy Logan
43 * Rev: B.Martinez
44 ******************************************************************************/
45#include "i3mote.h"
46
47/* DriverLib Includes */
48#include "driverlib.h"
49
50/* Standard Includes */
51#include <stdint.h>
52#include <stdbool.h>
53
54int main(void)
55{
56 /* Halting the Watchdog */
57 MAP_WDT_A_holdTimer();
58
59 /* Configuring pins for peripheral/crystal usage*/
60 /* LFXTAL */
61 MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_PJ,
62 GPIO_PIN0 | GPIO_PIN1, GPIO_PRIMARY_MODULE_FUNCTION);
63
64 /* HFXTL */
65 MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_PJ,
66 GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION);
67
68 /* Clocks Output */
69 GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P4,
70 GPIO_PIN2|GPIO_PIN3|GPIO_PIN4, GPIO_PRIMARY_MODULE_FUNCTION);
71 GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7,
72 GPIO_PIN0, GPIO_PRIMARY_MODULE_FUNCTION);
73
74 /* LEDs */
75 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
76 MAP_GPIO_setOutputHighOnPin(HID_PORT, LEDG|LEDR);
77
78 /* Setting the external clock frequency. This API is optional */
79 CS_setExternalClockSourceFrequency(32000,12000000);
80
81 /* Starting HFXT in non-bypass mode without a timeout. Before we start
82 * we have to change VCORE to 1 to support the 48MHz frequency */
83 MAP_PCM_setCoreVoltageLevel(PCM_VCORE1);
84 MAP_FlashCtl_setWaitState(FLASH_BANK0, 2);
85 MAP_FlashCtl_setWaitState(FLASH_BANK1, 2);
86 CS_startHFXT(false);
87
88 /* Initializing MCLK to HFXT (effectively 48/4 MHz) */
89 MAP_CS_initClockSignal(CS_MCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_4);
90
91 /* Initializing ACLK to LFXT */
92 CS_startLFXT(false);
93 MAP_CS_initClockSignal(CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
94
95
96 /* Initializes Aux. Clocks System with DCO */
97 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
98 MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
99 MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_8);
100
101 /*
102 * Configuring SysTick to trigger at 6000000
103 * MCLK is 12MHz so this will make it toggle every 0.5s
104 * */
105
106 MAP_SysTick_enableModule();
107 MAP_SysTick_setPeriod(6000000);
108 MAP_Interrupt_enableSleepOnIsrExit();
109 MAP_SysTick_enableInterrupt();
110
111 /* Enabling MASTER interrupts */
112 MAP_Interrupt_enableMaster();
113
114 while (1)
115 {
116 MAP_PCM_gotoLPM0();
117 }
118}
119
120void SysTick_Handler(void)
121{
122 MAP_GPIO_toggleOutputOnPin(HID_PORT, LEDG|LEDR);
123}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd
deleted file mode 100644
index 346c191..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/msp432p401r.cmd
+++ /dev/null
@@ -1,84 +0,0 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c
deleted file mode 100644
index d5f9a14..0000000
--- a/Basic-Test-Package/MSP432/Test_MSP432_ClockSystem/startup_msp432p401r_ccs.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37//*****************************************************************************
38//
39// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
40//
41// Redistribution and use in source and binary forms, with or without
42// modification, are permitted provided that the following conditions
43// are met:
44//
45// Redistributions of source code must retain the above copyright
46// notice, this list of conditions and the following disclaimer.
47//
48// Redistributions in binary form must reproduce the above copyright
49// notice, this list of conditions and the following disclaimer in the
50// documentation and/or other materials provided with the
51// distribution.
52//
53// Neither the name of Texas Instruments Incorporated nor the names of
54// its contributors may be used to endorse or promote products derived
55// from this software without specific prior written permission.
56//
57// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
60// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
63// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
64// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
67// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68//
69// MSP432 Family Interrupt Vector Table for CGT
70//
71//****************************************************************************
72
73#include <stdint.h>
74
75/* Forward declaration of the default fault handlers. */
76static void resetISR(void);
77static void nmiISR(void);
78static void faultISR(void);
79static void defaultISR(void);
80
81
82/* External declaration for the reset handler that is to be called when the */
83/* processor is started */
84extern void _c_int00(void);
85
86/* External declaration for system initialization function */
87extern void SystemInit(void);
88
89/* Linker variable that marks the top of the stack. */
90extern unsigned long __STACK_END;
91
92
93/* External declarations for the interrupt handlers used by the application. */
94extern void SysTick_Handler(void);
95
96
97/* Interrupt vector table. Note that the proper constructs must be placed on this to */
98/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
99/* the program if located at a start address other than 0. */
100#pragma RETAIN(interruptVectors)
101#pragma DATA_SECTION(interruptVectors, ".intvecs")
102void (* const interruptVectors[])(void) =
103{
104 (void (*)(void))((uint32_t)&__STACK_END),
105 /* The initial stack pointer */
106 resetISR, /* The reset handler */
107 nmiISR, /* The NMI handler */
108 faultISR, /* The hard fault handler */
109 defaultISR, /* The MPU fault handler */
110 defaultISR, /* The bus fault handler */
111 defaultISR, /* The usage fault handler */
112 0, /* Reserved */
113 0, /* Reserved */
114 0, /* Reserved */
115 0, /* Reserved */
116 defaultISR, /* SVCall handler */
117 defaultISR, /* Debug monitor handler */
118 0, /* Reserved */
119 defaultISR, /* The PendSV handler */
120 SysTick_Handler, /* The SysTick handler */
121 defaultISR, /* PSS ISR */
122 defaultISR, /* CS ISR */
123 defaultISR, /* PCM ISR */
124 defaultISR, /* WDT ISR */
125 defaultISR, /* FPU ISR */
126 defaultISR, /* FLCTL ISR */
127 defaultISR, /* COMP0 ISR */
128 defaultISR, /* COMP1 ISR */
129 defaultISR, /* TA0_0 ISR */
130 defaultISR, /* TA0_N ISR */
131 defaultISR, /* TA1_0 ISR */
132 defaultISR, /* TA1_N ISR */
133 defaultISR, /* TA2_0 ISR */
134 defaultISR, /* TA2_N ISR */
135 defaultISR, /* TA3_0 ISR */
136 defaultISR, /* TA3_N ISR */
137 defaultISR, /* EUSCIA0 ISR */
138 defaultISR, /* EUSCIA1 ISR */
139 defaultISR, /* EUSCIA2 ISR */
140 defaultISR, /* EUSCIA3 ISR */
141 defaultISR, /* EUSCIB0 ISR */
142 defaultISR, /* EUSCIB1 ISR */
143 defaultISR, /* EUSCIB2 ISR */
144 defaultISR, /* EUSCIB3 ISR */
145 defaultISR, /* ADC14 ISR */
146 defaultISR, /* T32_INT1 ISR */
147 defaultISR, /* T32_INT2 ISR */
148 defaultISR, /* T32_INTC ISR */
149 defaultISR, /* AES ISR */
150 defaultISR, /* RTC ISR */
151 defaultISR, /* DMA_ERR ISR */
152 defaultISR, /* DMA_INT3 ISR */
153 defaultISR, /* DMA_INT2 ISR */