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authorBorja Martinez2016-09-10 12:48:13 -0500
committerBorja Martinez2016-09-10 12:48:13 -0500
commit7060e2a663c295f000cb3bec9ee0a03062a908df (patch)
tree2f0018be3347ed956994f8d803cf5c7032ea5d05
parentdfc5c91b9f14f56e4be572c28fd2c825b0e1c6b3 (diff)
downloadi3-mote-7060e2a663c295f000cb3bec9ee0a03062a908df.tar.gz
i3-mote-7060e2a663c295f000cb3bec9ee0a03062a908df.tar.xz
i3-mote-7060e2a663c295f000cb3bec9ee0a03062a908df.zip
Created Test MSP432 DebugUART EchoPC
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h25
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c146
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c255
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c434
5 files changed, 944 insertions, 0 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h
new file mode 100644
index 0000000..68dedce
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/i3mote.h
@@ -0,0 +1,25 @@
1/* Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7
8/* Rev.A
9#define LED_PORT GPIO_PORT_P8
10#define LEDR GPIO_PIN5
11#define LEDG GPIO_PIN6
12#define BUTTON GPIO_PIN7
13*/
14
15
16/* On Board EEPROM 25xx256*/
17#define EEPROM_SLAVE_ADDRESS 0x50
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c
new file mode 100644
index 0000000..e296f08
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/main.c
@@ -0,0 +1,146 @@
1/******************************************************************************
2 * MSP432 UART - PC Echo with 12MHz BRCLK
3 *
4 * Description: This demo echoes back characters received via a PC serial port.
5 * SMCLK/DCO is used as a clock source and the device is put in LPM0
6 * The auto-clock enable feature is used by the eUSCI and SMCLK is turned off
7 * when the UART is idle and turned on when a receive edge is detected.
8 * Note that level shifter hardware is needed to shift between RS232 and MSP
9 * voltage levels.
10 *
11 * MSP432P401
12 * -----------------
13 * | |
14 * | |
15 * | |
16 * RST -| P1.3/UCA0TXD|----> PC (echo)
17 * | |
18 * | |
19 * | P1.2/UCA0RXD|<---- PC
20 * | |
21 *
22 * Author: Timothy Logan
23 *
24 * I3Mote Version: B.Martinez
25 *
26 *
27 *
28*******************************************************************************/
29#include "i3mote.h"
30
31/* DriverLib Includes */
32#include "driverlib.h"
33
34
35/* Standard Includes */
36#include <stdint.h>
37#include <stdbool.h>
38
39#define SYSFREQ 12000000
40
41/* UART Configuration Parameter. These are the configuration parameters to
42 * make the eUSCI A UART module to operate with a 9600 baud rate.
43 * These values were calculated using the online calculator that TI provides at:
44 * http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html
45 */
46
47#ifdef UART_BAUD_9600
48 const eUSCI_UART_Config uartConfig =
49 {
50 EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
51 78, // BRDIV = 78
52 2, // UCxBRF = 2
53 0, // UCxBRS = 0
54 EUSCI_A_UART_NO_PARITY, // No Parity
55 EUSCI_A_UART_LSB_FIRST, // LSB First
56 EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
57 EUSCI_A_UART_MODE, // UART mode
58 EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
59 };
60#endif
61
62#ifdef UART_BAUD_115200
63 const eUSCI_UART_Config uartConfig =
64 {
65 EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
66 6, // BRDIV = 6
67 8, // UCxBRF = 8
68 32, // UCxBRS = 32
69 EUSCI_A_UART_NO_PARITY, // No Parity
70 EUSCI_A_UART_LSB_FIRST, // LSB First
71 EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
72 EUSCI_A_UART_MODE, // UART mode
73 EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION // Oversampling
74 };
75#endif
76
77
78
79int main(void)
80{
81
82 /* Halting WDT */
83 MAP_WDT_A_holdTimer();
84
85 /* Selecting P1.2 and P1.3 in UART mode */
86 MAP_GPIO_setAsPeripheralModuleFunctionInputPin(UART_PORT,
87 UART_RX_PIN | UART_TX_PIN, GPIO_PRIMARY_MODULE_FUNCTION);
88
89 /* LEDS Configuring P8.x as output */
90 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
91 MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDG|LEDR);
92
93 /* Setting DCO to 12MHz */
94 #if SYSFREQ==12000000
95 CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
96 #else
97 #error "Undefinde CLock Frequency"
98 #endif
99
100 /* Configuring UART Module */
101 MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig);
102
103 /* Enable UART module */
104 MAP_UART_enableModule(EUSCI_A0_BASE);
105
106 /* Enabling UART interrupts */
107 MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT);
108 MAP_Interrupt_enableInterrupt(INT_EUSCIA0);
109 MAP_Interrupt_enableSleepOnIsrExit();
110 MAP_Interrupt_enableMaster();
111
112 /* Enable SysTick (Toggle 0.5s) */
113 MAP_SysTick_enableModule();
114 MAP_SysTick_setPeriod(SYSFREQ/2);
115 MAP_SysTick_enableInterrupt();
116
117 /* Enabling MASTER interrupts */
118 MAP_Interrupt_enableMaster();
119
120 while(1)
121 {
122 MAP_PCM_gotoLPM0();
123 }
124}
125
126/* EUSCI A0 UART ISR - Echoes data back to PC host */
127void EUSCIA0_IRQHandler(void)
128{
129 uint32_t status = MAP_UART_getEnabledInterruptStatus(EUSCI_A0_BASE);
130
131 MAP_UART_clearInterruptFlag(EUSCI_A0_BASE, status);
132
133 if(status & EUSCI_A_UART_RECEIVE_INTERRUPT)
134 {
135 MAP_UART_transmitData(EUSCI_A0_BASE, MAP_UART_receiveData(EUSCI_A0_BASE));
136 }
137
138}
139
140void SysTick_Handler(void)
141{
142 MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG);
143}
144
145
146
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd
new file mode 100644
index 0000000..346c191
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/msp432p401r.cmd
@@ -0,0 +1,84 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c
new file mode 100644
index 0000000..e7fcb9f
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c
@@ -0,0 +1,255 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37//*****************************************************************************
38//
39// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
40//
41// Redistribution and use in source and binary forms, with or without
42// modification, are permitted provided that the following conditions
43// are met:
44//
45// Redistributions of source code must retain the above copyright
46// notice, this list of conditions and the following disclaimer.
47//
48// Redistributions in binary form must reproduce the above copyright
49// notice, this list of conditions and the following disclaimer in the
50// documentation and/or other materials provided with the
51// distribution.
52//
53// Neither the name of Texas Instruments Incorporated nor the names of
54// its contributors may be used to endorse or promote products derived
55// from this software without specific prior written permission.
56//
57// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
60// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
63// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
64// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
67// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68//
69// MSP432 Family Interrupt Vector Table for CGT
70//
71//****************************************************************************
72
73#include <stdint.h>
74
75/* Forward declaration of the default fault handlers. */
76static void resetISR(void);
77static void nmiISR(void);
78static void faultISR(void);
79static void defaultISR(void);
80
81
82/* External declaration for the reset handler that is to be called when the */
83/* processor is started */
84extern void _c_int00(void);
85
86/* External declaration for system initialization function */
87extern void SystemInit(void);
88
89/* Linker variable that marks the top of the stack. */
90extern unsigned long __STACK_END;
91
92
93/* External declarations for the interrupt handlers used by the application. */
94extern void EUSCIA0_IRQHandler (void);
95extern void SysTick_Handler(void);
96
97
98/* Interrupt vector table. Note that the proper constructs must be placed on this to */
99/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
100/* the program if located at a start address other than 0. */
101#pragma RETAIN(interruptVectors)
102#pragma DATA_SECTION(interruptVectors, ".intvecs")
103void (* const interruptVectors[])(void) =
104{
105 (void (*)(void))((uint32_t)&__STACK_END),
106 /* The initial stack pointer */
107 resetISR, /* The reset handler */
108 nmiISR, /* The NMI handler */
109 faultISR, /* The hard fault handler */
110 defaultISR, /* The MPU fault handler */
111 defaultISR, /* The bus fault handler */
112 defaultISR, /* The usage fault handler */
113 0, /* Reserved */
114 0, /* Reserved */
115 0, /* Reserved */
116 0, /* Reserved */
117 defaultISR, /* SVCall handler */
118 defaultISR, /* Debug monitor handler */
119 0, /* Reserved */
120 defaultISR, /* The PendSV handler */
121 SysTick_Handler, /* The SysTick handler */
122 defaultISR, /* PSS ISR */
123 defaultISR, /* CS ISR */
124 defaultISR, /* PCM ISR */
125 defaultISR, /* WDT ISR */
126 defaultISR, /* FPU ISR */
127 defaultISR, /* FLCTL ISR */
128 defaultISR, /* COMP0 ISR */
129 defaultISR, /* COMP1 ISR */
130 defaultISR, /* TA0_0 ISR */
131 defaultISR, /* TA0_N ISR */
132 defaultISR, /* TA1_0 ISR */
133 defaultISR, /* TA1_N ISR */
134 defaultISR, /* TA2_0 ISR */
135 defaultISR, /* TA2_N ISR */
136 defaultISR, /* TA3_0 ISR */
137 defaultISR, /* TA3_N ISR */
138 EUSCIA0_IRQHandler, /* EUSCIA0 ISR */
139 defaultISR, /* EUSCIA1 ISR */
140 defaultISR, /* EUSCIA2 ISR */
141 defaultISR, /* EUSCIA3 ISR */
142 defaultISR, /* EUSCIB0 ISR */
143 defaultISR, /* EUSCIB1 ISR */
144 defaultISR, /* EUSCIB2 ISR */
145 defaultISR, /* EUSCIB3 ISR */
146 defaultISR, /* ADC14 ISR */
147 defaultISR, /* T32_INT1 ISR */
148 defaultISR, /* T32_INT2 ISR */
149 defaultISR, /* T32_INTC ISR */
150 defaultISR, /* AES ISR */
151 defaultISR, /* RTC ISR */
152 defaultISR, /* DMA_ERR ISR */
153 defaultISR, /* DMA_INT3 ISR */
154 defaultISR, /* DMA_INT2 ISR */
155 defaultISR, /* DMA_INT1 ISR */
156 defaultISR, /* DMA_INT0 ISR */
157 defaultISR, /* PORT1 ISR */
158 defaultISR, /* PORT2 ISR */
159 defaultISR, /* PORT3 ISR */
160 defaultISR, /* PORT4 ISR */
161 defaultISR, /* PORT5 ISR */
162 defaultISR, /* PORT6 ISR */
163 defaultISR, /* Reserved 41 */
164 defaultISR, /* Reserved 42 */
165 defaultISR, /* Reserved 43 */
166 defaultISR, /* Reserved 44 */
167 defaultISR, /* Reserved 45 */
168 defaultISR, /* Reserved 46 */
169 defaultISR, /* Reserved 47 */
170 defaultISR, /* Reserved 48 */
171 defaultISR, /* Reserved 49 */
172 defaultISR, /* Reserved 50 */
173 defaultISR, /* Reserved 51 */
174 defaultISR, /* Reserved 52 */
175 defaultISR, /* Reserved 53 */
176 defaultISR, /* Reserved 54 */
177 defaultISR, /* Reserved 55 */
178 defaultISR, /* Reserved 56 */
179 defaultISR, /* Reserved 57 */
180 defaultISR, /* Reserved 58 */
181 defaultISR, /* Reserved 59 */
182 defaultISR, /* Reserved 60 */
183 defaultISR, /* Reserved 61 */
184 defaultISR, /* Reserved 62 */
185 defaultISR /* Reserved 63 */
186};
187
188
189/* This is the code that gets called when the processor first starts execution */
190/* following a reset event. Only the absolutely necessary set is performed, */
191/* after which the application supplied entry() routine is called. Any fancy */
192/* actions (such as making decisions based on the reset cause register, and */
193/* resetting the bits in that register) are left solely in the hands of the */
194/* application. */
195void resetISR(void)
196{
197 SystemInit();
198
199 /* Jump to the CCS C Initialization Routine. */
200 __asm(" .global _c_int00\n"
201 " b.w _c_int00");
202}
203
204/* This is the code that gets called when the processor receives a NMI. This */
205/* simply enters an infinite loop, preserving the system state for examination */
206/* by a debugger. */
207static void nmiISR(void)
208{
209 /* Fault trap exempt from ULP advisor */
210 #pragma diag_push
211 #pragma CHECK_ULP("-2.1")
212
213 /* Enter an infinite loop. */
214 while(1)
215 {
216 }
217
218 #pragma diag_pop
219}
220
221
222/* This is the code that gets called when the processor receives a fault */
223/* interrupt. This simply enters an infinite loop, preserving the system state */
224/* for examination by a debugger. */
225static void faultISR(void)
226{
227 /* Fault trap exempt from ULP advisor */
228 #pragma diag_push
229 #pragma CHECK_ULP("-2.1")
230
231 /* Enter an infinite loop. */
232 while(1)
233 {
234 }
235
236 #pragma diag_pop
237}
238
239
240/* This is the code that gets called when the processor receives an unexpected */
241/* interrupt. This simply enters an infinite loop, preserving the system state */
242/* for examination by a debugger. */
243static void defaultISR(void)
244{
245 /* Fault trap exempt from ULP advisor */
246 #pragma diag_push
247 #pragma CHECK_ULP("-2.1")
248
249 /* Enter an infinite loop. */
250 while(1)
251 {
252 }
253
254 #pragma diag_pop
255}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c
new file mode 100644
index 0000000..9479e03
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/system_msp432p401r.c
@@ -0,0 +1,434 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37/**************************************************************************//**
38* @file system_msp432p401r.c
39* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
40* MSP432P401R
41* @version V1.00
42* @date 20-Oct-2015
43*
44* @note View configuration instructions embedded in comments
45*
46******************************************************************************/
47//*****************************************************************************
48//
49// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
50//
51// Redistribution and use in source and binary forms, with or without
52// modification, are permitted provided that the following conditions
53// are met:
54//
55// Redistributions of source code must retain the above copyright
56// notice, this list of conditions and the following disclaimer.
57//
58// Redistributions in binary form must reproduce the above copyright
59// notice, this list of conditions and the following disclaimer in the
60// documentation and/or other materials provided with the
61// distribution.
62//
63// Neither the name of Texas Instruments Incorporated nor the names of
64// its contributors may be used to endorse or promote products derived
65// from this software without specific prior written permission.
66//
67// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
68// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
69// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
70// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
71// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
72// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
74// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
75// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78//
79//*****************************************************************************
80
81#include <stdint.h>
82#include "msp.h"
83
84/*--------------------- Configuration Instructions ----------------------------
85 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
86 #define __HALT_WDT 1
87 2. Insert your desired CPU frequency in Hz at:
88 #define __SYSTEM_CLOCK 3000000
89 3. If you prefer the DC-DC power regulator (more efficient at higher
90 frequencies), set the __REGULATOR to 1:
91 #define __REGULATOR 1
92 *---------------------------------------------------------------------------*/
93
94/*--------------------- Watchdog Timer Configuration ------------------------*/
95// Halt the Watchdog Timer
96// <0> Do not halt the WDT
97// <1> Halt the WDT
98#define __HALT_WDT 1
99
100/*--------------------- CPU Frequency Configuration -------------------------*/
101// CPU Frequency
102// <1500000> 1.5 MHz
103// <3000000> 3 MHz
104// <12000000> 12 MHz
105// <24000000> 24 MHz
106// <48000000> 48 MHz
107#define __SYSTEM_CLOCK 1500000
108
109/*--------------------- Power Regulator Configuration -----------------------*/
110// Power Regulator Mode
111// <0> LDO
112// <1> DC-DC
113#define __REGULATOR 1
114
115/*----------------------------------------------------------------------------
116 Define clocks, used for SystemCoreClockUpdate()
117 *---------------------------------------------------------------------------*/
118#define __VLOCLK 10000
119#define __MODCLK 24000000
120#define __LFXT 32768
121#define __HFXT 48000000
122
123/*----------------------------------------------------------------------------
124 Clock Variable definitions
125 *---------------------------------------------------------------------------*/
126uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
127
128/**
129 * Update SystemCoreClock variable
130 *
131 * @param none
132 * @return none
133 *
134 * @brief Updates the SystemCoreClock with current core Clock
135 * retrieved from cpu registers.
136 */
137void SystemCoreClockUpdate(void)
138{
139 uint32_t source, divider;
140 uint8_t dividerValue;
141
142 float dcoConst;
143 int32_t calVal;
144 uint32_t centeredFreq;
145 int16_t dcoTune;
146
147 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
148 dividerValue = 1 << divider;
149 source = CS->CTL1 & CS_CTL1_SELM_MASK;
150
151 switch(source)
152 {
153 case CS_CTL1_SELM__LFXTCLK:
154 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
155 {
156 // Clear interrupt flag
157 CS->KEY = CS_KEY_VAL;
158 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
159 CS->KEY = 1;
160
161 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
162 {
163 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
164 {
165 SystemCoreClock = (128000 / dividerValue);
166 }
167 else
168 {
169 SystemCoreClock = (32000 / dividerValue);
170 }
171 }
172 else
173 {
174 SystemCoreClock = __LFXT / dividerValue;
175 }
176 }
177 else
178 {
179 SystemCoreClock = __LFXT / dividerValue;
180 }
181 break;
182 case CS_CTL1_SELM__VLOCLK:
183 SystemCoreClock = __VLOCLK / dividerValue;
184 break;
185 case CS_CTL1_SELM__REFOCLK:
186 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
187 {
188 SystemCoreClock = (128000 / dividerValue);
189 }
190 else
191 {
192 SystemCoreClock = (32000 / dividerValue);
193 }
194 break;
195 case CS_CTL1_SELM__DCOCLK:
196 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
197
198 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
199 {
200 case CS_CTL0_DCORSEL_0:
201 centeredFreq = 1500000;
202 break;
203 case CS_CTL0_DCORSEL_1:
204 centeredFreq = 3000000;
205 break;
206 case CS_CTL0_DCORSEL_2:
207 centeredFreq = 6000000;
208 break;
209 case CS_CTL0_DCORSEL_3:
210 centeredFreq = 12000000;
211 break;
212 case CS_CTL0_DCORSEL_4:
213 centeredFreq = 24000000;
214 break;
215 case CS_CTL0_DCORSEL_5:
216 centeredFreq = 48000000;
217 break;
218 }
219
220 if(dcoTune == 0)
221 {
222 SystemCoreClock = centeredFreq;
223 }
224 else
225 {
226
227 if(dcoTune & 0x1000)
228 {
229 dcoTune = dcoTune | 0xF000;
230 }
231
232 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
233 {
234 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
235 calVal = TLV->DCOER_FCAL_RSEL04;
236 }
237 /* Internal Resistor */
238 else
239 {
240 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
241 calVal = TLV->DCOIR_FCAL_RSEL04;
242 }
243
244 SystemCoreClock = (uint32_t) ((centeredFreq)
245 / (1
246 - ((dcoConst * dcoTune)
247 / (8 * (1 + dcoConst * (768 - calVal))))));
248 }
249 break;
250 case CS_CTL1_SELM__MODOSC:
251 SystemCoreClock = __MODCLK / dividerValue;
252 break;
253 case CS_CTL1_SELM__HFXTCLK:
254 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
255 {
256 // Clear interrupt flag
257 CS->KEY = CS_KEY_VAL;
258 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
259 CS->KEY = 1;
260
261 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
262 {
263 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
264 {
265 SystemCoreClock = (128000 / dividerValue);
266 }
267 else
268 {
269 SystemCoreClock = (32000 / dividerValue);
270 }
271 }
272 else
273 {
274 SystemCoreClock = __HFXT / dividerValue;
275 }
276 }
277 else
278 {
279 SystemCoreClock = __HFXT / dividerValue;
280 }
281 break;
282 }
283}
284
285/**
286 * Initialize the system
287 *
288 * @param none
289 * @return none
290 *
291 * @brief Setup the microcontroller system.
292 *
293 * Performs the following initialization steps:
294 * 1. Enables the FPU
295 * 2. Halts the WDT if requested
296 * 3. Enables all SRAM banks
297 * 4. Sets up power regulator and VCORE
298 * 5. Enable Flash wait states if needed
299 * 6. Change MCLK to desired frequency
300 * 7. Enable Flash read buffering
301 */
302void SystemInit(void)
303{
304 // Enable FPU if used
305 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
306 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
307 (3UL << 11 * 2)); /* Set CP11 Full Access */
308 #endif
309
310 #if (__HALT_WDT == 1)
311 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
312 #endif
313
314 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
315
316 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
317 // Default VCORE is LDO VCORE0 so no change necessary
318
319 // Switches LDO VCORE0 to DCDC VCORE0 if requested
320 #if __REGULATOR
321 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
322 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
323 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
324 #endif
325
326 // No flash wait states necessary
327
328 // DCO = 1.5 MHz; MCLK = source
329 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
330 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
331 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
332 CS->KEY = 0;
333
334 // Set Flash Bank read buffering
335 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
336 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
337
338 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
339 // Default VCORE is LDO VCORE0 so no change necessary
340
341 // Switches LDO VCORE0 to DCDC VCORE0 if requested
342 #if __REGULATOR
343 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
344 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
345 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
346 #endif
347
348 // No flash wait states necessary
349
350 // DCO = 3 MHz; MCLK = source
351 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
352 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
353 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
354 CS->KEY = 0;
355
356 // Set Flash Bank read buffering
357 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
358 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
359
360 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
361 // Default VCORE is LDO VCORE0 so no change necessary
362
363 // Switches LDO VCORE0 to DCDC VCORE0 if requested
364 #if __REGULATOR
365 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
366 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
367 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
368 #endif
369
370 // No flash wait states necessary
371
372 // DCO = 12 MHz; MCLK = source
373 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
374 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
375 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
376 CS->KEY = 0;
377
378 // Set Flash Bank read buffering
379 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
380 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
381
382 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
383 // Default VCORE is LDO VCORE0 so no change necessary
384
385 // Switches LDO VCORE0 to DCDC VCORE0 if requested
386 #if __REGULATOR
387 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
388 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
389 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
390 #endif
391
392 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
393 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
394 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
395
396 // DCO = 24 MHz; MCLK = source
397 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
398 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
399 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
400 CS->KEY = 0;
401
402 // Set Flash Bank read buffering
403 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
404 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
405
406 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
407 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
408 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
409 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
410 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
411
412 // Switches LDO VCORE1 to DCDC VCORE1 if requested
413 #if __REGULATOR
414 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
415 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
416 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
417 #endif
418
419 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
420 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
421 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
422
423 // DCO = 48 MHz; MCLK = source
424 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
425 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
426 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
427 CS->KEY = 0;
428
429 // Set Flash Bank read buffering
430 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
431 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
432 #endif
433
434}