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authorBorja Martinez2016-09-11 12:11:00 -0500
committerBorja Martinez2016-09-11 12:11:00 -0500
commit7b80650fc531bf2b93db1770ad66f2c333b6d4ca (patch)
treef48e6be43b1cb4ac368090fe3c6fb39efb68f35d
parentac6f47b3016800dfddb4516e3b943de64058e883 (diff)
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Created Boot MSP430 Dual
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/lnk_msp430g2221.cmd144
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c275
2 files changed, 419 insertions, 0 deletions
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/lnk_msp430g2221.cmd b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/lnk_msp430g2221.cmd
new file mode 100644
index 0000000..a0ba06b
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/lnk_msp430g2221.cmd
@@ -0,0 +1,144 @@
1/* ============================================================================ */
2/* Copyright (c) 2016, Texas Instruments Incorporated */
3/* All rights reserved. */
4/* */
5/* Redistribution and use in source and binary forms, with or without */
6/* modification, are permitted provided that the following conditions */
7/* are met: */
8/* */
9/* * Redistributions of source code must retain the above copyright */
10/* notice, this list of conditions and the following disclaimer. */
11/* */
12/* * Redistributions in binary form must reproduce the above copyright */
13/* notice, this list of conditions and the following disclaimer in the */
14/* documentation and/or other materials provided with the distribution. */
15/* */
16/* * Neither the name of Texas Instruments Incorporated nor the names of */
17/* its contributors may be used to endorse or promote products derived */
18/* from this software without specific prior written permission. */
19/* */
20/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
21/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
22/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
23/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
24/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
25/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
26/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
27/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
28/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
29/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
30/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
31/* ============================================================================ */
32
33/******************************************************************************/
34/* lnk_msp430g2221.cmd - LINKER COMMAND FILE FOR LINKING MSP430G2221 PROGRAMS */
35/* */
36/* Usage: lnk430 <obj files...> -o <out file> -m <map file> lnk.cmd */
37/* cl430 <src files...> -z -o <out file> -m <map file> lnk.cmd */
38/* */
39/*----------------------------------------------------------------------------*/
40/* These linker options are for command line linking only. For IDE linking, */
41/* you should set your linker options in Project Properties */
42/* -c LINK USING C CONVENTIONS */
43/* -stack 0x0100 SOFTWARE STACK SIZE */
44/* -heap 0x0100 HEAP AREA SIZE */
45/* */
46/*----------------------------------------------------------------------------*/
47/* Version: 1.191 */
48/*----------------------------------------------------------------------------*/
49
50/****************************************************************************/
51/* Specify the system memory map */
52/****************************************************************************/
53
54MEMORY
55{
56 SFR : origin = 0x0000, length = 0x0010
57 PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
58 PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
59 RAM : origin = 0x0200, length = 0x0080
60 INFOA : origin = 0x10C0, length = 0x0040
61 INFOB : origin = 0x1080, length = 0x0040
62 INFOC : origin = 0x1040, length = 0x0040
63 INFOD : origin = 0x1000, length = 0x0040
64 FLASH : origin = 0xF800, length = 0x07E0
65 INT00 : origin = 0xFFE0, length = 0x0002
66 INT01 : origin = 0xFFE2, length = 0x0002
67 INT02 : origin = 0xFFE4, length = 0x0002
68 INT03 : origin = 0xFFE6, length = 0x0002
69 INT04 : origin = 0xFFE8, length = 0x0002
70 INT05 : origin = 0xFFEA, length = 0x0002
71 INT06 : origin = 0xFFEC, length = 0x0002
72 INT07 : origin = 0xFFEE, length = 0x0002
73 INT08 : origin = 0xFFF0, length = 0x0002
74 INT09 : origin = 0xFFF2, length = 0x0002
75 INT10 : origin = 0xFFF4, length = 0x0002
76 INT11 : origin = 0xFFF6, length = 0x0002
77 INT12 : origin = 0xFFF8, length = 0x0002
78 INT13 : origin = 0xFFFA, length = 0x0002
79 INT14 : origin = 0xFFFC, length = 0x0002
80 RESET : origin = 0xFFFE, length = 0x0002
81}
82
83/****************************************************************************/
84/* Specify the sections allocation into memory */
85/****************************************************************************/
86
87SECTIONS
88{
89 .bss : {} > RAM /* Global & static vars */
90 .data : {} > RAM /* Global & static vars */
91 .TI.noinit : {} > RAM /* For #pragma noinit */
92 .sysmem : {} > RAM /* Dynamic memory allocation area */
93 .stack : {} > RAM (HIGH) /* Software system stack */
94
95 .text : {} > FLASH /* Code */
96 .cinit : {} > FLASH /* Initialization tables */
97 .const : {} > FLASH /* Constant data */
98 .cio : {} > RAM /* C I/O Buffer */
99
100 .pinit : {} > FLASH /* C++ Constructor tables */
101 .binit : {} > FLASH /* Boot-time Initialization tables */
102 .init_array : {} > FLASH /* C++ Constructor tables */
103 .mspabi.exidx : {} > FLASH /* C++ Constructor tables */
104 .mspabi.extab : {} > FLASH /* C++ Constructor tables */
105#ifdef __TI_COMPILER_VERSION
106 #if __TI_COMPILER_VERSION >= 15009000
107 #ifndef __LARGE_DATA_MODEL__
108 .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
109 #else
110 .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
111 #endif
112 #endif
113#endif
114
115 .infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */
116 .infoB : {} > INFOB
117 .infoC : {} > INFOC
118 .infoD : {} > INFOD
119
120 /* MSP430 Interrupt vectors */
121 .int00 : {} > INT00
122 .int01 : {} > INT01
123 PORT1 : { * ( .int02 ) } > INT02 type = VECT_INIT
124 PORT2 : { * ( .int03 ) } > INT03 type = VECT_INIT
125 USI : { * ( .int04 ) } > INT04 type = VECT_INIT
126 .int05 : {} > INT05
127 .int06 : {} > INT06
128 .int07 : {} > INT07
129 TIMERA1 : { * ( .int08 ) } > INT08 type = VECT_INIT
130 TIMERA0 : { * ( .int09 ) } > INT09 type = VECT_INIT
131 WDT : { * ( .int10 ) } > INT10 type = VECT_INIT
132 .int11 : {} > INT11
133 .int12 : {} > INT12
134 .int13 : {} > INT13
135 NMI : { * ( .int14 ) } > INT14 type = VECT_INIT
136 .reset : {} > RESET /* MSP430 Reset vector */
137}
138
139/****************************************************************************/
140/* Include peripherals memory map */
141/****************************************************************************/
142
143-l msp430g2221.cmd
144
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
new file mode 100644
index 0000000..3de4526
--- /dev/null
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
@@ -0,0 +1,275 @@
1/*
2/*---------------------------------------------------------------------------*/
3#include <msp430.h>
4#include <stdint.h>
5#include <stdbool.h>
6#include <stdio.h>
7
8#define CC2650
9#define MSP432
10
11/*---------------------------------------------------------------------------*/
12#define RESET_IN1 ( BIT0 ) // RTS - RESET
13#define BOOT_IN1 ( BIT1 ) // DTR - BOOT
14#define RESET_OUT1 ( BIT2 ) // RTS - RESET
15#define BOOT_OUT1 ( BIT3 ) // DTR - BOOT
16/*---------------------------------------------------------------------------*/
17#define RESET_IN2 ( BIT4 ) // RTS - RESET
18#define BOOT_IN2 ( BIT5 ) // DTR - BOOT
19#define RESET_OUT2 ( BIT6 ) // RTS - RESET
20#define BOOT_OUT2 ( BIT7 ) // DTR - BOOT
21
22/*---------------------------------------------------------------------------*/
23#define BOOTLOADER_TIMEOUT ( 3000 ) // ~2s ms @ 1.5 kHz
24#define STARTUP_DELAY ( 425 ) // ~0.1ms us @ 4.25 MHz
25#define MSEC_DELAY ( 4250 ) // ~1ms @ 4.25 MHz
26#define BOOTLOADER_DELAY ( 5*MSEC_DELAY ) // ~1ms @ 4.25 MHz
27
28/*---------------------------------------------------------------------------*/
29static volatile bool bootloader_active = false;
30static volatile bool bootload_enable = false;
31/*---------------------------------------------------------------------------*/
32int main(void) {
33
34 // Disable Watchdog
35 WDTCTL = WDTPW + WDTHOLD;
36
37 // Set DCO operation to 4.25 MHz
38 BCSCTL1 &= ~(BIT2 + BIT1 + BIT0);
39 BCSCTL1 |= (BIT3 + BIT1 + BIT0);
40
41 /*
42 * Configure MCLK, SMCLK, ACLK
43 MCLK = DCO / 1 = 4.25 MHz
44 SMCLK = DCO / 1 = 4.25 MHz
45 ACLK = VLOCLK / 8 = 12 kHz / 8 = 1.5 kHz
46 */
47 BCSCTL1 |= (XT2OFF + DIVA_3);
48 BCSCTL3 |= (LFXT1S_2);
49
50 // Configure P1 input and ouput
51#ifdef MSP432
52 P1DIR &= ~(RESET_IN1 + BOOT_IN1);
53 P1DIR &= ~(RESET_OUT1);
54 P1DIR |= (BOOT_OUT1);
55 P1OUT |= (BOOT_OUT1);
56#endif
57
58#ifdef CC2650
59 P1DIR &= ~(RESET_IN2 + BOOT_IN2);
60 P1DIR &= ~(RESET_OUT2);
61 P1DIR |= (BOOT_OUT2);
62 P1OUT |= (BOOT_OUT2);
63#endif
64
65 // Wait for stabilization
66 __delay_cycles(STARTUP_DELAY);
67
68#ifdef MSP432
69 // Configure RESET_IN1 interrupt high to low
70 P1IFG &= ~(RESET_IN1);
71 P1IES |= (RESET_IN1);
72 P1IE |= (RESET_IN1);
73#endif
74
75#ifdef CC2650
76 // Configure RESET_IN2 interrupt high to low
77 P1IFG &= ~(RESET_IN2);
78 P1IES |= (RESET_IN2);
79 P1IE |= (RESET_IN2);
80#endif
81
82 // Forever
83 while (1) {
84 // Go to the lowest LPM
85 if (bootloader_active == true) {
86 _BIS_SR(LPM3_bits + GIE);
87 } else {
88 _BIS_SR(LPM4_bits + GIE);
89 }
90 }
91
92 return 0;
93
94}
95/*---------------------------------------------------------------------------*/
96#pragma vector=PORT1_VECTOR
97__interrupt void port1_isr (void) {
98
99#ifdef MSP432
100 // RESET_IN1 high to low
101 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
102 ((P1IN & RESET_IN1) == 0) &&
103 ((P1IES & RESET_IN1) == RESET_IN1)) {
104
105 // RESET_IN1 interrupt clear
106 P1IFG &= ~(RESET_IN1);
107
108 // RESET_IN1 low to high
109 P1IES &= ~(RESET_IN1);
110 // BOOT_IN1 high to low
111 P1IES |= (BOOT_IN1);
112 P1IE |= (RESET_IN1 + BOOT_IN1);
113
114 // TIMERA0 configure
115 CCR0 = BOOTLOADER_TIMEOUT;
116 CCTL0 = (CCIE);
117 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
118
119 // Set bootloader_active
120 bootloader_active = true;
121 }
122
123 // BOOT_IN1 high to low
124 if (((P1IFG & BOOT_IN1) == BOOT_IN1) &&
125 ((P1IN & BOOT_IN1) == 0) &&
126 ((P1IES & BOOT_IN1) == BOOT_IN1)) {
127 // BOOT_IN1 interrupt clear
128 P1IFG &= ~(BOOT_IN1);
129
130 // RESET_IN1 should be low
131 if ((P1IN & RESET_IN1) == 0) {
132 bootload_enable = true;
133 }
134 }
135
136 // RESET_IN1 low to high
137 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
138 ((P1IN & RESET_IN1) == RESET_IN1) &&
139 ((P1IES & RESET_IN1) == 0)) {
140 // RESET_IN1 interrupt clear
141 P1IFG &= ~(RESET_IN1);
142
143 // RESET_IN1 and BOOT_IN1 disable
144 P1IE &= ~(RESET_IN1 + BOOT_IN1);
145
146 // If bootload_enable is set
147 if (bootload_enable == true) {
148 // RESET_OUT1 is now ouput
149 P1DIR |= (RESET_OUT1);
150 //__delay_cycles(STARTUP_DELAY);
151 P1OUT &= ~(BOOT_OUT1);
152 __delay_cycles(STARTUP_DELAY);
153 /* Reset Pulse */
154 P1OUT &=~(RESET_OUT1);
155 __delay_cycles(MSEC_DELAY);
156 P1OUT |= (RESET_OUT1);
157 __delay_cycles(BOOTLOADER_DELAY);
158
159 /* Release Boot Pin*/
160 P1OUT |= (BOOT_OUT1);
161 // RESET_OUT1 is now input
162 P1DIR &= ~(RESET_OUT1);
163 }
164 }
165#endif
166
167#ifdef CC2650
168 // RESET_IN1 high to low
169 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
170 ((P1IN & RESET_IN2) == 0) &&
171 ((P1IES & RESET_IN2) == RESET_IN2)) {
172
173 // RESET_IN2 interrupt clear
174 P1IFG &= ~(RESET_IN2);
175
176 // RESET_IN2 low to high
177 // BOOT_IN2 high to low
178 P1IES &= ~(RESET_IN2);
179 P1IES |= (BOOT_IN2);
180 P1IE |= (RESET_IN2 + BOOT_IN2);
181
182 // TIMERA0 configure
183 CCR0 = BOOTLOADER_TIMEOUT;
184 CCTL0 = (CCIE);
185 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
186
187 // Set bootloader_active
188 bootloader_active = true;
189 }
190
191 // BOOT_IN2 high to low
192 if (((P1IFG & BOOT_IN2) == BOOT_IN2) &&
193 ((P1IN & BOOT_IN2) == 0) &&
194 ((P1IES & BOOT_IN2) == BOOT_IN2)) {
195
196 // BOOT_IN2 interrupt clear
197 P1IFG &= ~(BOOT_IN2);
198
199 // RESET_IN1 should be low
200 if ((P1IN & RESET_IN2) == 0) {
201 bootload_enable = true;
202 }
203 }
204
205 // RESET_IN1 low to high
206 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
207 ((P1IN & RESET_IN2) == RESET_IN2) &&
208 ((P1IES & RESET_IN2) == 0)) {
209 // RESET_IN1 interrupt clear
210 P1IFG &= ~(RESET_IN2);
211
212 // RESET_IN1 and BOOT_IN1 disable
213 P1IE &= ~(RESET_IN2 + BOOT_IN2);
214
215 // If bootload_enable is set
216 if (bootload_enable == true) {
217 // RESET_OUT1 is now ouput
218 P1DIR |= (RESET_OUT2);
219 //__delay_cycles(STARTUP_DELAY);
220 P1OUT &= ~(BOOT_OUT2);
221 __delay_cycles(STARTUP_DELAY);
222 /* Reset Pulse */
223 P1OUT &=~(RESET_OUT2);
224 __delay_cycles(MSEC_DELAY);
225 P1OUT |= (RESET_OUT2);
226 __delay_cycles(BOOTLOADER_DELAY);
227
228 /* Release Boot Pin*/
229 P1OUT |= (BOOT_OUT2);
230 // RESET_OUT1 is now input
231 P1DIR &= ~(RESET_OUT2);
232 }
233 }
234#endif
235
236 _BIC_SR_IRQ(LPM4_bits + GIE);
237}
238/*---------------------------------------------------------------------------*/
239#pragma vector=TIMERA0_VECTOR
240__interrupt void timera0_isr (void) {
241
242 // TIMERA0 reset
243 TACTL = 0;
244 CCTL0 &=~(CCIE);
245
246 // Clear variables
247 bootloader_active = false;
248 bootload_enable = false;
249
250#ifdef MSP432
251 // Ensure RESET_OUT1 and BOOT_OUT1 are high
252 P1OUT |= (RESET_OUT1 + BOOT_OUT1);
253 P1DIR &=~(RESET_OUT1);
254
255 // (Re)Enable RESET_IN1 high to low Int
256 P1IES |= (RESET_IN1);
257 P1IFG &= ~(RESET_IN1+BOOT_IN1);
258 P1IE |= (RESET_IN1);
259#endif
260
261#ifdef CC2650
262 // Ensure RESET_OUT2 and BOOT_OUT2 are high
263 P1OUT |= (RESET_OUT2 + BOOT_OUT2);
264 P1DIR &=~(RESET_OUT2);
265
266 // (Re)Enable RESET_IN2 high to low Int
267 P1IES |= (RESET_IN2);
268 P1IFG &= ~(RESET_IN2+BOOT_IN2);
269 P1IE |= (RESET_IN2);
270#endif
271
272 _BIC_SR_IRQ(LPM3_bits + GIE);
273
274}
275/*---------------------------------------------------------------------------*/