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authorBorja Martinez2016-09-17 15:26:13 -0500
committerBorja Martinez2016-09-17 15:26:13 -0500
commitccabc6d8588226438b21f1bcf9c0dec8dda97ba5 (patch)
tree0e11792115bbb5e2f99bed9444aabc2bada1e870
parentc4906f63b421cc7bdd4b88e78bba1c8f07f13e99 (diff)
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BSL msp430 compatible with FDTI windows driver
-rw-r--r--Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c403
1 files changed, 252 insertions, 151 deletions
diff --git a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
index 3de4526..333088b 100644
--- a/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
+++ b/Basic-Test-Package/BSL/MSP430/Boot_MSP430_Dual/main.c
@@ -1,5 +1,5 @@
1/*
2/*---------------------------------------------------------------------------*/ 1/*---------------------------------------------------------------------------*/
2
3#include <msp430.h> 3#include <msp430.h>
4#include <stdint.h> 4#include <stdint.h>
5#include <stdbool.h> 5#include <stdbool.h>
@@ -9,28 +9,38 @@
9#define MSP432 9#define MSP432
10 10
11/*---------------------------------------------------------------------------*/ 11/*---------------------------------------------------------------------------*/
12#define RESET_IN1 ( BIT0 ) // RTS - RESET 12#define RESET_IN1 (BIT0) // RTS - RESET
13#define BOOT_IN1 ( BIT1 ) // DTR - BOOT 13#define BOOT_IN1 (BIT1) // DTR - BOOT
14#define RESET_OUT1 ( BIT2 ) // RTS - RESET 14#define RESET_OUT1 (BIT2) // RTS - RESET
15#define BOOT_OUT1 ( BIT3 ) // DTR - BOOT 15#define BOOT_OUT1 (BIT3) // DTR - BOOT
16/*---------------------------------------------------------------------------*/ 16/*---------------------------------------------------------------------------*/
17#define RESET_IN2 ( BIT4 ) // RTS - RESET 17#define RESET_IN2 (BIT4) // RTS - RESET
18#define BOOT_IN2 ( BIT5 ) // DTR - BOOT 18#define BOOT_IN2 (BIT5) // DTR - BOOT
19#define RESET_OUT2 ( BIT6 ) // RTS - RESET 19#define RESET_OUT2 (BIT6) // RTS - RESET
20#define BOOT_OUT2 ( BIT7 ) // DTR - BOOT 20#define BOOT_OUT2 (BIT7) // DTR - BOOT
21 21
22/*---------------------------------------------------------------------------*/ 22/*---------------------------------------------------------------------------*/
23#define BOOTLOADER_TIMEOUT ( 3000 ) // ~2s ms @ 1.5 kHz 23/* Timer Delays*/
24#define STARTUP_DELAY ( 425 ) // ~0.1ms us @ 4.25 MHz 24#define STARTUP_DELAY (3000) // ~2s @ 1.5 Khz
25#define MSEC_DELAY ( 4250 ) // ~1ms @ 4.25 MHz 25#define BOOTLOADER_TIMEOUT (50) // ~100 ms @ 1.5 kHz
26#define BOOTLOADER_DELAY ( 5*MSEC_DELAY ) // ~1ms @ 4.25 MHz 26
27/*---------------------------------------------------------------------------*/
28/* Procesor Delays */
29#define MSEC_DELAY (4250) // ~1 ms @ 4.25 MHz
30#define CC2650_BSL_DELAY (8500) // 2 ms @ 4.25 MHz
31#define MSP432_BSL_DELAY (42500) // 10 ms @ 4.25 MHz
32
27 33
28/*---------------------------------------------------------------------------*/ 34/*---------------------------------------------------------------------------*/
29static volatile bool bootloader_active = false; 35static volatile bool bootloader_active = false;
30static volatile bool bootload_enable = false; 36static volatile bool bootload_enable = false;
37
38
31/*---------------------------------------------------------------------------*/ 39/*---------------------------------------------------------------------------*/
32int main(void) { 40int main(void) {
33 41
42 int i;
43
34 // Disable Watchdog 44 // Disable Watchdog
35 WDTCTL = WDTPW + WDTHOLD; 45 WDTCTL = WDTPW + WDTHOLD;
36 46
@@ -39,7 +49,6 @@ int main(void) {
39 BCSCTL1 |= (BIT3 + BIT1 + BIT0); 49 BCSCTL1 |= (BIT3 + BIT1 + BIT0);
40 50
41 /* 51 /*
42 * Configure MCLK, SMCLK, ACLK
43 MCLK = DCO / 1 = 4.25 MHz 52 MCLK = DCO / 1 = 4.25 MHz
44 SMCLK = DCO / 1 = 4.25 MHz 53 SMCLK = DCO / 1 = 4.25 MHz
45 ACLK = VLOCLK / 8 = 12 kHz / 8 = 1.5 kHz 54 ACLK = VLOCLK / 8 = 12 kHz / 8 = 1.5 kHz
@@ -47,41 +56,51 @@ int main(void) {
47 BCSCTL1 |= (XT2OFF + DIVA_3); 56 BCSCTL1 |= (XT2OFF + DIVA_3);
48 BCSCTL3 |= (LFXT1S_2); 57 BCSCTL3 |= (LFXT1S_2);
49 58
50 // Configure P1 input and ouput 59 /* Wait Oscillator stable */
60 while (IFG1 & OFIFG) // OSCFault flag still set?
61 {
62 IFG1 &= ~OFIFG; // Clear OSCFault flag
63 for (i = 0xFFF; i > 0; i--); // Time for flag to set
64 }
65
66 // Startup Delay: avoid DTR/RTS glitches on FDTI initialization
67 TACCTL1 = CCIE;
68 TACCR1 = STARTUP_DELAY;
69 TACTL = (TASSEL_1 + MC_2 + TAIE + TACLR);
70 _BIS_SR(LPM3_bits + GIE);
71
72// Configure P1 input and ouput
51#ifdef MSP432 73#ifdef MSP432
52 P1DIR &= ~(RESET_IN1 + BOOT_IN1); 74 P1DIR &= ~(RESET_IN1 + BOOT_IN1);
53 P1DIR &= ~(RESET_OUT1); 75 P1DIR &= ~(RESET_OUT1);
54 P1DIR |= (BOOT_OUT1); 76 P1DIR |= (BOOT_OUT1);
55 P1OUT |= (BOOT_OUT1); 77 P1OUT |= (BOOT_OUT1);
56#endif 78#endif
57 79
58#ifdef CC2650 80#ifdef CC2650
59 P1DIR &= ~(RESET_IN2 + BOOT_IN2); 81 P1DIR &= ~(RESET_IN2 + BOOT_IN2);
60 P1DIR &= ~(RESET_OUT2); 82 P1DIR &= ~(RESET_OUT2);
61 P1DIR |= (BOOT_OUT2); 83 P1DIR |= (BOOT_OUT2);
62 P1OUT |= (BOOT_OUT2); 84 P1OUT |= (BOOT_OUT2);
63#endif 85#endif
64 86
65 // Wait for stabilization 87// Configure P1 ints
66 __delay_cycles(STARTUP_DELAY);
67
68#ifdef MSP432 88#ifdef MSP432
69 // Configure RESET_IN1 interrupt high to low 89 // Configure BOOT_IN1 interrupt high to low
70 P1IFG &= ~(RESET_IN1); 90 P1IFG &=~ (BOOT_IN1);
71 P1IES |= (RESET_IN1); 91 P1IES |= (BOOT_IN1);
72 P1IE |= (RESET_IN1); 92 P1IE |= (BOOT_IN1);
73#endif 93#endif
74 94
75#ifdef CC2650 95#ifdef CC2650
76 // Configure RESET_IN2 interrupt high to low 96 // Configure BOOT_IN2 interrupt high to low
77 P1IFG &= ~(RESET_IN2); 97 P1IFG &=~ (BOOT_IN2);
78 P1IES |= (RESET_IN2); 98 P1IES |= (BOOT_IN2);
79 P1IE |= (RESET_IN2); 99 P1IE |= (BOOT_IN2);
80#endif 100#endif
81 101
82 // Forever 102 // Forever: Go to the lowest LPM
83 while (1) { 103 while (1) {
84 // Go to the lowest LPM
85 if (bootloader_active == true) { 104 if (bootloader_active == true) {
86 _BIS_SR(LPM3_bits + GIE); 105 _BIS_SR(LPM3_bits + GIE);
87 } else { 106 } else {
@@ -96,180 +115,262 @@ int main(void) {
96#pragma vector=PORT1_VECTOR 115#pragma vector=PORT1_VECTOR
97__interrupt void port1_isr (void) { 116__interrupt void port1_isr (void) {
98 117
118 int flag=0;
119
99#ifdef MSP432 120#ifdef MSP432
100 // RESET_IN1 high to low 121
101 if (((P1IFG & RESET_IN1) == RESET_IN1) && 122 // BOOT_IN2 high to low
123 if (((P1IFG & BOOT_IN1) == BOOT_IN1) &&
124 ((P1IN & BOOT_IN1) == 0) &&
125 ((P1IES & BOOT_IN1) == BOOT_IN1)) {
126
127 // BOOT_IN2 interrupt clear and disable
128 P1IFG &=~ (BOOT_IN1);
129 P1IE &=~ (BOOT_IN1);
130
131 flag=1;
132
133 /* Disable CC2650 BSL */
134 P1IFG &=~(RESET_IN2|BOOT_IN2);
135 P1IE &=~(RESET_IN2|BOOT_IN2);
136
137 /* Enable Reset High to Low */
138 P1IES |= (RESET_IN1);
139 P1IFG &=~ (RESET_IN1);
140 P1IE |= (RESET_IN1);
141
142 // RESET_IN1 should be low
143 if ((P1IN & RESET_IN1) == 0) {
144 bootloader_active = true;
145 }
146 }
147
148
149 // RESET_IN1 high to low
150 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
102 ((P1IN & RESET_IN1) == 0) && 151 ((P1IN & RESET_IN1) == 0) &&
103 ((P1IES & RESET_IN1) == RESET_IN1)) { 152 ((P1IES & RESET_IN1) == RESET_IN1)) {
104 153
105 // RESET_IN1 interrupt clear 154 // RESET_IN1 interrupt clear and disable
106 P1IFG &= ~(RESET_IN1); 155 P1IFG &=~(RESET_IN1);
156 P1IE &=~(RESET_IN1);
107 157
108 // RESET_IN1 low to high 158 flag=1;
109 P1IES &= ~(RESET_IN1);
110 // BOOT_IN1 high to low
111 P1IES |= (BOOT_IN1);
112 P1IE |= (RESET_IN1 + BOOT_IN1);
113 159
114 // TIMERA0 configure 160 /* Enable Reset_IN Low to High */
115 CCR0 = BOOTLOADER_TIMEOUT; 161 P1IES &=~ (RESET_IN1);
116 CCTL0 = (CCIE); 162 P1IFG &=~ (RESET_IN1);
117 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR); 163 P1IE |= (RESET_IN1);
118 164
119 // Set bootloader_active 165 // Enable Bootload
120 bootloader_active = true; 166 bootload_enable = true;
121 } 167 }
122 168
123 // BOOT_IN1 high to low
124 if (((P1IFG & BOOT_IN1) == BOOT_IN1) &&
125 ((P1IN & BOOT_IN1) == 0) &&
126 ((P1IES & BOOT_IN1) == BOOT_IN1)) {
127 // BOOT_IN1 interrupt clear
128 P1IFG &= ~(BOOT_IN1);
129 169
130 // RESET_IN1 should be low
131 if ((P1IN & RESET_IN1) == 0) {
132 bootload_enable = true;
133 }
134 }
135 170
136 // RESET_IN1 low to high 171 // RESET_IN1 low to high
137 if (((P1IFG & RESET_IN1) == RESET_IN1) && 172 if (((P1IFG & RESET_IN1) == RESET_IN1) &&
138 ((P1IN & RESET_IN1) == RESET_IN1) && 173 ((P1IN & RESET_IN1) == RESET_IN1) &&
139 ((P1IES & RESET_IN1) == 0)) { 174 ((P1IES & RESET_IN1) == 0)) {
140 // RESET_IN1 interrupt clear 175
141 P1IFG &= ~(RESET_IN1); 176 // RESET_IN1 interrupt clear and dsiable
142 177 P1IFG &=~(RESET_IN1);
143 // RESET_IN1 and BOOT_IN1 disable 178 P1IE &= ~(RESET_IN1);
144 P1IE &= ~(RESET_IN1 + BOOT_IN1); 179
145 180 flag=1;
146 // If bootload_enable is set 181
147 if (bootload_enable == true) { 182 // If bootload_enable is set
148 // RESET_OUT1 is now ouput 183 if (bootload_enable == true) {
149 P1DIR |= (RESET_OUT1); 184
150 //__delay_cycles(STARTUP_DELAY); 185 // RESET_OUT1 ouput
151 P1OUT &= ~(BOOT_OUT1); 186 P1DIR |= (RESET_OUT1);
152 __delay_cycles(STARTUP_DELAY); 187 P1OUT &= ~(BOOT_OUT1);
153 /* Reset Pulse */ 188
154 P1OUT &=~(RESET_OUT1); 189 // Reset Pulse
155 __delay_cycles(MSEC_DELAY); 190 __delay_cycles(MSEC_DELAY);
156 P1OUT |= (RESET_OUT1); 191 P1OUT &=~(RESET_OUT1);
157 __delay_cycles(BOOTLOADER_DELAY); 192 __delay_cycles(MSEC_DELAY);
158 193 P1OUT |= (RESET_OUT1);
159 /* Release Boot Pin*/ 194
160 P1OUT |= (BOOT_OUT1); 195 __delay_cycles(MSP432_BSL_DELAY);
161 // RESET_OUT1 is now input 196 // Release Boot Pin
162 P1DIR &= ~(RESET_OUT1); 197 P1OUT |= (BOOT_OUT1);
163 } 198 P1DIR &= ~(RESET_OUT1);
199
200 }
164 } 201 }
165#endif 202#endif
166 203
167#ifdef CC2650 204#ifdef CC2650
168 // RESET_IN1 high to low
169 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
170 ((P1IN & RESET_IN2) == 0) &&
171 ((P1IES & RESET_IN2) == RESET_IN2)) {
172
173 // RESET_IN2 interrupt clear
174 P1IFG &= ~(RESET_IN2);
175 205
176 // RESET_IN2 low to high
177 // BOOT_IN2 high to low 206 // BOOT_IN2 high to low
178 P1IES &= ~(RESET_IN2); 207 if (((P1IFG & BOOT_IN2) == BOOT_IN2) &&
179 P1IES |= (BOOT_IN2); 208 ((P1IN & BOOT_IN2) == 0) &&
180 P1IE |= (RESET_IN2 + BOOT_IN2); 209 ((P1IES & BOOT_IN2) == BOOT_IN2)) {
181 210
182 // TIMERA0 configure 211 // BOOT_IN2 interrupt clear and disable
183 CCR0 = BOOTLOADER_TIMEOUT; 212 P1IFG &=~ (BOOT_IN2);
184 CCTL0 = (CCIE); 213 P1IE &=~ (BOOT_IN2);
185 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
186 214
187 // Set bootloader_active 215 flag=1;
188 bootloader_active = true;
189 }
190 216
191 // BOOT_IN2 high to low 217 /* Disable MCP432 Boot */
192 if (((P1IFG & BOOT_IN2) == BOOT_IN2) && 218 P1IFG &=~(RESET_IN1|BOOT_IN1);
193 ((P1IN & BOOT_IN2) == 0) && 219 P1IE &=~(RESET_IN1|BOOT_IN1);
194 ((P1IES & BOOT_IN2) == BOOT_IN2)) {
195 220
196 // BOOT_IN2 interrupt clear 221 /* Enable Reset High to Low */
197 P1IFG &= ~(BOOT_IN2); 222 P1IES |= (RESET_IN2);
223 P1IFG &=~ (RESET_IN2);
224 P1IE |= (RESET_IN2);
198 225
199 // RESET_IN1 should be low 226 // RESET_IN2 should be low
200 if ((P1IN & RESET_IN2) == 0) { 227 if ((P1IN & RESET_IN2) == 0) {
201 bootload_enable = true; 228 bootloader_active = true;
229 }
202 } 230 }
203 }
204 231
205 // RESET_IN1 low to high 232
206 if (((P1IFG & RESET_IN2) == RESET_IN2) && 233 // RESET_IN1 high to low
207 ((P1IN & RESET_IN2) == RESET_IN2) && 234 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
208 ((P1IES & RESET_IN2) == 0)) { 235 ((P1IN & RESET_IN2) == 0) &&
209 // RESET_IN1 interrupt clear 236 ((P1IES & RESET_IN2) == RESET_IN2)) {
210 P1IFG &= ~(RESET_IN2); 237
211 238 // RESET_IN2 interrupt clear
212 // RESET_IN1 and BOOT_IN1 disable 239 P1IFG &=~(RESET_IN2);
213 P1IE &= ~(RESET_IN2 + BOOT_IN2); 240 P1IE &=~(RESET_IN2);
214 241
215 // If bootload_enable is set 242 flag=1;
216 if (bootload_enable == true) { 243
217 // RESET_OUT1 is now ouput 244 /* Low to High */
218 P1DIR |= (RESET_OUT2); 245 P1IES &=~ (RESET_IN2);
219 //__delay_cycles(STARTUP_DELAY); 246 P1IFG &=~ (RESET_IN2);
220 P1OUT &= ~(BOOT_OUT2); 247 P1IE |= (RESET_IN2);
221 __delay_cycles(STARTUP_DELAY); 248
222 /* Reset Pulse */ 249 // Set bootloader_active
223 P1OUT &=~(RESET_OUT2); 250 bootload_enable = true;
224 __delay_cycles(MSEC_DELAY); 251 }
225 P1OUT |= (RESET_OUT2); 252
226 __delay_cycles(BOOTLOADER_DELAY); 253
227 254
228 /* Release Boot Pin*/ 255 // RESET_IN1 low to high
229 P1OUT |= (BOOT_OUT2); 256 if (((P1IFG & RESET_IN2) == RESET_IN2) &&
230 // RESET_OUT1 is now input 257 ((P1IN & RESET_IN2) == RESET_IN2) &&
231 P1DIR &= ~(RESET_OUT2); 258 ((P1IES & RESET_IN2) == 0)) {
232 } 259
233 } 260 // RESET_IN1 interrupt clear
261 P1IFG &=~(RESET_IN2);
262 P1IE &= ~(RESET_IN2);
263
264 flag=1;
265
266 // If bootload_enable is set
267 if (bootload_enable == true) {
268
269 // RESET_OUT1 is now ouput
270 P1DIR |= (RESET_OUT2);
271 //__delay_cycles(STARTUP_DELAY);
272 P1OUT &= ~(BOOT_OUT2);
273
274 /* Reset Pulse */
275 __delay_cycles(425);
276 P1OUT &=~(RESET_OUT2);
277 __delay_cycles(MSEC_DELAY);
278 P1OUT |= (RESET_OUT2);
279 __delay_cycles(CC2650_BSL_DELAY);
280
281 /* Release Boot Pin*/
282 P1OUT |= (BOOT_OUT2);
283 // RESET_OUT2 is now input
284 P1DIR &= ~(RESET_OUT2);
285 }
286 }
234#endif 287#endif
235 288
289 // Set TIMER_A-CCR0 Timout
290 TACCR0 = BOOTLOADER_TIMEOUT;
291 TACCTL0 = (CCIE);
292 TACTL = (TASSEL_1 + MC_1 + TAIE + TACLR);
293
294 if(flag==0){
295 P1IFG = 0;
296 }
297
236 _BIC_SR_IRQ(LPM4_bits + GIE); 298 _BIC_SR_IRQ(LPM4_bits + GIE);
299
237} 300}
238/*---------------------------------------------------------------------------*/ 301/*---------------------------------------------------------------------------*/
239#pragma vector=TIMERA0_VECTOR 302#pragma vector=TIMERA0_VECTOR
240__interrupt void timera0_isr (void) { 303__interrupt void timera0_isr (void) {
241 304
242 // TIMERA0 reset 305 // TIMERA0 reset
243 TACTL = 0; 306 TACTL = 0;
244 CCTL0 &=~(CCIE); 307 TACCTL0 &=~(CCIE);
245 308
246 // Clear variables 309 // Clear variables
247 bootloader_active = false; 310 bootloader_active = false;
248 bootload_enable = false; 311 bootload_enable = false;
249 312
250#ifdef MSP432 313#ifdef MSP432
314
251 // Ensure RESET_OUT1 and BOOT_OUT1 are high 315 // Ensure RESET_OUT1 and BOOT_OUT1 are high
252 P1OUT |= (RESET_OUT1 + BOOT_OUT1); 316 P1OUT |= (RESET_OUT1 + BOOT_OUT1);
253 P1DIR &=~(RESET_OUT1); 317 P1DIR &=~(RESET_OUT1);
254 318
255 // (Re)Enable RESET_IN1 high to low Int 319 // (Re)Enable BOOT_IN1 high to low Int
256 P1IES |= (RESET_IN1); 320 P1IES |= (BOOT_IN1);
257 P1IFG &= ~(RESET_IN1+BOOT_IN1); 321 P1IFG &= ~(RESET_IN1+BOOT_IN1);
258 P1IE |= (RESET_IN1); 322 P1IE &=~ (RESET_IN1);
323 P1IE |= (BOOT_IN1);
259#endif 324#endif
260 325
326
261#ifdef CC2650 327#ifdef CC2650
262 // Ensure RESET_OUT2 and BOOT_OUT2 are high 328 // Ensure RESET_OUT2 and BOOT_OUT2 are high
263 P1OUT |= (RESET_OUT2 + BOOT_OUT2); 329 P1OUT |= (RESET_OUT2 + BOOT_OUT2);
264 P1DIR &=~(RESET_OUT2); 330 P1DIR &=~(RESET_OUT2);
265 331
266 // (Re)Enable RESET_IN2 high to low Int 332 // (Re)Enable RESET_IN2 high to low Int
267 P1IES |= (RESET_IN2); 333 P1IES |= (BOOT_IN2);
268 P1IFG &= ~(RESET_IN2+BOOT_IN2); 334 P1IFG &= ~(RESET_IN2+BOOT_IN2);
269 P1IE |= (RESET_IN2); 335 P1IE &=~ (RESET_IN2);
336 P1IE |= (BOOT_IN2);
270#endif 337#endif
271 338
339
272 _BIC_SR_IRQ(LPM3_bits + GIE); 340 _BIC_SR_IRQ(LPM3_bits + GIE);
273 341
274} 342}
343
344#pragma vector=TIMERA1_VECTOR
345__interrupt void timera1_isr (void) {
346
347
348 switch(TAIV)
349 {
350 case TAIV_TACCR1: // CCR1
351 {
352 TACTL = 0;
353 TACCTL1 &=~(CCIE);
354 }
355 break;
356
357 case TAIV_TAIFG: // overflow not used
358 break;
359
360 }
361
362 _BIC_SR_IRQ(LPM3_bits + GIE);
363
364}
365
366
367/*
368#pragma vector=NMI_VECTOR
369__interrupt void nmi_isr (void) {
370 _BIC_SR_IRQ(LPM3_bits + GIE);
371}
372*/
373
374
375
275/*---------------------------------------------------------------------------*/ 376/*---------------------------------------------------------------------------*/