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authorBorja Martinez2016-09-10 09:29:11 -0500
committerBorja Martinez2016-09-10 09:29:11 -0500
commitd3b6449727b9a0dccfce53754bfcfd5e8ee24e6c (patch)
tree2d8c6017d4214465ab13115d5f61f3fdb482ae52
parent73dd92ace9935733181337e2ac6543825b75ad00 (diff)
downloadi3-mote-d3b6449727b9a0dccfce53754bfcfd5e8ee24e6c.tar.gz
i3-mote-d3b6449727b9a0dccfce53754bfcfd5e8ee24e6c.tar.xz
i3-mote-d3b6449727b9a0dccfce53754bfcfd5e8ee24e6c.zip
Test MSP432 Blink Leds
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h15
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c78
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c254
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c369
5 files changed, 800 insertions, 0 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h
new file mode 100644
index 0000000..fc06eaa
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/i3mote.h
@@ -0,0 +1,15 @@
1
2
3/* Rev.B */
4#define HID_PORT GPIO_PORT_P6
5#define LEDR GPIO_PIN2
6#define LEDG GPIO_PIN3
7#define BUTTON GPIO_PIN1
8
9
10/* Rev.A
11#define LED_PORT GPIO_PORT_P8
12#define LEDR GPIO_PIN5
13#define LEDG GPIO_PIN6
14#define BUTTON GPIO_PIN7
15*/
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c
new file mode 100644
index 0000000..7011617
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/main.c
@@ -0,0 +1,78 @@
1/*******************************************************************************
2 * MSP432 Clock System - HFXT Startup
3 *
4 * Description: Starts the DCO to 48MHz sources MCLK from it,
5 * Blinks two LEDs using SysTick (which is sourced from MCLK).
6 *
7 *
8 * MSP432P401
9 * ------------------
10 * /|\| |
11 * --|RST |
12 * | |---> LEDG
13 * BT1 --->| |---> LEDR
14 * | |
15 * | < 12Mhz DCO > |
16 * | |
17 *
18 * Author: B.Martinez
19 ******************************************************************************/
20#include "i3mote.h"
21
22
23/* DriverLib Includes */
24#include "driverlib.h"
25
26/* Standard Includes */
27#include <stdint.h>
28#include <stdbool.h>
29
30
31int main(void)
32{
33 /* Halting the Watchdog */
34 MAP_WDT_A_holdTimer();
35
36 /* Set Button Pin as Input */
37 MAP_GPIO_setAsInputPin(HID_PORT,BUTTON);
38
39 /* Set LED Pins as Output */
40 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
41
42 /* Set LED Initial Value */
43 MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDG);
44 //MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDR);
45 MAP_GPIO_setOutputHighOnPin(HID_PORT, LEDR);
46
47 /* Setting the external clock frequency (This API is optional) */
48 CS_setExternalClockSourceFrequency(32000,12000000);
49
50 /* Initializes MCLK Clocks System with DCO */
51 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
52 MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
53
54 /*
55 * Configuring SysTick to trigger at 6000000
56 * MCLK is 12MHz so this will make it toggle every 0.5s
57 */
58 MAP_SysTick_enableModule();
59 MAP_SysTick_setPeriod(6000000);
60 MAP_Interrupt_enableSleepOnIsrExit();
61 MAP_SysTick_enableInterrupt();
62
63 /* Enabling MASTER interrupts */
64 MAP_Interrupt_enableMaster();
65
66 while (1)
67 {
68 MAP_PCM_gotoLPM0();
69 }
70}
71
72void SysTick_Handler(void)
73{
74 if(MAP_GPIO_getInputPinValue(HID_PORT,BUTTON)){
75 MAP_GPIO_toggleOutputOnPin(GPIO_PORT_P6, GPIO_PIN2|GPIO_PIN3);
76 }
77
78}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd
new file mode 100644
index 0000000..346c191
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/msp432p401r.cmd
@@ -0,0 +1,84 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c
new file mode 100644
index 0000000..d5f9a14
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/startup_msp432p401r_ccs.c
@@ -0,0 +1,254 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37//*****************************************************************************
38//
39// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
40//
41// Redistribution and use in source and binary forms, with or without
42// modification, are permitted provided that the following conditions
43// are met:
44//
45// Redistributions of source code must retain the above copyright
46// notice, this list of conditions and the following disclaimer.
47//
48// Redistributions in binary form must reproduce the above copyright
49// notice, this list of conditions and the following disclaimer in the
50// documentation and/or other materials provided with the
51// distribution.
52//
53// Neither the name of Texas Instruments Incorporated nor the names of
54// its contributors may be used to endorse or promote products derived
55// from this software without specific prior written permission.
56//
57// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
60// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
63// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
64// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
67// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68//
69// MSP432 Family Interrupt Vector Table for CGT
70//
71//****************************************************************************
72
73#include <stdint.h>
74
75/* Forward declaration of the default fault handlers. */
76static void resetISR(void);
77static void nmiISR(void);
78static void faultISR(void);
79static void defaultISR(void);
80
81
82/* External declaration for the reset handler that is to be called when the */
83/* processor is started */
84extern void _c_int00(void);
85
86/* External declaration for system initialization function */
87extern void SystemInit(void);
88
89/* Linker variable that marks the top of the stack. */
90extern unsigned long __STACK_END;
91
92
93/* External declarations for the interrupt handlers used by the application. */
94extern void SysTick_Handler(void);
95
96
97/* Interrupt vector table. Note that the proper constructs must be placed on this to */
98/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
99/* the program if located at a start address other than 0. */
100#pragma RETAIN(interruptVectors)
101#pragma DATA_SECTION(interruptVectors, ".intvecs")
102void (* const interruptVectors[])(void) =
103{
104 (void (*)(void))((uint32_t)&__STACK_END),
105 /* The initial stack pointer */
106 resetISR, /* The reset handler */
107 nmiISR, /* The NMI handler */
108 faultISR, /* The hard fault handler */
109 defaultISR, /* The MPU fault handler */
110 defaultISR, /* The bus fault handler */
111 defaultISR, /* The usage fault handler */
112 0, /* Reserved */
113 0, /* Reserved */
114 0, /* Reserved */
115 0, /* Reserved */
116 defaultISR, /* SVCall handler */
117 defaultISR, /* Debug monitor handler */
118 0, /* Reserved */
119 defaultISR, /* The PendSV handler */
120 SysTick_Handler, /* The SysTick handler */
121 defaultISR, /* PSS ISR */
122 defaultISR, /* CS ISR */
123 defaultISR, /* PCM ISR */
124 defaultISR, /* WDT ISR */
125 defaultISR, /* FPU ISR */
126 defaultISR, /* FLCTL ISR */
127 defaultISR, /* COMP0 ISR */
128 defaultISR, /* COMP1 ISR */
129 defaultISR, /* TA0_0 ISR */
130 defaultISR, /* TA0_N ISR */
131 defaultISR, /* TA1_0 ISR */
132 defaultISR, /* TA1_N ISR */
133 defaultISR, /* TA2_0 ISR */
134 defaultISR, /* TA2_N ISR */
135 defaultISR, /* TA3_0 ISR */
136 defaultISR, /* TA3_N ISR */
137 defaultISR, /* EUSCIA0 ISR */
138 defaultISR, /* EUSCIA1 ISR */
139 defaultISR, /* EUSCIA2 ISR */
140 defaultISR, /* EUSCIA3 ISR */
141 defaultISR, /* EUSCIB0 ISR */
142 defaultISR, /* EUSCIB1 ISR */
143 defaultISR, /* EUSCIB2 ISR */
144 defaultISR, /* EUSCIB3 ISR */
145 defaultISR, /* ADC14 ISR */
146 defaultISR, /* T32_INT1 ISR */
147 defaultISR, /* T32_INT2 ISR */
148 defaultISR, /* T32_INTC ISR */
149 defaultISR, /* AES ISR */
150 defaultISR, /* RTC ISR */
151 defaultISR, /* DMA_ERR ISR */
152 defaultISR, /* DMA_INT3 ISR */
153 defaultISR, /* DMA_INT2 ISR */
154 defaultISR, /* DMA_INT1 ISR */
155 defaultISR, /* DMA_INT0 ISR */
156 defaultISR, /* PORT1 ISR */
157 defaultISR, /* PORT2 ISR */
158 defaultISR, /* PORT3 ISR */
159 defaultISR, /* PORT4 ISR */
160 defaultISR, /* PORT5 ISR */
161 defaultISR, /* PORT6 ISR */
162 defaultISR, /* Reserved 41 */
163 defaultISR, /* Reserved 42 */
164 defaultISR, /* Reserved 43 */
165 defaultISR, /* Reserved 44 */
166 defaultISR, /* Reserved 45 */
167 defaultISR, /* Reserved 46 */
168 defaultISR, /* Reserved 47 */
169 defaultISR, /* Reserved 48 */
170 defaultISR, /* Reserved 49 */
171 defaultISR, /* Reserved 50 */
172 defaultISR, /* Reserved 51 */
173 defaultISR, /* Reserved 52 */
174 defaultISR, /* Reserved 53 */
175 defaultISR, /* Reserved 54 */
176 defaultISR, /* Reserved 55 */
177 defaultISR, /* Reserved 56 */
178 defaultISR, /* Reserved 57 */
179 defaultISR, /* Reserved 58 */
180 defaultISR, /* Reserved 59 */
181 defaultISR, /* Reserved 60 */
182 defaultISR, /* Reserved 61 */
183 defaultISR, /* Reserved 62 */
184 defaultISR /* Reserved 63 */
185};
186
187
188/* This is the code that gets called when the processor first starts execution */
189/* following a reset event. Only the absolutely necessary set is performed, */
190/* after which the application supplied entry() routine is called. Any fancy */
191/* actions (such as making decisions based on the reset cause register, and */
192/* resetting the bits in that register) are left solely in the hands of the */
193/* application. */
194void resetISR(void)
195{
196 SystemInit();
197
198 /* Jump to the CCS C Initialization Routine. */
199 __asm(" .global _c_int00\n"
200 " b.w _c_int00");
201}
202
203/* This is the code that gets called when the processor receives a NMI. This */
204/* simply enters an infinite loop, preserving the system state for examination */
205/* by a debugger. */
206static void nmiISR(void)
207{
208 /* Fault trap exempt from ULP advisor */
209 #pragma diag_push
210 #pragma CHECK_ULP("-2.1")
211
212 /* Enter an infinite loop. */
213 while(1)
214 {
215 }
216
217 #pragma diag_pop
218}
219
220
221/* This is the code that gets called when the processor receives a fault */
222/* interrupt. This simply enters an infinite loop, preserving the system state */
223/* for examination by a debugger. */
224static void faultISR(void)
225{
226 /* Fault trap exempt from ULP advisor */
227 #pragma diag_push
228 #pragma CHECK_ULP("-2.1")
229
230 /* Enter an infinite loop. */
231 while(1)
232 {
233 }
234
235 #pragma diag_pop
236}
237
238
239/* This is the code that gets called when the processor receives an unexpected */
240/* interrupt. This simply enters an infinite loop, preserving the system state */
241/* for examination by a debugger. */
242static void defaultISR(void)
243{
244 /* Fault trap exempt from ULP advisor */
245 #pragma diag_push
246 #pragma CHECK_ULP("-2.1")
247
248 /* Enter an infinite loop. */
249 while(1)
250 {
251 }
252
253 #pragma diag_pop
254}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c
new file mode 100644
index 0000000..4dcf1da
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_Blink_SysTick/system_msp432p401r.c
@@ -0,0 +1,369 @@
1/*
2
3/**************************************************************************//**
4* @file system_msp432p401r.c
5* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
6* MSP432P401R
7* @version V1.00
8* @date 20-Oct-2015
9*
10* @note View configuration instructions embedded in comments
11*
12******************************************************************************/
13
14//*****************************************************************************
15
16#include <stdint.h>
17#include "msp.h"
18
19/*--------------------- Configuration Instructions ----------------------------
20 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
21 #define __HALT_WDT 1
22 2. Insert your desired CPU frequency in Hz at:
23 #define __SYSTEM_CLOCK 3000000
24 3. If you prefer the DC-DC power regulator (more efficient at higher
25 frequencies), set the __REGULATOR to 1:
26 #define __REGULATOR 1
27 *---------------------------------------------------------------------------*/
28
29/*--------------------- Watchdog Timer Configuration ------------------------*/
30// Halt the Watchdog Timer
31// <0> Do not halt the WDT
32// <1> Halt the WDT
33#define __HALT_WDT 1
34
35/*--------------------- CPU Frequency Configuration -------------------------*/
36// CPU Frequency
37// <1500000> 1.5 MHz
38// <3000000> 3 MHz
39// <12000000> 12 MHz
40// <24000000> 24 MHz
41// <48000000> 48 MHz
42#define __SYSTEM_CLOCK 12000000
43
44/*--------------------- Power Regulator Configuration -----------------------*/
45// Power Regulator Mode
46// <0> LDO
47// <1> DC-DC
48#define __REGULATOR 1
49
50/*----------------------------------------------------------------------------
51 Define clocks, used for SystemCoreClockUpdate()
52 *---------------------------------------------------------------------------*/
53#define __VLOCLK 10000
54#define __MODCLK 24000000
55#define __LFXT 32768
56#define __HFXT 48000000
57
58/*----------------------------------------------------------------------------
59 Clock Variable definitions
60 *---------------------------------------------------------------------------*/
61uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
62
63/**
64 * Update SystemCoreClock variable
65 *
66 * @param none
67 * @return none
68 *
69 * @brief Updates the SystemCoreClock with current core Clock
70 * retrieved from cpu registers.
71 */
72void SystemCoreClockUpdate(void)
73{
74 uint32_t source, divider;
75 uint8_t dividerValue;
76
77 float dcoConst;
78 int32_t calVal;
79 uint32_t centeredFreq;
80 int16_t dcoTune;
81
82 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
83 dividerValue = 1 << divider;
84 source = CS->CTL1 & CS_CTL1_SELM_MASK;
85
86 switch(source)
87 {
88 case CS_CTL1_SELM__LFXTCLK:
89 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
90 {
91 // Clear interrupt flag
92 CS->KEY = CS_KEY_VAL;
93 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
94 CS->KEY = 1;
95
96 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
97 {
98 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
99 {
100 SystemCoreClock = (128000 / dividerValue);
101 }
102 else
103 {
104 SystemCoreClock = (32000 / dividerValue);
105 }
106 }
107 else
108 {
109 SystemCoreClock = __LFXT / dividerValue;
110 }
111 }
112 else
113 {
114 SystemCoreClock = __LFXT / dividerValue;
115 }
116 break;
117 case CS_CTL1_SELM__VLOCLK:
118 SystemCoreClock = __VLOCLK / dividerValue;
119 break;
120 case CS_CTL1_SELM__REFOCLK:
121 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
122 {
123 SystemCoreClock = (128000 / dividerValue);
124 }
125 else
126 {
127 SystemCoreClock = (32000 / dividerValue);
128 }
129 break;
130 case CS_CTL1_SELM__DCOCLK:
131 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
132
133 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
134 {
135 case CS_CTL0_DCORSEL_0:
136 centeredFreq = 1500000;
137 break;
138 case CS_CTL0_DCORSEL_1:
139 centeredFreq = 3000000;
140 break;
141 case CS_CTL0_DCORSEL_2:
142 centeredFreq = 6000000;
143 break;
144 case CS_CTL0_DCORSEL_3:
145 centeredFreq = 12000000;
146 break;
147 case CS_CTL0_DCORSEL_4:
148 centeredFreq = 24000000;
149 break;
150 case CS_CTL0_DCORSEL_5:
151 centeredFreq = 48000000;
152 break;
153 }
154
155 if(dcoTune == 0)
156 {
157 SystemCoreClock = centeredFreq;
158 }
159 else
160 {
161
162 if(dcoTune & 0x1000)
163 {
164 dcoTune = dcoTune | 0xF000;
165 }
166
167 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
168 {
169 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
170 calVal = TLV->DCOER_FCAL_RSEL04;
171 }
172 /* Internal Resistor */
173 else
174 {
175 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
176 calVal = TLV->DCOIR_FCAL_RSEL04;
177 }
178
179 SystemCoreClock = (uint32_t) ((centeredFreq)
180 / (1
181 - ((dcoConst * dcoTune)
182 / (8 * (1 + dcoConst * (768 - calVal))))));
183 }
184 break;
185 case CS_CTL1_SELM__MODOSC:
186 SystemCoreClock = __MODCLK / dividerValue;
187 break;
188 case CS_CTL1_SELM__HFXTCLK:
189 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
190 {
191 // Clear interrupt flag
192 CS->KEY = CS_KEY_VAL;
193 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
194 CS->KEY = 1;
195
196 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
197 {
198 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
199 {
200 SystemCoreClock = (128000 / dividerValue);
201 }
202 else
203 {
204 SystemCoreClock = (32000 / dividerValue);
205 }
206 }
207 else
208 {
209 SystemCoreClock = __HFXT / dividerValue;
210 }
211 }
212 else
213 {
214 SystemCoreClock = __HFXT / dividerValue;
215 }
216 break;
217 }
218}
219
220/**
221 * Initialize the system
222 *
223 * @param none
224 * @return none
225 *
226 * @brief Setup the microcontroller system.
227 *
228 * Performs the following initialization steps:
229 * 1. Enables the FPU
230 * 2. Halts the WDT if requested
231 * 3. Enables all SRAM banks
232 * 4. Sets up power regulator and VCORE
233 * 5. Enable Flash wait states if needed
234 * 6. Change MCLK to desired frequency
235 * 7. Enable Flash read buffering
236 */
237void SystemInit(void)
238{
239 // Enable FPU if used
240 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
241 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
242 (3UL << 11 * 2)); /* Set CP11 Full Access */
243 #endif
244
245 #if (__HALT_WDT == 1)
246 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
247 #endif
248
249 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
250
251 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
252 // Default VCORE is LDO VCORE0 so no change necessary
253
254 // Switches LDO VCORE0 to DCDC VCORE0 if requested
255 #if __REGULATOR
256 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
257 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
258 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
259 #endif
260
261 // No flash wait states necessary
262
263 // DCO = 1.5 MHz; MCLK = source
264 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
265 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
266 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
267 CS->KEY = 0;
268
269 // Set Flash Bank read buffering
270 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
271 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
272
273 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
274 // Default VCORE is LDO VCORE0 so no change necessary
275
276 // Switches LDO VCORE0 to DCDC VCORE0 if requested
277 #if __REGULATOR
278 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
279 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
280 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
281 #endif
282
283 // No flash wait states necessary
284
285 // DCO = 3 MHz; MCLK = source
286 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
287 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
288 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
289 CS->KEY = 0;
290
291 // Set Flash Bank read buffering
292 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
293 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
294
295 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
296 // Default VCORE is LDO VCORE0 so no change necessary
297
298 // Switches LDO VCORE0 to DCDC VCORE0 if requested
299 #if __REGULATOR
300 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
301 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
302 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
303 #endif
304
305 // No flash wait states necessary
306
307 // DCO = 12 MHz; MCLK = source
308 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
309 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
310 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
311 CS->KEY = 0;
312
313 // Set Flash Bank read buffering
314 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
315 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
316
317 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
318 // Default VCORE is LDO VCORE0 so no change necessary
319
320 // Switches LDO VCORE0 to DCDC VCORE0 if requested
321 #if __REGULATOR
322 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
323 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
324 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
325 #endif
326
327 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
328 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
329 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
330
331 // DCO = 24 MHz; MCLK = source
332 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
333 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
334 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
335 CS->KEY = 0;
336
337 // Set Flash Bank read buffering
338 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
339 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
340
341 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
342 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
343 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
344 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
345 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
346
347 // Switches LDO VCORE1 to DCDC VCORE1 if requested
348 #if __REGULATOR
349 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
350 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
351 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
352 #endif
353
354 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
355 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
356 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
357
358 // DCO = 48 MHz; MCLK = source
359 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
360 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
361 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
362 CS->KEY = 0;
363
364 // Set Flash Bank read buffering
365 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
366 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
367 #endif
368
369}