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authorBorja Martinez2016-09-10 12:09:15 -0500
committerBorja Martinez2016-09-10 12:09:15 -0500
commitdfc5c91b9f14f56e4be572c28fd2c825b0e1c6b3 (patch)
treea49fcef7e08d082d6288e97e885f0bcb8d0486fe
parenta99955e7fde336f52fd81b00eb4e998768c5aaf5 (diff)
downloadi3-mote-dfc5c91b9f14f56e4be572c28fd2c825b0e1c6b3.tar.gz
i3-mote-dfc5c91b9f14f56e4be572c28fd2c825b0e1c6b3.tar.xz
i3-mote-dfc5c91b9f14f56e4be572c28fd2c825b0e1c6b3.zip
Created Test MSP432 I2C M24xx256
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c202
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h48
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h16
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c91
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd104
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c219
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c399
7 files changed, 1079 insertions, 0 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c
new file mode 100644
index 0000000..b30f071
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.c
@@ -0,0 +1,202 @@
1/* --COPYRIGHT--,BSD
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * --/COPYRIGHT--*/
32//****************************************************************************
33//
34// HAL_I2C.c - Hardware abstraction layer for I2C with MSP432P401R
35//
36//****************************************************************************
37
38#include <driverlib.h>
39#include <HAL_I2C.h>
40
41
42/* I2C Master Configuration Parameter */
43const eUSCI_I2C_MasterConfig i2cConfig =
44{
45 EUSCI_B_I2C_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
46 12000000, // SMCLK = 48MHz
47 EUSCI_B_I2C_SET_DATA_RATE_100KBPS, // Desired I2C Clock of 100khz
48 0, // No byte counter threshold
49 EUSCI_B_I2C_NO_AUTO_STOP // No Autostop
50};
51
52void Init_I2C_GPIO()
53{
54 /* Select I2C function for I2C_SCL(P6.5) */
55 GPIO_setAsPeripheralModuleFunctionOutputPin(
56 GPIO_PORT_P3,
57 GPIO_PIN7,
58 //GPIO_PORT_P6,
59 //GPIO_PIN5,
60 //GPIO_PORT_P1,
61 //GPIO_PIN7,
62 GPIO_PRIMARY_MODULE_FUNCTION);
63
64 /* Select I2C function for I2C_SDA(P6.4) */
65 GPIO_setAsPeripheralModuleFunctionOutputPin(
66 GPIO_PORT_P3,
67 GPIO_PIN6,
68 //GPIO_PORT_P6,
69 //GPIO_PIN4,
70 //GPIO_PORT_P1,
71 //GPIO_PIN6,
72 GPIO_PRIMARY_MODULE_FUNCTION);
73}
74
75
76/***************************************************************************//**
77 * @brief Configures I2C
78 * @param none
79 * @return none
80 ******************************************************************************/
81
82void I2C_init(void)
83{
84 /* Initialize USCI_B0 and I2C Master to communicate with slave devices*/
85 I2C_initMaster(EUSCI_B2_BASE, &i2cConfig);
86 //I2C_initMaster(EUSCI_B2_BASE, &i2cConfig);
87
88 /* Disable I2C module to make changes */
89 I2C_disableModule(EUSCI_B2_BASE);
90 //I2C_disableModule(EUSCI_B2_BASE);
91
92 /* Enable I2C Module to start operations */
93 I2C_enableModule(EUSCI_B2_BASE);
94 //I2C_enableModule(EUSCI_B2_BASE);
95
96 return;
97}
98
99
100/***************************************************************************//**
101 * @brief Reads data from the sensor
102 * @param writeByte Address of register to read from
103 * @return Register contents
104 ******************************************************************************/
105
106unsigned char I2C_eeprom_read_byte(unsigned short addr)
107{
108 volatile int val = 0;
109 volatile int valScratch = 0;
110
111 /* Set master to transmit mode PL */
112 I2C_setMode(EUSCI_B2_BASE,
113 EUSCI_B_I2C_TRANSMIT_MODE);
114
115 /* Clear any existing interrupt flag PL */
116 I2C_clearInterruptFlag(EUSCI_B2_BASE,
117 EUSCI_B_I2C_TRANSMIT_INTERRUPT0);
118
119 /* Wait until ready to write PL */
120 while (I2C_isBusBusy(EUSCI_B2_BASE));
121
122 /* Initiate start and send first character */
123 I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(addr>>8)&0x00FF);
124 /* Wait for TX to finish */
125 while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));
126
127 /* Send Next Character */
128 I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(addr&0x00FF));
129 /* Wait for TX to finish */
130 while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));
131
132 /* Initiate stop only */
133 I2C_masterSendMultiByteStop(EUSCI_B2_BASE);
134 /* Wait for Stop to finish */
135 while(!I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_STOP_INTERRUPT));
136
137 /*
138 * Generate Start condition and set it to receive mode.
139 * This sends out the slave address and continues to read until you issue a STOP
140 */
141
142 I2C_setMode(EUSCI_B2_BASE,EUSCI_B_I2C_RECEIVE_MODE);
143 while (I2C_isBusBusy(EUSCI_B2_BASE));
144
145 val=I2C_masterReceiveSingleByte(EUSCI_B2_BASE);
146
147 /* Return temperature value */
148 return val;
149}
150
151
152/***************************************************************************//**
153 * @brief Writes data to the sensor
154 * @param pointer Address of register you want to modify
155 * @param writeByte Data to be written to the specified register
156 * @return none
157 ******************************************************************************/
158
159void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte)
160{
161 /* Set master to transmit mode PL */
162 I2C_setMode(EUSCI_B2_BASE,
163 EUSCI_B_I2C_TRANSMIT_MODE);
164
165 /* Clear any existing interrupt flag PL */
166 I2C_clearInterruptFlag(EUSCI_B2_BASE,
167 EUSCI_B_I2C_TRANSMIT_INTERRUPT0);
168
169 /* Wait until ready to write PL */
170 while (I2C_isBusBusy(EUSCI_B2_BASE));
171
172 /* Initiate start and send first character */
173 I2C_masterSendMultiByteStart(EUSCI_B2_BASE,(unsigned char)(pointer>>8));
174 while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));
175
176
177 I2C_masterSendMultiByteNext(EUSCI_B2_BASE,(unsigned char)(pointer&0x00FF));
178 while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));
179
180
181 I2C_masterSendMultiByteFinish(EUSCI_B2_BASE,
182 (unsigned char)(writeByte&0xFF));
183 while(!(I2C_getInterruptStatus(EUSCI_B2_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0)));
184
185 while (I2C_isBusBusy(EUSCI_B2_BASE));
186
187}
188
189
190void I2C_setslave(unsigned int slaveAdr)
191{
192 /* Specify slave address for I2C */
193 //I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr);
194 I2C_setSlaveAddress(EUSCI_B2_BASE,slaveAdr);
195
196 /* Enable and clear the interrupt flag */
197 I2C_clearInterruptFlag(EUSCI_B2_BASE,
198 EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0);
199 //I2C_clearInterruptFlag(EUSCI_B2_BASE,
200 // EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT0);
201 return;
202}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h
new file mode 100644
index 0000000..917f385
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/HAL_I2C.h
@@ -0,0 +1,48 @@
1/* --COPYRIGHT--,BSD
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * --/COPYRIGHT--*/
32//****************************************************************************
33//
34// HAL_I2C.h - Prototypes of hardware abstraction layer for I2C between
35// MSP432P401R and OPT3001
36//
37//****************************************************************************
38
39#ifndef __HAL_I2C_H_
40#define __HAL_I2C_H_
41
42void Init_I2C_GPIO(void);
43void I2C_init(void);
44unsigned char I2C_eeprom_read_byte(unsigned short);
45void I2C_eeprom_write_byte(unsigned short pointer, unsigned char writeByte);
46void I2C_setslave(unsigned int slaveAdr);
47
48#endif /* __HAL_I2C_H_ */
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h
new file mode 100644
index 0000000..750f90e
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/i3mote.h
@@ -0,0 +1,16 @@
1/* Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7
8/* Rev.A
9#define LED_PORT GPIO_PORT_P8
10#define LEDR GPIO_PIN5
11#define LEDG GPIO_PIN6
12#define BUTTON GPIO_PIN7
13*/
14
15
16#define EEPROM_SLAVE_ADDRESS 0x50
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c
new file mode 100644
index 0000000..2c7286c
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/main.c
@@ -0,0 +1,91 @@
1//****************************************************************************
2//
3//
4//
5//****************************************************************************
6#include "i3mote.h"
7
8/* MSP432 Incldues */
9#include "msp.h"
10#include <driverlib.h>
11
12/* Standard Includes */
13#include <stdint.h>
14#include <stdio.h>
15#include <stdlib.h>
16
17
18/* I2C Support */
19#include <HAL_I2C.h>
20
21
22/* Local Definitions */
23#define NPOS 256 // EEPROM positions to Read/Write
24
25void main(void)
26{
27
28 unsigned short i=0;
29 unsigned short val;
30
31 /* Halting WDT and disabling master interrupts */
32 MAP_WDT_A_holdTimer();
33 MAP_Interrupt_disableMaster();
34
35 /* Initializes Clock System */
36 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
37 MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
38 MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
39 MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
40 MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
41
42 /* Disable GPS VCC */
43 MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P2,GPIO_PIN4);
44 MAP_GPIO_setAsOutputPin(GPIO_PORT_P2,GPIO_PIN4);
45
46 /* LEDs */
47 MAP_GPIO_setAsOutputPin(HID_PORT,LEDG|LEDR);
48 MAP_GPIO_setOutputLowOnPin(HID_PORT, LEDG|LEDR);
49
50 /* Initialize I2C communication */
51 Init_I2C_GPIO();
52 I2C_init();
53
54 I2C_setslave(EEPROM_SLAVE_ADDRESS);
55
56
57 for(i=0;i<NPOS;i++){
58 I2C_eeprom_write_byte((int16_t)i,i);
59 __delay_cycles(12000*10);
60 }
61
62 for(i=0;i<NPOS;i++){
63 val=I2C_eeprom_read_byte(i);
64 printf("%02X %02X\n",i,val);
65 if(val!=(0xFF&i)){
66 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
67 exit(-1);
68 }
69 }
70
71 for(i=0;i<NPOS;i++){
72 I2C_eeprom_write_byte((int16_t)i,~i);
73 __delay_cycles(12000*10);
74 }
75
76 for(i=0;i<NPOS;i++){
77 val=I2C_eeprom_read_byte(i);
78 printf("%02X %02X\n",(~i)&0xFF,val);
79 if(val!=(0xFF&(~i))){
80 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
81 exit(-1);
82 }
83 }
84
85 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDG);
86
87 /* Enter LPM0 forever*/
88 MAP_PCM_gotoLPM0();
89
90}
91
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd
new file mode 100644
index 0000000..41aad2d
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/msp432p401r.cmd
@@ -0,0 +1,104 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2016-01-26
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45#ifdef __TI_COMPILER_VERSION__
46#if __TI_COMPILER_VERSION__ >= 15009000
47 ALIAS
48 {
49 SRAM_CODE (RWX): origin = 0x01000000
50 SRAM_DATA (RW) : origin = 0x20000000
51 } length = 0x00010000
52#else
53 /* Hint: If the user wants to use ram functions, please observe that SRAM_CODE */
54 /* and SRAM_DATA memory areas are overlapping. You need to take measures to separate */
55 /* data from code in RAM. This is only valid for Compiler version earlier than 15.09.0.STS.*/
56 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
57 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
58#endif
59#endif
60}
61
62/* The following command line options are set as part of the CCS project. */
63/* If you are building using the command line, or for some reason want to */
64/* define them here, you can uncomment and modify these lines as needed. */
65/* If you are using CCS for building, it is probably better to make any such */
66/* modifications in your CCS project and leave this file alone. */
67/* */
68/* A heap size of 1024 bytes is recommended when you plan to use printf() */
69/* for debug output to the console window. */
70/* */
71/* --heap_size=1024 */
72/* --stack_size=512 */
73/* --library=rtsv7M4_T_le_eabi.lib */
74
75/* Section allocation in memory */
76
77SECTIONS
78{
79 .intvecs: > 0x00000000
80 .text : > MAIN
81 .const : > MAIN
82 .cinit : > MAIN
83 .pinit : > MAIN
84 .init_array : > MAIN
85 .binit : {} > MAIN
86
87 .flashMailbox : > 0x00200000
88
89 .vtable : > 0x20000000
90 .data : > SRAM_DATA
91 .bss : > SRAM_DATA
92 .sysmem : > SRAM_DATA
93 .stack : > SRAM_DATA (HIGH)
94
95#ifdef __TI_COMPILER_VERSION__
96#if __TI_COMPILER_VERSION__ >= 15009000
97 .TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT)
98#endif
99#endif
100}
101
102/* Symbolic definition of the WDTCTL register for RTS */
103WDTCTL_SYM = 0x4000480C;
104
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c
new file mode 100644
index 0000000..e8714ad
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/startup_msp432p401r_ccs.c
@@ -0,0 +1,219 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* MSP432P401R Interrupt Vector Table and startup code for CCS TI ARM
34*
35*****************************************************************************/
36
37#include <stdint.h>
38
39/* Forward declaration of the default fault handlers. */
40static void resetISR(void);
41static void nmiISR(void);
42static void faultISR(void);
43static void defaultISR(void);
44
45
46/* External declaration for the reset handler that is to be called when the */
47/* processor is started */
48extern void _c_int00(void);
49
50/* External declaration for system initialization function */
51extern void SystemInit(void);
52
53/* Linker variable that marks the top of the stack. */
54extern unsigned long __STACK_END;
55
56
57/* External declarations for the interrupt handlers used by the application. */
58/* To be added by user */
59
60
61/* Interrupt vector table. Note that the proper constructs must be placed on this to */
62/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
63/* the program if located at a start address other than 0. */
64#pragma RETAIN(interruptVectors)
65#pragma DATA_SECTION(interruptVectors, ".intvecs")
66void (* const interruptVectors[])(void) =
67{
68 (void (*)(void))((uint32_t)&__STACK_END),
69 /* The initial stack pointer */
70 resetISR, /* The reset handler */
71 nmiISR, /* The NMI handler */
72 faultISR, /* The hard fault handler */
73 defaultISR, /* The MPU fault handler */
74 defaultISR, /* The bus fault handler */
75 defaultISR, /* The usage fault handler */
76 0, /* Reserved */
77 0, /* Reserved */
78 0, /* Reserved */
79 0, /* Reserved */
80 defaultISR, /* SVCall handler */
81 defaultISR, /* Debug monitor handler */
82 0, /* Reserved */
83 defaultISR, /* The PendSV handler */
84 defaultISR, /* The SysTick handler */
85 defaultISR, /* PSS ISR */
86 defaultISR, /* CS ISR */
87 defaultISR, /* PCM ISR */
88 defaultISR, /* WDT ISR */
89 defaultISR, /* FPU ISR */
90 defaultISR, /* FLCTL ISR */
91 defaultISR, /* COMP0 ISR */
92 defaultISR, /* COMP1 ISR */
93 defaultISR, /* TA0_0 ISR */
94 defaultISR, /* TA0_N ISR */
95 defaultISR, /* TA1_0 ISR */
96 defaultISR, /* TA1_N ISR */
97 defaultISR, /* TA2_0 ISR */
98 defaultISR, /* TA2_N ISR */
99 defaultISR, /* TA3_0 ISR */
100 defaultISR, /* TA3_N ISR */
101 defaultISR, /* EUSCIA0 ISR */
102 defaultISR, /* EUSCIA1 ISR */
103 defaultISR, /* EUSCIA2 ISR */
104 defaultISR, /* EUSCIA3 ISR */
105 defaultISR, /* EUSCIB0 ISR */
106 defaultISR, /* EUSCIB1 ISR */
107 defaultISR, /* EUSCIB2 ISR */
108 defaultISR, /* EUSCIB3 ISR */
109 defaultISR, /* ADC14 ISR */
110 defaultISR, /* T32_INT1 ISR */
111 defaultISR, /* T32_INT2 ISR */
112 defaultISR, /* T32_INTC ISR */
113 defaultISR, /* AES ISR */
114 defaultISR, /* RTC ISR */
115 defaultISR, /* DMA_ERR ISR */
116 defaultISR, /* DMA_INT3 ISR */
117 defaultISR, /* DMA_INT2 ISR */
118 defaultISR, /* DMA_INT1 ISR */
119 defaultISR, /* DMA_INT0 ISR */
120 defaultISR, /* PORT1 ISR */
121 defaultISR, /* PORT2 ISR */
122 defaultISR, /* PORT3 ISR */
123 defaultISR, /* PORT4 ISR */
124 defaultISR, /* PORT5 ISR */
125 defaultISR, /* PORT6 ISR */
126 defaultISR, /* Reserved 41 */
127 defaultISR, /* Reserved 42 */
128 defaultISR, /* Reserved 43 */
129 defaultISR, /* Reserved 44 */
130 defaultISR, /* Reserved 45 */
131 defaultISR, /* Reserved 46 */
132 defaultISR, /* Reserved 47 */
133 defaultISR, /* Reserved 48 */
134 defaultISR, /* Reserved 49 */
135 defaultISR, /* Reserved 50 */
136 defaultISR, /* Reserved 51 */
137 defaultISR, /* Reserved 52 */
138 defaultISR, /* Reserved 53 */
139 defaultISR, /* Reserved 54 */
140 defaultISR, /* Reserved 55 */
141 defaultISR, /* Reserved 56 */
142 defaultISR, /* Reserved 57 */
143 defaultISR, /* Reserved 58 */
144 defaultISR, /* Reserved 59 */
145 defaultISR, /* Reserved 60 */
146 defaultISR, /* Reserved 61 */
147 defaultISR, /* Reserved 62 */
148 defaultISR /* Reserved 63 */
149};
150
151
152/* This is the code that gets called when the processor first starts execution */
153/* following a reset event. Only the absolutely necessary set is performed, */
154/* after which the application supplied entry() routine is called. Any fancy */
155/* actions (such as making decisions based on the reset cause register, and */
156/* resetting the bits in that register) are left solely in the hands of the */
157/* application. */
158void resetISR(void)
159{
160 SystemInit();
161
162 /* Jump to the CCS C Initialization Routine. */
163 __asm(" .global _c_int00\n"
164 " b.w _c_int00");
165}
166
167/* This is the code that gets called when the processor receives a NMI. This */
168/* simply enters an infinite loop, preserving the system state for examination */
169/* by a debugger. */
170static void nmiISR(void)
171{
172 /* Fault trap exempt from ULP advisor */
173 #pragma diag_push
174 #pragma CHECK_ULP("-2.1")
175
176 /* Enter an infinite loop. */
177 while(1)
178 {
179 }
180
181 #pragma diag_pop
182}
183
184
185/* This is the code that gets called when the processor receives a fault */
186/* interrupt. This simply enters an infinite loop, preserving the system state */
187/* for examination by a debugger. */
188static void faultISR(void)
189{
190 /* Fault trap exempt from ULP advisor */
191 #pragma diag_push
192 #pragma CHECK_ULP("-2.1")
193
194 /* Enter an infinite loop. */
195 while(1)
196 {
197 }
198
199 #pragma diag_pop
200}
201
202
203/* This is the code that gets called when the processor receives an unexpected */
204/* interrupt. This simply enters an infinite loop, preserving the system state */
205/* for examination by a debugger. */
206static void defaultISR(void)
207{
208 /* Fault trap exempt from ULP advisor */
209 #pragma diag_push
210 #pragma CHECK_ULP("-2.1")
211
212 /* Enter an infinite loop. */
213 while(1)
214 {
215 }
216
217 #pragma diag_pop
218}
219
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c
new file mode 100644
index 0000000..fb2b92e
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_I2C_M24xx256/system_msp432p401r.c
@@ -0,0 +1,399 @@
1/**************************************************************************//**
2* @file system_msp432p401r.c
3* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
4* MSP432P401R
5* @version V2.1.0
6* @date 2016-01-26
7*
8* @note View configuration instructions embedded in comments
9*
10******************************************************************************/
11//*****************************************************************************
12//
13// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions
17// are met:
18//
19// Redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer.
21//
22// Redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the
25// distribution.
26//
27// Neither the name of Texas Instruments Incorporated nor the names of
28// its contributors may be used to endorse or promote products derived
29// from this software without specific prior written permission.
30//
31// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42//
43//*****************************************************************************
44
45#include <stdint.h>
46#include "msp.h"
47
48/*--------------------- Configuration Instructions ----------------------------
49 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
50 #define __HALT_WDT 1
51 2. Insert your desired CPU frequency in Hz at:
52 #define __SYSTEM_CLOCK 12000000
53 3. If you prefer the DC-DC power regulator (more efficient at higher
54 frequencies), set the __REGULATOR to 1:
55 #define __REGULATOR 1
56 *---------------------------------------------------------------------------*/
57
58/*--------------------- Watchdog Timer Configuration ------------------------*/
59// Halt the Watchdog Timer
60// <0> Do not halt the WDT
61// <1> Halt the WDT
62#define __HALT_WDT 1
63
64/*--------------------- CPU Frequency Configuration -------------------------*/
65// CPU Frequency
66// <1500000> 1.5 MHz
67// <3000000> 3 MHz
68// <12000000> 12 MHz
69// <24000000> 24 MHz
70// <48000000> 48 MHz
71#define __SYSTEM_CLOCK 3000000
72
73/*--------------------- Power Regulator Configuration -----------------------*/
74// Power Regulator Mode
75// <0> LDO
76// <1> DC-DC
77#define __REGULATOR 0
78
79/*----------------------------------------------------------------------------
80 Define clocks, used for SystemCoreClockUpdate()
81 *---------------------------------------------------------------------------*/
82#define __VLOCLK 10000
83#define __MODCLK 24000000
84#define __LFXT 32768
85#define __HFXT 48000000
86
87/*----------------------------------------------------------------------------
88 Clock Variable definitions
89 *---------------------------------------------------------------------------*/
90uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
91
92/**
93 * Update SystemCoreClock variable
94 *
95 * @param none
96 * @return none
97 *
98 * @brief Updates the SystemCoreClock with current core Clock
99 * retrieved from cpu registers.
100 */
101void SystemCoreClockUpdate(void)
102{
103 uint32_t source, divider;
104 uint8_t dividerValue;
105
106 float dcoConst;
107 int32_t calVal;
108 uint32_t centeredFreq;
109 int16_t dcoTune;
110
111 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
112 dividerValue = 1 << divider;
113 source = CS->CTL1 & CS_CTL1_SELM_MASK;
114
115 switch(source)
116 {
117 case CS_CTL1_SELM__LFXTCLK:
118 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
119 {
120 // Clear interrupt flag
121 CS->KEY = CS_KEY_VAL;
122 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
123 CS->KEY = 1;
124
125 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
126 {
127 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
128 {
129 SystemCoreClock = (128000 / dividerValue);
130 }
131 else
132 {
133 SystemCoreClock = (32000 / dividerValue);
134 }
135 }
136 else
137 {
138 SystemCoreClock = __LFXT / dividerValue;
139 }
140 }
141 else
142 {
143 SystemCoreClock = __LFXT / dividerValue;
144 }
145 break;
146 case CS_CTL1_SELM__VLOCLK:
147 SystemCoreClock = __VLOCLK / dividerValue;
148 break;
149 case CS_CTL1_SELM__REFOCLK:
150 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
151 {
152 SystemCoreClock = (128000 / dividerValue);
153 }
154 else
155 {
156 SystemCoreClock = (32000 / dividerValue);
157 }
158 break;
159 case CS_CTL1_SELM__DCOCLK:
160 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
161
162 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
163 {
164 case CS_CTL0_DCORSEL_0:
165 centeredFreq = 1500000;
166 break;
167 case CS_CTL0_DCORSEL_1:
168 centeredFreq = 3000000;
169 break;
170 case CS_CTL0_DCORSEL_2:
171 centeredFreq = 6000000;
172 break;
173 case CS_CTL0_DCORSEL_3:
174 centeredFreq = 12000000;
175 break;
176 case CS_CTL0_DCORSEL_4:
177 centeredFreq = 24000000;
178 break;
179 case CS_CTL0_DCORSEL_5:
180 centeredFreq = 48000000;
181 break;
182 }
183
184 if(dcoTune == 0)
185 {
186 SystemCoreClock = centeredFreq;
187 }
188 else
189 {
190
191 if(dcoTune & 0x1000)
192 {
193 dcoTune = dcoTune | 0xF000;
194 }
195
196 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
197 {
198 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
199 calVal = TLV->DCOER_FCAL_RSEL04;
200 }
201 /* Internal Resistor */
202 else
203 {
204 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
205 calVal = TLV->DCOIR_FCAL_RSEL04;
206 }
207
208 SystemCoreClock = (uint32_t) ((centeredFreq)
209 / (1
210 - ((dcoConst * dcoTune)
211 / (8 * (1 + dcoConst * (768 - calVal))))));
212 }
213 break;
214 case CS_CTL1_SELM__MODOSC:
215 SystemCoreClock = __MODCLK / dividerValue;
216 break;
217 case CS_CTL1_SELM__HFXTCLK:
218 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
219 {
220 // Clear interrupt flag
221 CS->KEY = CS_KEY_VAL;
222 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
223 CS->KEY = 1;
224
225 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
226 {
227 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
228 {
229 SystemCoreClock = (128000 / dividerValue);
230 }
231 else
232 {
233 SystemCoreClock = (32000 / dividerValue);
234 }
235 }
236 else
237 {
238 SystemCoreClock = __HFXT / dividerValue;
239 }
240 }
241 else
242 {
243 SystemCoreClock = __HFXT / dividerValue;
244 }
245 break;
246 }
247}
248
249/**
250 * Initialize the system
251 *
252 * @param none
253 * @return none
254 *
255 * @brief Setup the microcontroller system.
256 *
257 * Performs the following initialization steps:
258 * 1. Enables the FPU
259 * 2. Halts the WDT if requested
260 * 3. Enables all SRAM banks
261 * 4. Sets up power regulator and VCORE
262 * 5. Enable Flash wait states if needed
263 * 6. Change MCLK to desired frequency
264 * 7. Enable Flash read buffering
265 */
266void SystemInit(void)
267{
268 // Enable FPU if used
269 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
270 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
271 (3UL << 11 * 2)); /* Set CP11 Full Access */
272 #endif
273
274 #if (__HALT_WDT == 1)
275 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
276 #endif
277
278 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
279
280 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
281 // Default VCORE is LDO VCORE0 so no change necessary
282
283 // Switches LDO VCORE0 to DCDC VCORE0 if requested
284 #if __REGULATOR
285 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
286 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
287 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
288 #endif
289
290 // No flash wait states necessary
291
292 // DCO = 1.5 MHz; MCLK = source
293 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
294 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
295 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
296 CS->KEY = 0;
297
298 // Set Flash Bank read buffering
299 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
300 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
301
302 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
303 // Default VCORE is LDO VCORE0 so no change necessary
304
305 // Switches LDO VCORE0 to DCDC VCORE0 if requested
306 #if __REGULATOR
307 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
308 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
309 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
310 #endif
311
312 // No flash wait states necessary
313
314 // DCO = 3 MHz; MCLK = source
315 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
316 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
317 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
318 CS->KEY = 0;
319
320 // Set Flash Bank read buffering
321 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
322 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
323
324 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
325 // Default VCORE is LDO VCORE0 so no change necessary
326
327 // Switches LDO VCORE0 to DCDC VCORE0 if requested
328 #if __REGULATOR
329 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
330 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
331 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
332 #endif
333
334 // No flash wait states necessary
335
336 // DCO = 12 MHz; MCLK = source
337 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
338 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
339 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
340 CS->KEY = 0;
341
342 // Set Flash Bank read buffering
343 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
344 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
345
346 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
347 // Default VCORE is LDO VCORE0 so no change necessary
348
349 // Switches LDO VCORE0 to DCDC VCORE0 if requested
350 #if __REGULATOR
351 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
352 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
353 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
354 #endif
355
356 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
357 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
358 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
359
360 // DCO = 24 MHz; MCLK = source
361 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
362 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
363 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
364 CS->KEY = 0;
365
366 // Set Flash Bank read buffering
367 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
368 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
369
370 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
371 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
372 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
373 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
374 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
375
376 // Switches LDO VCORE1 to DCDC VCORE1 if requested
377 #if __REGULATOR
378 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
379 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
380 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
381 #endif
382
383 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
384 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
385 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
386
387 // DCO = 48 MHz; MCLK = source
388 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
389 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
390 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
391 CS->KEY = 0;
392
393 // Set Flash Bank read buffering
394 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
395 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
396 #endif
397
398}
399