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authorBorja Martinez2016-09-10 13:41:15 -0500
committerBorja Martinez2016-09-10 13:41:15 -0500
commite310e04250e6d3b0846dd3839d0113ce09d8cb9d (patch)
tree36f2a2c6a45fb14f5d118d2ccd9653fff1c064c2
parent7060e2a663c295f000cb3bec9ee0a03062a908df (diff)
downloadi3-mote-e310e04250e6d3b0846dd3839d0113ce09d8cb9d.tar.gz
i3-mote-e310e04250e6d3b0846dd3839d0113ce09d8cb9d.tar.xz
i3-mote-e310e04250e6d3b0846dd3839d0113ce09d8cb9d.zip
Created Test MSP432 3wSPI M25P40
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h33
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c191
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd84
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c189
-rw-r--r--Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c435
5 files changed, 932 insertions, 0 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h
new file mode 100644
index 0000000..31196c6
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/i3mote.h
@@ -0,0 +1,33 @@
1/* Rev.B */
2#define HID_PORT GPIO_PORT_P6
3#define LEDR GPIO_PIN2
4#define LEDG GPIO_PIN3
5#define BUTTON GPIO_PIN1
6
7
8/* Rev.A
9#define LED_PORT GPIO_PORT_P8
10#define LEDR GPIO_PIN5
11#define LEDG GPIO_PIN6
12#define BUTTON GPIO_PIN7
13*/
14
15
16/* On Board EEPROM 25xx256*/
17#define EEPROM_SLAVE_ADDRESS 0x50
18
19
20/* Debg UART */
21#define UART_BAUD_115200
22#define UART_PORT GPIO_PORT_P1
23#define UART_TX_PIN GPIO_PIN3
24#define UART_RX_PIN GPIO_PIN2
25
26/* Flash SPI */
27#define FLASH_SPI_PORT GPIO_PORT_P3
28#define FLASH_SPI_NCS_PIN GPIO_PIN0
29#define FLASH_SPI_CLK_PIN GPIO_PIN1
30#define FLASH_SPI_MISO_PIN GPIO_PIN2
31#define FLASH_SPI_MOSI_PIN GPIO_PIN3
32
33
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c
new file mode 100644
index 0000000..0743654
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/main.c
@@ -0,0 +1,191 @@
1/******************************************************************************
2 * MSP432 SPI - 3-wire Master Interface to On board M24P40
3 *
4 *
5 * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 12MHz
6 *
7 * Use with SPI Slave Data Echo code example.
8 *
9 * MSP432P401
10 * -----------------
11 * | |
12 * | |
13 * | |
14 * | P1.6|-> Data Out (UCB0SIMO)
15 * | |
16 * | P1.7|<- Data In (UCB0SOMI)
17 * | |
18 * | P1.5|-> Serial Clock Out (UCB0CLK)
19 * Author: B.Martinez
20*******************************************************************************/
21#include "i3mote.h"
22
23
24/* DriverLib Includes */
25#include "driverlib.h"
26
27/* Standard Includes */
28#include <stdint.h>
29#include <stdlib.h>
30
31#include <stdbool.h>
32
33#include <stdio.h>
34
35/* Statics */
36static volatile uint8_t RXData = 0;
37static volatile uint8_t RXDataCnt = 0;
38static uint8_t TXData = 0;
39
40#define SYSFREQ 12000000
41
42/* SPI Master Configuration Parameter */
43const eUSCI_SPI_MasterConfig spiMasterConfig =
44{
45 EUSCI_A_SPI_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
46 SYSFREQ, // SMCLK = DCO = 12MHZ
47 50000, // SPICLK = 50khz
48 EUSCI_A_SPI_MSB_FIRST, // MSB First
49 EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase (Default)
50 EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // High polarity
51 EUSCI_A_SPI_3PIN
52};
53
54
55int main(void)
56{
57 volatile uint32_t ii;
58
59 /* Halting WDT */
60 WDT_A_holdTimer();
61
62 /* Initializes Clock System */
63 MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
64 MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
65 MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
66 MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 );
67 MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
68
69
70 /* LEDS as output */
71 MAP_GPIO_setAsOutputPin(HID_PORT,LEDR|LEDG);
72 MAP_GPIO_setOutputLowOnPin(HID_PORT,LEDR|LEDG);
73
74
75 /* CS Configuring P3.0 as output */
76 MAP_GPIO_setAsOutputPin(FLASH_SPI_PORT, FLASH_SPI_NCS_PIN);
77 MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_NCS_PIN);
78
79 /* SPI */
80 GPIO_setAsPeripheralModuleFunctionInputPin(FLASH_SPI_PORT,
81 FLASH_SPI_CLK_PIN | FLASH_SPI_MISO_PIN | FLASH_SPI_MOSI_PIN, GPIO_PRIMARY_MODULE_FUNCTION);
82
83
84 /* Configuring SPI in 3wire master mode */
85 SPI_initMaster(EUSCI_A2_BASE, &spiMasterConfig);
86
87 /* Enable SPI module */
88 SPI_enableModule(EUSCI_A2_BASE);
89
90 /* Enabling interrupts */
91 SPI_enableInterrupt(EUSCI_A2_BASE, EUSCI_A_SPI_RECEIVE_INTERRUPT);
92 Interrupt_enableInterrupt(INT_EUSCIA2);
93 Interrupt_enableSleepOnIsrExit();
94
95 /* Polling to see if the TX buffer is ready */
96 while (!(SPI_getInterruptStatus(EUSCI_A2_BASE,EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
97
98 // CS
99 MAP_GPIO_setOutputLowOnPin(FLASH_SPI_PORT,FLASH_SPI_NCS_PIN);
100
101 /* Transmitting first command to slave */
102 TXData=0x9E;
103 SPI_transmitData(EUSCI_A2_BASE, TXData);
104
105 //P6OUT |= BIT0;
106 //MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P6, LEDG);
107 /* Enabling MASTER interrupts */
108 // MAP_Interrupt_enableMaster();
109
110 while(1)
111 {
112 MAP_PCM_gotoLPM0();
113 }
114
115}
116
117//******************************************************************************
118//
119//This is the EUSCI_A2 interrupt vector service routine.
120//
121//******************************************************************************
122void EUSCIA2_IRQHandler(void)
123{
124 uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_A2_BASE);
125 uint32_t jj;
126
127 SPI_clearInterruptFlag(EUSCI_A2_BASE, status);
128
129 if(status & EUSCI_A_SPI_RECEIVE_INTERRUPT)
130 {
131
132 /* USCI_B0 TX buffer ready? */
133 while (!(SPI_getInterruptStatus(EUSCI_A2_BASE, EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
134
135 RXData = SPI_receiveData(EUSCI_A2_BASE);
136 printf("%i %02X\n",RXDataCnt,RXData);
137
138 switch(RXDataCnt){
139 case 1:
140 if(RXData!=0x20){
141 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
142 exit(-1);
143 }
144 break;
145 case 2:
146 if(RXData!=0x71){
147 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
148 exit(-1);
149 }
150 break;
151 case 3:
152 if(RXData!=0x15){
153 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
154 exit(-1);
155 }
156 break;
157 case 4:
158 if(RXData!=0x10){
159 MAP_GPIO_setOutputHighOnPin(HID_PORT,LEDR);
160 exit(-1);
161 }
162 break;
163 }
164
165 RXDataCnt++;
166
167 if(RXDataCnt==5){
168
169 MAP_GPIO_setOutputHighOnPin(FLASH_SPI_PORT, FLASH_SPI_NCS_PIN);
170
171 /* Enable SysTick and Blink Forever */
172 MAP_SysTick_enableModule();
173 MAP_SysTick_setPeriod(SYSFREQ/4);
174 MAP_Interrupt_enableSleepOnIsrExit();
175 MAP_SysTick_enableInterrupt();
176
177 }
178 else{
179 /* Send the next data packet */
180 SPI_transmitData(EUSCI_A2_BASE, ++TXData);
181 }
182
183 /* Delay between transmissions for slave to process information */
184 for(jj=50;jj<50;jj++);
185 }
186}
187
188void SysTick_Handler(void)
189{
190 MAP_GPIO_toggleOutputOnPin(HID_PORT,LEDG);
191}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd
new file mode 100644
index 0000000..346c191
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/msp432p401r.cmd
@@ -0,0 +1,84 @@
1/******************************************************************************
2*
3* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions
7* are met:
8*
9* Redistributions of source code must retain the above copyright
10* notice, this list of conditions and the following disclaimer.
11*
12* Redistributions in binary form must reproduce the above copyright
13* notice, this list of conditions and the following disclaimer in the
14* documentation and/or other materials provided with the
15* distribution.
16*
17* Neither the name of Texas Instruments Incorporated nor the names of
18* its contributors may be used to endorse or promote products derived
19* from this software without specific prior written permission.
20*
21* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*
33* Default linker command file for Texas Instruments MSP432P401R
34*
35* File creation date: 2015-09-03
36*
37*****************************************************************************/
38
39--retain=flashMailbox
40
41MEMORY
42{
43 MAIN (RX) : origin = 0x00000000, length = 0x00040000
44 INFO (RX) : origin = 0x00200000, length = 0x00004000
45 SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
46 SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
47}
48
49/* The following command line options are set as part of the CCS project. */
50/* If you are building using the command line, or for some reason want to */
51/* define them here, you can uncomment and modify these lines as needed. */
52/* If you are using CCS for building, it is probably better to make any such */
53/* modifications in your CCS project and leave this file alone. */
54/* */
55/* A heap size of 1024 bytes is recommended when you plan to use printf() */
56/* for debug output to the console window. */
57/* */
58/* --heap_size=1024 */
59/* --stack_size=512 */
60/* --library=rtsv7M4_T_le_eabi.lib */
61
62/* Section allocation in memory */
63
64SECTIONS
65{
66 .intvecs: > 0x00000000
67 .text : > MAIN
68 .const : > MAIN
69 .cinit : > MAIN
70 .pinit : > MAIN
71 .init_array : > MAIN
72
73 .flashMailbox : > 0x00200000
74
75 .vtable : > 0x20000000
76 .data : > SRAM_DATA
77 .bss : > SRAM_DATA
78 .sysmem : > SRAM_DATA
79 .stack : > SRAM_DATA (HIGH)
80}
81
82/* Symbolic definition of the WDTCTL register for RTS */
83WDTCTL_SYM = 0x4000480C;
84
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c
new file mode 100644
index 0000000..c168bfa
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/startup_msp432p401r_ccs.c
@@ -0,0 +1,189 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5*/
6
7#include <stdint.h>
8
9/* Forward declaration of the default fault handlers. */
10static void resetISR(void);
11static void nmiISR(void);
12static void faultISR(void);
13static void defaultISR(void);
14
15
16/* External declaration for the reset handler that is to be called when the */
17/* processor is started */
18extern void _c_int00(void);
19
20/* External declaration for system initialization function */
21extern void SystemInit(void);
22
23/* Linker variable that marks the top of the stack. */
24extern unsigned long __STACK_END;
25
26
27/* External declarations for the interrupt handlers used by the application. */
28// extern void EUSCIB0_IRQHandler (void);
29extern void EUSCIA2_IRQHandler (void);
30extern void SysTick_Handler(void);
31
32/* Interrupt vector table. Note that the proper constructs must be placed on this to */
33/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
34/* the program if located at a start address other than 0. */
35#pragma RETAIN(interruptVectors)
36#pragma DATA_SECTION(interruptVectors, ".intvecs")
37void (* const interruptVectors[])(void) =
38{
39 (void (*)(void))((uint32_t)&__STACK_END),
40 /* The initial stack pointer */
41 resetISR, /* The reset handler */
42 nmiISR, /* The NMI handler */
43 faultISR, /* The hard fault handler */
44 defaultISR, /* The MPU fault handler */
45 defaultISR, /* The bus fault handler */
46 defaultISR, /* The usage fault handler */
47 0, /* Reserved */
48 0, /* Reserved */
49 0, /* Reserved */
50 0, /* Reserved */
51 defaultISR, /* SVCall handler */
52 defaultISR, /* Debug monitor handler */
53 0, /* Reserved */
54 defaultISR, /* The PendSV handler */
55 SysTick_Handler, /* The SysTick handler */
56 defaultISR, /* PSS ISR */
57 defaultISR, /* CS ISR */
58 defaultISR, /* PCM ISR */
59 defaultISR, /* WDT ISR */
60 defaultISR, /* FPU ISR */
61 defaultISR, /* FLCTL ISR */
62 defaultISR, /* COMP0 ISR */
63 defaultISR, /* COMP1 ISR */
64 defaultISR, /* TA0_0 ISR */
65 defaultISR, /* TA0_N ISR */
66 defaultISR, /* TA1_0 ISR */
67 defaultISR, /* TA1_N ISR */
68 defaultISR, /* TA2_0 ISR */
69 defaultISR, /* TA2_N ISR */
70 defaultISR, /* TA3_0 ISR */
71 defaultISR, /* TA3_N ISR */
72 defaultISR, /* EUSCIA0 ISR */
73 defaultISR, /* EUSCIA1 ISR */
74 EUSCIA2_IRQHandler, /* EUSCIA2 ISR */
75 defaultISR, /* EUSCIA3 ISR */
76 defaultISR, /* EUSCIB0 ISR */
77 defaultISR, /* EUSCIB1 ISR */
78 defaultISR, /* EUSCIB2 ISR */
79 defaultISR, /* EUSCIB3 ISR */
80 defaultISR, /* ADC14 ISR */
81 defaultISR, /* T32_INT1 ISR */
82 defaultISR, /* T32_INT2 ISR */
83 defaultISR, /* T32_INTC ISR */
84 defaultISR, /* AES ISR */
85 defaultISR, /* RTC ISR */
86 defaultISR, /* DMA_ERR ISR */
87 defaultISR, /* DMA_INT3 ISR */
88 defaultISR, /* DMA_INT2 ISR */
89 defaultISR, /* DMA_INT1 ISR */
90 defaultISR, /* DMA_INT0 ISR */
91 defaultISR, /* PORT1 ISR */
92 defaultISR, /* PORT2 ISR */
93 defaultISR, /* PORT3 ISR */
94 defaultISR, /* PORT4 ISR */
95 defaultISR, /* PORT5 ISR */
96 defaultISR, /* PORT6 ISR */
97 defaultISR, /* Reserved 41 */
98 defaultISR, /* Reserved 42 */
99 defaultISR, /* Reserved 43 */
100 defaultISR, /* Reserved 44 */
101 defaultISR, /* Reserved 45 */
102 defaultISR, /* Reserved 46 */
103 defaultISR, /* Reserved 47 */
104 defaultISR, /* Reserved 48 */
105 defaultISR, /* Reserved 49 */
106 defaultISR, /* Reserved 50 */
107 defaultISR, /* Reserved 51 */
108 defaultISR, /* Reserved 52 */
109 defaultISR, /* Reserved 53 */
110 defaultISR, /* Reserved 54 */
111 defaultISR, /* Reserved 55 */
112 defaultISR, /* Reserved 56 */
113 defaultISR, /* Reserved 57 */
114 defaultISR, /* Reserved 58 */
115 defaultISR, /* Reserved 59 */
116 defaultISR, /* Reserved 60 */
117 defaultISR, /* Reserved 61 */
118 defaultISR, /* Reserved 62 */
119 defaultISR /* Reserved 63 */
120};
121
122
123/* This is the code that gets called when the processor first starts execution */
124/* following a reset event. Only the absolutely necessary set is performed, */
125/* after which the application supplied entry() routine is called. Any fancy */
126/* actions (such as making decisions based on the reset cause register, and */
127/* resetting the bits in that register) are left solely in the hands of the */
128/* application. */
129void resetISR(void)
130{
131 SystemInit();
132
133 /* Jump to the CCS C Initialization Routine. */
134 __asm(" .global _c_int00\n"
135 " b.w _c_int00");
136}
137
138/* This is the code that gets called when the processor receives a NMI. This */
139/* simply enters an infinite loop, preserving the system state for examination */
140/* by a debugger. */
141static void nmiISR(void)
142{
143 /* Fault trap exempt from ULP advisor */
144 #pragma diag_push
145 #pragma CHECK_ULP("-2.1")
146
147 /* Enter an infinite loop. */
148 while(1)
149 {
150 }
151
152 #pragma diag_pop
153}
154
155
156/* This is the code that gets called when the processor receives a fault */
157/* interrupt. This simply enters an infinite loop, preserving the system state */
158/* for examination by a debugger. */
159static void faultISR(void)
160{
161 /* Fault trap exempt from ULP advisor */
162 #pragma diag_push
163 #pragma CHECK_ULP("-2.1")
164
165 /* Enter an infinite loop. */
166 while(1)
167 {
168 }
169
170 #pragma diag_pop
171}
172
173
174/* This is the code that gets called when the processor receives an unexpected */
175/* interrupt. This simply enters an infinite loop, preserving the system state */
176/* for examination by a debugger. */
177static void defaultISR(void)
178{
179 /* Fault trap exempt from ULP advisor */
180 #pragma diag_push
181 #pragma CHECK_ULP("-2.1")
182
183 /* Enter an infinite loop. */
184 while(1)
185 {
186 }
187
188 #pragma diag_pop
189}
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c
new file mode 100644
index 0000000..93b5a72
--- /dev/null
+++ b/Basic-Test-Package/MSP432/Test_MSP432_3wSPI_M25P40/system_msp432p401r.c
@@ -0,0 +1,435 @@
1/*
2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
5 *
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * --/COPYRIGHT--*/
37/**************************************************************************//**
38* @file system_msp432p401r.c
39* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
40* MSP432P401R
41* @version V1.00
42* @date 20-Oct-2015
43*
44* @note View configuration instructions embedded in comments
45*
46******************************************************************************/
47//*****************************************************************************
48//
49// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
50//
51// Redistribution and use in source and binary forms, with or without
52// modification, are permitted provided that the following conditions
53// are met:
54//
55// Redistributions of source code must retain the above copyright
56// notice, this list of conditions and the following disclaimer.
57//
58// Redistributions in binary form must reproduce the above copyright
59// notice, this list of conditions and the following disclaimer in the
60// documentation and/or other materials provided with the
61// distribution.
62//
63// Neither the name of Texas Instruments Incorporated nor the names of
64// its contributors may be used to endorse or promote products derived
65// from this software without specific prior written permission.
66//
67// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
68// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
69// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
70// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
71// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
72// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
73// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
74// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
75// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78//
79//*****************************************************************************
80
81#include <stdint.h>
82
83#include "msp.h"
84
85/*--------------------- Configuration Instructions ----------------------------
86 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
87 #define __HALT_WDT 1
88 2. Insert your desired CPU frequency in Hz at:
89 #define __SYSTEM_CLOCK 3000000
90 3. If you prefer the DC-DC power regulator (more efficient at higher
91 frequencies), set the __REGULATOR to 1:
92 #define __REGULATOR 1
93 *---------------------------------------------------------------------------*/
94
95/*--------------------- Watchdog Timer Configuration ------------------------*/
96// Halt the Watchdog Timer
97// <0> Do not halt the WDT
98// <1> Halt the WDT
99#define __HALT_WDT 1
100
101/*--------------------- CPU Frequency Configuration -------------------------*/
102// CPU Frequency
103// <1500000> 1.5 MHz
104// <3000000> 3 MHz
105// <12000000> 12 MHz
106// <24000000> 24 MHz
107// <48000000> 48 MHz
108#define __SYSTEM_CLOCK 1500000
109
110/*--------------------- Power Regulator Configuration -----------------------*/
111// Power Regulator Mode
112// <0> LDO
113// <1> DC-DC
114#define __REGULATOR 1
115
116/*----------------------------------------------------------------------------
117 Define clocks, used for SystemCoreClockUpdate()
118 *---------------------------------------------------------------------------*/
119#define __VLOCLK 10000
120#define __MODCLK 24000000
121#define __LFXT 32768
122#define __HFXT 48000000
123
124/*----------------------------------------------------------------------------
125 Clock Variable definitions
126 *---------------------------------------------------------------------------*/
127uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
128
129/**
130 * Update SystemCoreClock variable
131 *
132 * @param none
133 * @return none
134 *
135 * @brief Updates the SystemCoreClock with current core Clock
136 * retrieved from cpu registers.
137 */
138void SystemCoreClockUpdate(void)
139{
140 uint32_t source, divider;
141 uint8_t dividerValue;
142
143 float dcoConst;
144 int32_t calVal;
145 uint32_t centeredFreq;
146 int16_t dcoTune;
147
148 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
149 dividerValue = 1 << divider;
150 source = CS->CTL1 & CS_CTL1_SELM_MASK;
151
152 switch(source)
153 {
154 case CS_CTL1_SELM__LFXTCLK:
155 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
156 {
157 // Clear interrupt flag
158 CS->KEY = CS_KEY_VAL;
159 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
160 CS->KEY = 1;
161
162 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
163 {
164 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
165 {
166 SystemCoreClock = (128000 / dividerValue);
167 }
168 else
169 {
170 SystemCoreClock = (32000 / dividerValue);
171 }
172 }
173 else
174 {
175 SystemCoreClock = __LFXT / dividerValue;
176 }
177 }
178 else
179 {
180 SystemCoreClock = __LFXT / dividerValue;
181 }
182 break;
183 case CS_CTL1_SELM__VLOCLK:
184 SystemCoreClock = __VLOCLK / dividerValue;
185 break;
186 case CS_CTL1_SELM__REFOCLK:
187 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
188 {
189 SystemCoreClock = (128000 / dividerValue);
190 }
191 else
192 {
193 SystemCoreClock = (32000 / dividerValue);
194 }
195 break;
196 case CS_CTL1_SELM__DCOCLK:
197 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
198
199 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
200 {
201 case CS_CTL0_DCORSEL_0:
202 centeredFreq = 1500000;
203 break;
204 case CS_CTL0_DCORSEL_1:
205 centeredFreq = 3000000;
206 break;
207 case CS_CTL0_DCORSEL_2:
208 centeredFreq = 6000000;
209 break;
210 case CS_CTL0_DCORSEL_3:
211 centeredFreq = 12000000;
212 break;
213 case CS_CTL0_DCORSEL_4:
214 centeredFreq = 24000000;
215 break;
216 case CS_CTL0_DCORSEL_5:
217 centeredFreq = 48000000;
218 break;
219 }
220
221 if(dcoTune == 0)
222 {
223 SystemCoreClock = centeredFreq;
224 }
225 else
226 {
227
228 if(dcoTune & 0x1000)
229 {
230 dcoTune = dcoTune | 0xF000;
231 }
232
233 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
234 {
235 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
236 calVal = TLV->DCOER_FCAL_RSEL04;
237 }
238 /* Internal Resistor */
239 else
240 {
241 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
242 calVal = TLV->DCOIR_FCAL_RSEL04;
243 }
244
245 SystemCoreClock = (uint32_t) ((centeredFreq)
246 / (1
247 - ((dcoConst * dcoTune)
248 / (8 * (1 + dcoConst * (768 - calVal))))));
249 }
250 break;
251 case CS_CTL1_SELM__MODOSC:
252 SystemCoreClock = __MODCLK / dividerValue;
253 break;
254 case CS_CTL1_SELM__HFXTCLK:
255 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
256 {
257 // Clear interrupt flag
258 CS->KEY = CS_KEY_VAL;
259 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
260 CS->KEY = 1;
261
262 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
263 {
264 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
265 {
266 SystemCoreClock = (128000 / dividerValue);
267 }
268 else
269 {
270 SystemCoreClock = (32000 / dividerValue);
271 }
272 }
273 else
274 {
275 SystemCoreClock = __HFXT / dividerValue;
276 }
277 }
278 else
279 {
280 SystemCoreClock = __HFXT / dividerValue;
281 }
282 break;
283 }
284}
285
286/**
287 * Initialize the system
288 *
289 * @param none
290 * @return none
291 *
292 * @brief Setup the microcontroller system.
293 *
294 * Performs the following initialization steps:
295 * 1. Enables the FPU
296 * 2. Halts the WDT if requested
297 * 3. Enables all SRAM banks
298 * 4. Sets up power regulator and VCORE
299 * 5. Enable Flash wait states if needed
300 * 6. Change MCLK to desired frequency
301 * 7. Enable Flash read buffering
302 */
303void SystemInit(void)
304{
305 // Enable FPU if used
306 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
307 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
308 (3UL << 11 * 2)); /* Set CP11 Full Access */
309 #endif
310
311 #if (__HALT_WDT == 1)
312 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
313 #endif
314
315 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
316
317 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
318 // Default VCORE is LDO VCORE0 so no change necessary
319
320 // Switches LDO VCORE0 to DCDC VCORE0 if requested
321 #if __REGULATOR
322 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
323 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
324 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
325 #endif
326
327 // No flash wait states necessary
328
329 // DCO = 1.5 MHz; MCLK = source
330 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
331 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
332 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
333 CS->KEY = 0;
334
335 // Set Flash Bank read buffering
336 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
337 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
338
339 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
340 // Default VCORE is LDO VCORE0 so no change necessary
341
342 // Switches LDO VCORE0 to DCDC VCORE0 if requested
343 #if __REGULATOR
344 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
345 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
346 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
347 #endif
348
349 // No flash wait states necessary
350
351 // DCO = 3 MHz; MCLK = source
352 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
353 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
354 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
355 CS->KEY = 0;
356
357 // Set Flash Bank read buffering
358 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
359 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
360
361 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
362 // Default VCORE is LDO VCORE0 so no change necessary
363
364 // Switches LDO VCORE0 to DCDC VCORE0 if requested
365 #if __REGULATOR
366 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
367 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
368 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
369 #endif
370
371 // No flash wait states necessary
372
373 // DCO = 12 MHz; MCLK = source
374 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
375 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
376 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
377 CS->KEY = 0;
378
379 // Set Flash Bank read buffering
380 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
381 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
382
383 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
384 // Default VCORE is LDO VCORE0 so no change necessary
385
386 // Switches LDO VCORE0 to DCDC VCORE0 if requested
387 #if __REGULATOR
388 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
389 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
390 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
391 #endif
392
393 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
394 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
395 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
396
397 // DCO = 24 MHz; MCLK = source
398 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
399 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
400 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
401 CS->KEY = 0;
402
403 // Set Flash Bank read buffering
404 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
405 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
406
407 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
408 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
409 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
410 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
411 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
412
413 // Switches LDO VCORE1 to DCDC VCORE1 if requested
414 #if __REGULATOR
415 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
416 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
417 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
418 #endif
419
420 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
421 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
422 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
423
424 // DCO = 48 MHz; MCLK = source
425 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
426 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
427 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
428 CS->KEY = 0;
429
430 // Set Flash Bank read buffering
431 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
432 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
433 #endif
434
435}