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Diffstat (limited to 'Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c')
-rw-r--r-- | Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c | 255 |
1 files changed, 255 insertions, 0 deletions
diff --git a/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c new file mode 100644 index 0000000..e7fcb9f --- /dev/null +++ b/Basic-Test-Package/MSP432/Test_MSP432_DebugUART_EchoPC/startup_msp432p401r_ccs.c | |||
@@ -0,0 +1,255 @@ | |||
1 | /* | ||
2 | * ------------------------------------------- | ||
3 | * MSP432 DriverLib - v3_10_00_09 | ||
4 | * ------------------------------------------- | ||
5 | * | ||
6 | * --COPYRIGHT--,BSD,BSD | ||
7 | * Copyright (c) 2014, Texas Instruments Incorporated | ||
8 | * All rights reserved. | ||
9 | * | ||
10 | * Redistribution and use in source and binary forms, with or without | ||
11 | * modification, are permitted provided that the following conditions | ||
12 | * are met: | ||
13 | * | ||
14 | * * Redistributions of source code must retain the above copyright | ||
15 | * notice, this list of conditions and the following disclaimer. | ||
16 | * | ||
17 | * * Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in the | ||
19 | * documentation and/or other materials provided with the distribution. | ||
20 | * | ||
21 | * * Neither the name of Texas Instruments Incorporated nor the names of | ||
22 | * its contributors may be used to endorse or promote products derived | ||
23 | * from this software without specific prior written permission. | ||
24 | * | ||
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | ||
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | ||
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | ||
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; | ||
32 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
33 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR | ||
34 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, | ||
35 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
36 | * --/COPYRIGHT--*/ | ||
37 | //***************************************************************************** | ||
38 | // | ||
39 | // Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ | ||
40 | // | ||
41 | // Redistribution and use in source and binary forms, with or without | ||
42 | // modification, are permitted provided that the following conditions | ||
43 | // are met: | ||
44 | // | ||
45 | // Redistributions of source code must retain the above copyright | ||
46 | // notice, this list of conditions and the following disclaimer. | ||
47 | // | ||
48 | // Redistributions in binary form must reproduce the above copyright | ||
49 | // notice, this list of conditions and the following disclaimer in the | ||
50 | // documentation and/or other materials provided with the | ||
51 | // distribution. | ||
52 | // | ||
53 | // Neither the name of Texas Instruments Incorporated nor the names of | ||
54 | // its contributors may be used to endorse or promote products derived | ||
55 | // from this software without specific prior written permission. | ||
56 | // | ||
57 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
58 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
59 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
60 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
61 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
62 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
63 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
64 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
65 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
66 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
67 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
68 | // | ||
69 | // MSP432 Family Interrupt Vector Table for CGT | ||
70 | // | ||
71 | //**************************************************************************** | ||
72 | |||
73 | #include <stdint.h> | ||
74 | |||
75 | /* Forward declaration of the default fault handlers. */ | ||
76 | static void resetISR(void); | ||
77 | static void nmiISR(void); | ||
78 | static void faultISR(void); | ||
79 | static void defaultISR(void); | ||
80 | |||
81 | |||
82 | /* External declaration for the reset handler that is to be called when the */ | ||
83 | /* processor is started */ | ||
84 | extern void _c_int00(void); | ||
85 | |||
86 | /* External declaration for system initialization function */ | ||
87 | extern void SystemInit(void); | ||
88 | |||
89 | /* Linker variable that marks the top of the stack. */ | ||
90 | extern unsigned long __STACK_END; | ||
91 | |||
92 | |||
93 | /* External declarations for the interrupt handlers used by the application. */ | ||
94 | extern void EUSCIA0_IRQHandler (void); | ||
95 | extern void SysTick_Handler(void); | ||
96 | |||
97 | |||
98 | /* Interrupt vector table. Note that the proper constructs must be placed on this to */ | ||
99 | /* ensure that it ends up at physical address 0x0000.0000 or at the start of */ | ||
100 | /* the program if located at a start address other than 0. */ | ||
101 | #pragma RETAIN(interruptVectors) | ||
102 | #pragma DATA_SECTION(interruptVectors, ".intvecs") | ||
103 | void (* const interruptVectors[])(void) = | ||
104 | { | ||
105 | (void (*)(void))((uint32_t)&__STACK_END), | ||
106 | /* The initial stack pointer */ | ||
107 | resetISR, /* The reset handler */ | ||
108 | nmiISR, /* The NMI handler */ | ||
109 | faultISR, /* The hard fault handler */ | ||
110 | defaultISR, /* The MPU fault handler */ | ||
111 | defaultISR, /* The bus fault handler */ | ||
112 | defaultISR, /* The usage fault handler */ | ||
113 | 0, /* Reserved */ | ||
114 | 0, /* Reserved */ | ||
115 | 0, /* Reserved */ | ||
116 | 0, /* Reserved */ | ||
117 | defaultISR, /* SVCall handler */ | ||
118 | defaultISR, /* Debug monitor handler */ | ||
119 | 0, /* Reserved */ | ||
120 | defaultISR, /* The PendSV handler */ | ||
121 | SysTick_Handler, /* The SysTick handler */ | ||
122 | defaultISR, /* PSS ISR */ | ||
123 | defaultISR, /* CS ISR */ | ||
124 | defaultISR, /* PCM ISR */ | ||
125 | defaultISR, /* WDT ISR */ | ||
126 | defaultISR, /* FPU ISR */ | ||
127 | defaultISR, /* FLCTL ISR */ | ||
128 | defaultISR, /* COMP0 ISR */ | ||
129 | defaultISR, /* COMP1 ISR */ | ||
130 | defaultISR, /* TA0_0 ISR */ | ||
131 | defaultISR, /* TA0_N ISR */ | ||
132 | defaultISR, /* TA1_0 ISR */ | ||
133 | defaultISR, /* TA1_N ISR */ | ||
134 | defaultISR, /* TA2_0 ISR */ | ||
135 | defaultISR, /* TA2_N ISR */ | ||
136 | defaultISR, /* TA3_0 ISR */ | ||
137 | defaultISR, /* TA3_N ISR */ | ||
138 | EUSCIA0_IRQHandler, /* EUSCIA0 ISR */ | ||
139 | defaultISR, /* EUSCIA1 ISR */ | ||
140 | defaultISR, /* EUSCIA2 ISR */ | ||
141 | defaultISR, /* EUSCIA3 ISR */ | ||
142 | defaultISR, /* EUSCIB0 ISR */ | ||
143 | defaultISR, /* EUSCIB1 ISR */ | ||
144 | defaultISR, /* EUSCIB2 ISR */ | ||
145 | defaultISR, /* EUSCIB3 ISR */ | ||
146 | defaultISR, /* ADC14 ISR */ | ||
147 | defaultISR, /* T32_INT1 ISR */ | ||
148 | defaultISR, /* T32_INT2 ISR */ | ||
149 | defaultISR, /* T32_INTC ISR */ | ||
150 | defaultISR, /* AES ISR */ | ||
151 | defaultISR, /* RTC ISR */ | ||
152 | defaultISR, /* DMA_ERR ISR */ | ||
153 | defaultISR, /* DMA_INT3 ISR */ | ||
154 | defaultISR, /* DMA_INT2 ISR */ | ||
155 | defaultISR, /* DMA_INT1 ISR */ | ||
156 | defaultISR, /* DMA_INT0 ISR */ | ||
157 | defaultISR, /* PORT1 ISR */ | ||
158 | defaultISR, /* PORT2 ISR */ | ||
159 | defaultISR, /* PORT3 ISR */ | ||
160 | defaultISR, /* PORT4 ISR */ | ||
161 | defaultISR, /* PORT5 ISR */ | ||
162 | defaultISR, /* PORT6 ISR */ | ||
163 | defaultISR, /* Reserved 41 */ | ||
164 | defaultISR, /* Reserved 42 */ | ||
165 | defaultISR, /* Reserved 43 */ | ||
166 | defaultISR, /* Reserved 44 */ | ||
167 | defaultISR, /* Reserved 45 */ | ||
168 | defaultISR, /* Reserved 46 */ | ||
169 | defaultISR, /* Reserved 47 */ | ||
170 | defaultISR, /* Reserved 48 */ | ||
171 | defaultISR, /* Reserved 49 */ | ||
172 | defaultISR, /* Reserved 50 */ | ||
173 | defaultISR, /* Reserved 51 */ | ||
174 | defaultISR, /* Reserved 52 */ | ||
175 | defaultISR, /* Reserved 53 */ | ||
176 | defaultISR, /* Reserved 54 */ | ||
177 | defaultISR, /* Reserved 55 */ | ||
178 | defaultISR, /* Reserved 56 */ | ||
179 | defaultISR, /* Reserved 57 */ | ||
180 | defaultISR, /* Reserved 58 */ | ||
181 | defaultISR, /* Reserved 59 */ | ||
182 | defaultISR, /* Reserved 60 */ | ||
183 | defaultISR, /* Reserved 61 */ | ||
184 | defaultISR, /* Reserved 62 */ | ||
185 | defaultISR /* Reserved 63 */ | ||
186 | }; | ||
187 | |||
188 | |||
189 | /* This is the code that gets called when the processor first starts execution */ | ||
190 | /* following a reset event. Only the absolutely necessary set is performed, */ | ||
191 | /* after which the application supplied entry() routine is called. Any fancy */ | ||
192 | /* actions (such as making decisions based on the reset cause register, and */ | ||
193 | /* resetting the bits in that register) are left solely in the hands of the */ | ||
194 | /* application. */ | ||
195 | void resetISR(void) | ||
196 | { | ||
197 | SystemInit(); | ||
198 | |||
199 | /* Jump to the CCS C Initialization Routine. */ | ||
200 | __asm(" .global _c_int00\n" | ||
201 | " b.w _c_int00"); | ||
202 | } | ||
203 | |||
204 | /* This is the code that gets called when the processor receives a NMI. This */ | ||
205 | /* simply enters an infinite loop, preserving the system state for examination */ | ||
206 | /* by a debugger. */ | ||
207 | static void nmiISR(void) | ||
208 | { | ||
209 | /* Fault trap exempt from ULP advisor */ | ||
210 | #pragma diag_push | ||
211 | #pragma CHECK_ULP("-2.1") | ||
212 | |||
213 | /* Enter an infinite loop. */ | ||
214 | while(1) | ||
215 | { | ||
216 | } | ||
217 | |||
218 | #pragma diag_pop | ||
219 | } | ||
220 | |||
221 | |||
222 | /* This is the code that gets called when the processor receives a fault */ | ||
223 | /* interrupt. This simply enters an infinite loop, preserving the system state */ | ||
224 | /* for examination by a debugger. */ | ||
225 | static void faultISR(void) | ||
226 | { | ||
227 | /* Fault trap exempt from ULP advisor */ | ||
228 | #pragma diag_push | ||
229 | #pragma CHECK_ULP("-2.1") | ||
230 | |||
231 | /* Enter an infinite loop. */ | ||
232 | while(1) | ||
233 | { | ||
234 | } | ||
235 | |||
236 | #pragma diag_pop | ||
237 | } | ||
238 | |||
239 | |||
240 | /* This is the code that gets called when the processor receives an unexpected */ | ||
241 | /* interrupt. This simply enters an infinite loop, preserving the system state */ | ||
242 | /* for examination by a debugger. */ | ||
243 | static void defaultISR(void) | ||
244 | { | ||
245 | /* Fault trap exempt from ULP advisor */ | ||
246 | #pragma diag_push | ||
247 | #pragma CHECK_ULP("-2.1") | ||
248 | |||
249 | /* Enter an infinite loop. */ | ||
250 | while(1) | ||
251 | { | ||
252 | } | ||
253 | |||
254 | #pragma diag_pop | ||
255 | } | ||