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authorNikhil Devshatwar2020-08-18 11:01:11 -0500
committerDave Gerlach2020-08-19 09:56:35 -0500
commit378d8a1dbd0fd911bd631d9a838dd5df77666385 (patch)
tree7ea946c48510854cf5954504a083754a06a0d5e1
parent8a598218c7e10636f3e6736f91d55778fe7a978f (diff)
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soc: j7200: Update RM board config with latest data
* Increase resource allocation for meeting RTOS use cases * Add block copy channel allocation Auto generated from k3-resource-partitioning tool commit ID 8e058012d5bcc457ae1f9212425d0d0ccd534752 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Diffstat
-rw-r--r--soc/j7200/evm/rm-cfg.c714
-rw-r--r--soc/j7200/evm/sysfw_img_cfg.h4
2 files changed, 520 insertions, 198 deletions
diff --git a/soc/j7200/evm/rm-cfg.c b/soc/j7200/evm/rm-cfg.c
index 24db2c917..9dc7048fa 100644
--- a/soc/j7200/evm/rm-cfg.c
+++ b/soc/j7200/evm/rm-cfg.c
@@ -2,7 +2,7 @@
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -258,7 +258,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
258 RESASG_SUBTYPE_IR_OUTPUT), 258 RESASG_SUBTYPE_IR_OUTPUT),
259 .host_id = HOST_ID_A72_3, 259 .host_id = HOST_ID_A72_3,
260 }, 260 },
261 /* MODSS Interrupt aggregator0 Virtual intettupts */ 261 /* MODSS Interrupt aggregator0 Virtual interrupts */
262 { 262 {
263 .start_resource = 0, 263 .start_resource = 0,
264 .num_resource = 64, 264 .num_resource = 64,
@@ -274,7 +274,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
274 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 274 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
275 .host_id = HOST_ID_ALL, 275 .host_id = HOST_ID_ALL,
276 }, 276 },
277 /* MODSS Interrupt aggregator1 Virtual intettupts */ 277 /* MODSS Interrupt aggregator1 Virtual interrupts */
278 { 278 {
279 .start_resource = 0, 279 .start_resource = 0,
280 .num_resource = 64, 280 .num_resource = 64,
@@ -307,21 +307,42 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
307 }, 307 },
308 { 308 {
309 .start_resource = 136, 309 .start_resource = 136,
310 .num_resource = 8, 310 .num_resource = 16,
311 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
312 RESASG_SUBTYPE_IA_VINT),
313 .host_id = HOST_ID_MCU_0_R5_0,
314 },
315 {
316 .start_resource = 136,
317 .num_resource = 16,
318 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
319 RESASG_SUBTYPE_IA_VINT),
320 .host_id = HOST_ID_MCU_0_R5_1,
321 },
322 {
323 .start_resource = 152,
324 .num_resource = 16,
325 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
326 RESASG_SUBTYPE_IA_VINT),
327 .host_id = HOST_ID_MCU_0_R5_2,
328 },
329 {
330 .start_resource = 168,
331 .num_resource = 32,
311 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 332 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
312 RESASG_SUBTYPE_IA_VINT), 333 RESASG_SUBTYPE_IA_VINT),
313 .host_id = HOST_ID_MAIN_0_R5_0, 334 .host_id = HOST_ID_MAIN_0_R5_0,
314 }, 335 },
315 { 336 {
316 .start_resource = 144, 337 .start_resource = 200,
317 .num_resource = 24, 338 .num_resource = 24,
318 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 339 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
319 RESASG_SUBTYPE_IA_VINT), 340 RESASG_SUBTYPE_IA_VINT),
320 .host_id = HOST_ID_MAIN_0_R5_2, 341 .host_id = HOST_ID_MAIN_0_R5_2,
321 }, 342 },
322 { 343 {
323 .start_resource = 168, 344 .start_resource = 224,
324 .num_resource = 88, 345 .num_resource = 32,
325 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 346 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
326 RESASG_SUBTYPE_IA_VINT), 347 RESASG_SUBTYPE_IA_VINT),
327 .host_id = HOST_ID_ALL, 348 .host_id = HOST_ID_ALL,
@@ -343,42 +364,42 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
343 }, 364 },
344 { 365 {
345 .start_resource = 1554, 366 .start_resource = 1554,
346 .num_resource = 32, 367 .num_resource = 128,
347 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 368 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
348 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 369 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
349 .host_id = HOST_ID_MCU_0_R5_0, 370 .host_id = HOST_ID_MCU_0_R5_0,
350 }, 371 },
351 { 372 {
352 .start_resource = 1554, 373 .start_resource = 1554,
353 .num_resource = 32, 374 .num_resource = 128,
354 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 375 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
355 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 376 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
356 .host_id = HOST_ID_MCU_0_R5_1, 377 .host_id = HOST_ID_MCU_0_R5_1,
357 }, 378 },
358 { 379 {
359 .start_resource = 1586, 380 .start_resource = 1682,
360 .num_resource = 32, 381 .num_resource = 128,
361 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 382 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
362 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 383 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
363 .host_id = HOST_ID_MCU_0_R5_2, 384 .host_id = HOST_ID_MCU_0_R5_2,
364 }, 385 },
365 { 386 {
366 .start_resource = 1618, 387 .start_resource = 1810,
367 .num_resource = 256, 388 .num_resource = 256,
368 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 389 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
369 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 390 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
370 .host_id = HOST_ID_MAIN_0_R5_0, 391 .host_id = HOST_ID_MAIN_0_R5_0,
371 }, 392 },
372 { 393 {
373 .start_resource = 1874, 394 .start_resource = 2066,
374 .num_resource = 512, 395 .num_resource = 512,
375 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 396 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
376 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 397 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
377 .host_id = HOST_ID_MAIN_0_R5_2, 398 .host_id = HOST_ID_MAIN_0_R5_2,
378 }, 399 },
379 { 400 {
380 .start_resource = 2386, 401 .start_resource = 2578,
381 .num_resource = 2222, 402 .num_resource = 2030,
382 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 403 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
383 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 404 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
384 .host_id = HOST_ID_ALL, 405 .host_id = HOST_ID_ALL,
@@ -421,26 +442,26 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
421 }, 442 },
422 { 443 {
423 .start_resource = 16, 444 .start_resource = 16,
424 .num_resource = 8, 445 .num_resource = 16,
425 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0, 446 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
426 RESASG_SUBTYPE_PROXY_PROXIES), 447 RESASG_SUBTYPE_PROXY_PROXIES),
427 .host_id = HOST_ID_MAIN_0_R5_0, 448 .host_id = HOST_ID_MAIN_0_R5_0,
428 }, 449 },
429 { 450 {
430 .start_resource = 24, 451 .start_resource = 32,
431 .num_resource = 8, 452 .num_resource = 16,
432 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0, 453 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
433 RESASG_SUBTYPE_PROXY_PROXIES), 454 RESASG_SUBTYPE_PROXY_PROXIES),
434 .host_id = HOST_ID_MAIN_0_R5_2, 455 .host_id = HOST_ID_MAIN_0_R5_2,
435 }, 456 },
436 { 457 {
437 .start_resource = 32, 458 .start_resource = 48,
438 .num_resource = 32, 459 .num_resource = 16,
439 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0, 460 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
440 RESASG_SUBTYPE_PROXY_PROXIES), 461 RESASG_SUBTYPE_PROXY_PROXIES),
441 .host_id = HOST_ID_ALL, 462 .host_id = HOST_ID_ALL,
442 }, 463 },
443 /* Main NAVSS Ringacc error event config */ 464 /* Main NAVSS Ring accelerator error event config */
444 { 465 {
445 .start_resource = 0, 466 .start_resource = 0,
446 .num_resource = 1, 467 .num_resource = 1,
@@ -448,178 +469,234 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
448 RESASG_SUBTYPE_RA_ERROR_OES), 469 RESASG_SUBTYPE_RA_ERROR_OES),
449 .host_id = HOST_ID_ALL, 470 .host_id = HOST_ID_ALL,
450 }, 471 },
451 /* Main NAVSS Ringacc Free rings */ 472 /* Main NAVSS Ring accelerator Free rings */
452 { 473 {
453 .start_resource = 120, 474 .start_resource = 120,
454 .num_resource = 150, 475 .num_resource = 200,
455 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 476 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
456 RESASG_SUBTYPE_RA_GP), 477 RESASG_SUBTYPE_RA_GP),
457 .host_id = HOST_ID_A72_2, 478 .host_id = HOST_ID_A72_2,
458 }, 479 },
459 { 480 {
460 .start_resource = 270, 481 .start_resource = 320,
461 .num_resource = 40, 482 .num_resource = 40,
462 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 483 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
463 RESASG_SUBTYPE_RA_GP), 484 RESASG_SUBTYPE_RA_GP),
464 .host_id = HOST_ID_A72_3, 485 .host_id = HOST_ID_A72_3,
465 }, 486 },
466 { 487 {
467 .start_resource = 310, 488 .start_resource = 360,
468 .num_resource = 6, 489 .num_resource = 32,
469 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 490 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
470 RESASG_SUBTYPE_RA_GP), 491 RESASG_SUBTYPE_RA_GP),
471 .host_id = HOST_ID_MCU_0_R5_0, 492 .host_id = HOST_ID_MCU_0_R5_0,
472 }, 493 },
473 { 494 {
474 .start_resource = 310, 495 .start_resource = 360,
475 .num_resource = 6, 496 .num_resource = 32,
476 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 497 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
477 RESASG_SUBTYPE_RA_GP), 498 RESASG_SUBTYPE_RA_GP),
478 .host_id = HOST_ID_MCU_0_R5_1, 499 .host_id = HOST_ID_MCU_0_R5_1,
479 }, 500 },
480 { 501 {
481 .start_resource = 316, 502 .start_resource = 392,
482 .num_resource = 6, 503 .num_resource = 32,
483 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 504 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
484 RESASG_SUBTYPE_RA_GP), 505 RESASG_SUBTYPE_RA_GP),
485 .host_id = HOST_ID_MCU_0_R5_2, 506 .host_id = HOST_ID_MCU_0_R5_2,
486 }, 507 },
487 { 508 {
488 .start_resource = 322, 509 .start_resource = 424,
489 .num_resource = 40, 510 .num_resource = 256,
490 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 511 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
491 RESASG_SUBTYPE_RA_GP), 512 RESASG_SUBTYPE_RA_GP),
492 .host_id = HOST_ID_MAIN_0_R5_0, 513 .host_id = HOST_ID_MAIN_0_R5_0,
493 }, 514 },
494 { 515 {
495 .start_resource = 362, 516 .start_resource = 680,
496 .num_resource = 182, 517 .num_resource = 256,
497 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 518 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
498 RESASG_SUBTYPE_RA_GP), 519 RESASG_SUBTYPE_RA_GP),
499 .host_id = HOST_ID_MAIN_0_R5_2, 520 .host_id = HOST_ID_MAIN_0_R5_2,
500 }, 521 },
501 { 522 {
502 .start_resource = 544, 523 .start_resource = 936,
503 .num_resource = 430, 524 .num_resource = 38,
504 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 525 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
505 RESASG_SUBTYPE_RA_GP), 526 RESASG_SUBTYPE_RA_GP),
506 .host_id = HOST_ID_ALL, 527 .host_id = HOST_ID_ALL,
507 }, 528 },
508 /* Main NAVSS Ringacc rings for Normal capacity Rx channels */ 529 /* Main NAVSS Rings for Normal capacity Rx channels */
509 { 530 {
510 .start_resource = 64, 531 .start_resource = 64,
511 .num_resource = 24, 532 .num_resource = 4,
512 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 533 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
513 RESASG_SUBTYPE_RA_UDMAP_RX), 534 RESASG_SUBTYPE_RA_UDMAP_RX),
514 .host_id = HOST_ID_A72_2, 535 .host_id = HOST_ID_A72_2,
515 }, 536 },
516 { 537 {
517 .start_resource = 88, 538 .start_resource = 68,
518 .num_resource = 10, 539 .num_resource = 2,
519 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 540 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
520 RESASG_SUBTYPE_RA_UDMAP_RX), 541 RESASG_SUBTYPE_RA_UDMAP_RX),
521 .host_id = HOST_ID_A72_3, 542 .host_id = HOST_ID_A72_3,
522 }, 543 },
523 { 544 {
524 .start_resource = 98, 545 .start_resource = 70,
525 .num_resource = 2, 546 .num_resource = 2,
526 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 547 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
527 RESASG_SUBTYPE_RA_UDMAP_RX), 548 RESASG_SUBTYPE_RA_UDMAP_RX),
528 .host_id = HOST_ID_MCU_0_R5_0, 549 .host_id = HOST_ID_MCU_0_R5_0,
529 }, 550 },
530 { 551 {
531 .start_resource = 98, 552 .start_resource = 70,
532 .num_resource = 2, 553 .num_resource = 2,
533 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 554 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
534 RESASG_SUBTYPE_RA_UDMAP_RX), 555 RESASG_SUBTYPE_RA_UDMAP_RX),
535 .host_id = HOST_ID_MCU_0_R5_1, 556 .host_id = HOST_ID_MCU_0_R5_1,
536 }, 557 },
537 { 558 {
538 .start_resource = 100, 559 .start_resource = 72,
539 .num_resource = 2, 560 .num_resource = 2,
540 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 561 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
541 RESASG_SUBTYPE_RA_UDMAP_RX), 562 RESASG_SUBTYPE_RA_UDMAP_RX),
542 .host_id = HOST_ID_MCU_0_R5_2, 563 .host_id = HOST_ID_MCU_0_R5_2,
543 }, 564 },
544 { 565 {
566 .start_resource = 74,
567 .num_resource = 2,
568 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
569 RESASG_SUBTYPE_RA_UDMAP_RX),
570 .host_id = HOST_ID_MAIN_0_R5_0,
571 },
572 {
573 .start_resource = 76,
574 .num_resource = 2,
575 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
576 RESASG_SUBTYPE_RA_UDMAP_RX),
577 .host_id = HOST_ID_MAIN_0_R5_2,
578 },
579 {
580 .start_resource = 78,
581 .num_resource = 20,
582 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
583 RESASG_SUBTYPE_RA_UDMAP_RX),
584 .host_id = HOST_ID_A72_2,
585 },
586 {
587 .start_resource = 98,
588 .num_resource = 4,
589 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
590 RESASG_SUBTYPE_RA_UDMAP_RX),
591 .host_id = HOST_ID_A72_3,
592 },
593 {
545 .start_resource = 102, 594 .start_resource = 102,
546 .num_resource = 7, 595 .num_resource = 8,
547 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 596 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
548 RESASG_SUBTYPE_RA_UDMAP_RX), 597 RESASG_SUBTYPE_RA_UDMAP_RX),
549 .host_id = HOST_ID_MAIN_0_R5_0, 598 .host_id = HOST_ID_MAIN_0_R5_0,
550 }, 599 },
551 { 600 {
552 .start_resource = 109, 601 .start_resource = 110,
553 .num_resource = 8, 602 .num_resource = 8,
554 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 603 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
555 RESASG_SUBTYPE_RA_UDMAP_RX), 604 RESASG_SUBTYPE_RA_UDMAP_RX),
556 .host_id = HOST_ID_MAIN_0_R5_2, 605 .host_id = HOST_ID_MAIN_0_R5_2,
557 }, 606 },
558 { 607 {
559 .start_resource = 117, 608 .start_resource = 118,
560 .num_resource = 3, 609 .num_resource = 2,
561 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 610 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
562 RESASG_SUBTYPE_RA_UDMAP_RX), 611 RESASG_SUBTYPE_RA_UDMAP_RX),
563 .host_id = HOST_ID_ALL, 612 .host_id = HOST_ID_ALL,
564 }, 613 },
565 /* Main NAVSS Ringacc rings for Normal capacity Tx channels */ 614 /* Main NAVSS Rings for Normal capacity Tx channels */
566 { 615 {
567 .start_resource = 4, 616 .start_resource = 4,
568 .num_resource = 24, 617 .num_resource = 4,
569 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 618 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
570 RESASG_SUBTYPE_RA_UDMAP_TX), 619 RESASG_SUBTYPE_RA_UDMAP_TX),
571 .host_id = HOST_ID_A72_2, 620 .host_id = HOST_ID_A72_2,
572 }, 621 },
573 { 622 {
574 .start_resource = 28, 623 .start_resource = 8,
575 .num_resource = 10, 624 .num_resource = 2,
576 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 625 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
577 RESASG_SUBTYPE_RA_UDMAP_TX), 626 RESASG_SUBTYPE_RA_UDMAP_TX),
578 .host_id = HOST_ID_A72_3, 627 .host_id = HOST_ID_A72_3,
579 }, 628 },
580 { 629 {
581 .start_resource = 38, 630 .start_resource = 10,
582 .num_resource = 2, 631 .num_resource = 2,
583 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 632 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
584 RESASG_SUBTYPE_RA_UDMAP_TX), 633 RESASG_SUBTYPE_RA_UDMAP_TX),
585 .host_id = HOST_ID_MCU_0_R5_0, 634 .host_id = HOST_ID_MCU_0_R5_0,
586 }, 635 },
587 { 636 {
588 .start_resource = 38, 637 .start_resource = 10,
589 .num_resource = 2, 638 .num_resource = 2,
590 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 639 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
591 RESASG_SUBTYPE_RA_UDMAP_TX), 640 RESASG_SUBTYPE_RA_UDMAP_TX),
592 .host_id = HOST_ID_MCU_0_R5_1, 641 .host_id = HOST_ID_MCU_0_R5_1,
593 }, 642 },
594 { 643 {
595 .start_resource = 40, 644 .start_resource = 12,
596 .num_resource = 2, 645 .num_resource = 2,
597 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 646 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
598 RESASG_SUBTYPE_RA_UDMAP_TX), 647 RESASG_SUBTYPE_RA_UDMAP_TX),
599 .host_id = HOST_ID_MCU_0_R5_2, 648 .host_id = HOST_ID_MCU_0_R5_2,
600 }, 649 },
601 { 650 {
651 .start_resource = 14,
652 .num_resource = 2,
653 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
654 RESASG_SUBTYPE_RA_UDMAP_TX),
655 .host_id = HOST_ID_MAIN_0_R5_0,
656 },
657 {
658 .start_resource = 16,
659 .num_resource = 2,
660 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
661 RESASG_SUBTYPE_RA_UDMAP_TX),
662 .host_id = HOST_ID_MAIN_0_R5_2,
663 },
664 {
665 .start_resource = 18,
666 .num_resource = 20,
667 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
668 RESASG_SUBTYPE_RA_UDMAP_TX),
669 .host_id = HOST_ID_A72_2,
670 },
671 {
672 .start_resource = 38,
673 .num_resource = 4,
674 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
675 RESASG_SUBTYPE_RA_UDMAP_TX),
676 .host_id = HOST_ID_A72_3,
677 },
678 {
602 .start_resource = 42, 679 .start_resource = 42,
603 .num_resource = 7, 680 .num_resource = 8,
604 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 681 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
605 RESASG_SUBTYPE_RA_UDMAP_TX), 682 RESASG_SUBTYPE_RA_UDMAP_TX),
606 .host_id = HOST_ID_MAIN_0_R5_0, 683 .host_id = HOST_ID_MAIN_0_R5_0,
607 }, 684 },
608 { 685 {
609 .start_resource = 49, 686 .start_resource = 50,
610 .num_resource = 8, 687 .num_resource = 8,
611 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 688 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
612 RESASG_SUBTYPE_RA_UDMAP_TX), 689 RESASG_SUBTYPE_RA_UDMAP_TX),
613 .host_id = HOST_ID_MAIN_0_R5_2, 690 .host_id = HOST_ID_MAIN_0_R5_2,
614 }, 691 },
615 { 692 {
616 .start_resource = 57, 693 .start_resource = 58,
617 .num_resource = 3, 694 .num_resource = 2,
618 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 695 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
619 RESASG_SUBTYPE_RA_UDMAP_TX), 696 RESASG_SUBTYPE_RA_UDMAP_TX),
620 .host_id = HOST_ID_ALL, 697 .host_id = HOST_ID_ALL,
621 }, 698 },
622 /* Main NAVSS Ringacc rings for High capacity Rx channels */ 699 /* Main NAVSS Rings for High capacity Rx channels */
623 { 700 {
624 .start_resource = 62, 701 .start_resource = 62,
625 .num_resource = 2, 702 .num_resource = 2,
@@ -627,7 +704,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
627 RESASG_SUBTYPE_RA_UDMAP_RX_H), 704 RESASG_SUBTYPE_RA_UDMAP_RX_H),
628 .host_id = HOST_ID_MAIN_0_R5_0, 705 .host_id = HOST_ID_MAIN_0_R5_0,
629 }, 706 },
630 /* Main NAVSS Ringacc rings for Ultra high capacity Rx channels */ 707 /* Main NAVSS Rings for Ultra high capacity Rx channels */
631 { 708 {
632 .start_resource = 60, 709 .start_resource = 60,
633 .num_resource = 2, 710 .num_resource = 2,
@@ -635,7 +712,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
635 RESASG_SUBTYPE_RA_UDMAP_RX_UH), 712 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
636 .host_id = HOST_ID_MAIN_0_R5_2, 713 .host_id = HOST_ID_MAIN_0_R5_2,
637 }, 714 },
638 /* Main NAVSS Ringacc rings for High capacity Tx channels */ 715 /* Main NAVSS Rings for High capacity Tx channels */
639 { 716 {
640 .start_resource = 2, 717 .start_resource = 2,
641 .num_resource = 2, 718 .num_resource = 2,
@@ -643,7 +720,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
643 RESASG_SUBTYPE_RA_UDMAP_TX_H), 720 RESASG_SUBTYPE_RA_UDMAP_TX_H),
644 .host_id = HOST_ID_MAIN_0_R5_0, 721 .host_id = HOST_ID_MAIN_0_R5_0,
645 }, 722 },
646 /* Main NAVSS Ringacc rings for Ultra high capacity Tx channels */ 723 /* Main NAVSS Rings for Ultra high capacity Tx channels */
647 { 724 {
648 .start_resource = 0, 725 .start_resource = 0,
649 .num_resource = 2, 726 .num_resource = 2,
@@ -651,7 +728,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
651 RESASG_SUBTYPE_RA_UDMAP_TX_UH), 728 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
652 .host_id = HOST_ID_MAIN_0_R5_2, 729 .host_id = HOST_ID_MAIN_0_R5_2,
653 }, 730 },
654 /* Main NAVSS Ringacc virt_id range */ 731 /* Main NAVSS Ring accelerator virt_id range */
655 { 732 {
656 .start_resource = 2, 733 .start_resource = 2,
657 .num_resource = 1, 734 .num_resource = 1,
@@ -666,7 +743,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
666 RESASG_SUBTYPE_RA_VIRTID), 743 RESASG_SUBTYPE_RA_VIRTID),
667 .host_id = HOST_ID_A72_3, 744 .host_id = HOST_ID_A72_3,
668 }, 745 },
669 /* Main NAVSS Ringacc ring monitors */ 746 /* Main NAVSS Ring accelerator ring monitors */
670 { 747 {
671 .start_resource = 0, 748 .start_resource = 0,
672 .num_resource = 3, 749 .num_resource = 3,
@@ -704,21 +781,21 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
704 }, 781 },
705 { 782 {
706 .start_resource = 7, 783 .start_resource = 7,
707 .num_resource = 6, 784 .num_resource = 16,
708 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 785 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
709 RESASG_SUBTYPE_RA_MONITORS), 786 RESASG_SUBTYPE_RA_MONITORS),
710 .host_id = HOST_ID_MAIN_0_R5_0, 787 .host_id = HOST_ID_MAIN_0_R5_0,
711 }, 788 },
712 { 789 {
713 .start_resource = 13, 790 .start_resource = 23,
714 .num_resource = 3, 791 .num_resource = 8,
715 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 792 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
716 RESASG_SUBTYPE_RA_MONITORS), 793 RESASG_SUBTYPE_RA_MONITORS),
717 .host_id = HOST_ID_MAIN_0_R5_2, 794 .host_id = HOST_ID_MAIN_0_R5_2,
718 }, 795 },
719 { 796 {
720 .start_resource = 16, 797 .start_resource = 31,
721 .num_resource = 16, 798 .num_resource = 1,
722 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 799 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
723 RESASG_SUBTYPE_RA_MONITORS), 800 RESASG_SUBTYPE_RA_MONITORS),
724 .host_id = HOST_ID_ALL, 801 .host_id = HOST_ID_ALL,
@@ -740,21 +817,14 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
740 }, 817 },
741 { 818 {
742 .start_resource = 76, 819 .start_resource = 76,
743 .num_resource = 64,
744 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
745 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
746 .host_id = HOST_ID_MAIN_0_R5_0,
747 },
748 {
749 .start_resource = 140,
750 .num_resource = 8, 820 .num_resource = 8,
751 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 821 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
752 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), 822 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
753 .host_id = HOST_ID_MAIN_0_R5_2, 823 .host_id = HOST_ID_MAIN_0_R5_2,
754 }, 824 },
755 { 825 {
756 .start_resource = 148, 826 .start_resource = 84,
757 .num_resource = 2, 827 .num_resource = 66,
758 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 828 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
759 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), 829 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
760 .host_id = HOST_ID_ALL, 830 .host_id = HOST_ID_ALL,
@@ -786,56 +856,84 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
786 /* Main NAVSS UDMA Normal capacity Rx channels */ 856 /* Main NAVSS UDMA Normal capacity Rx channels */
787 { 857 {
788 .start_resource = 4, 858 .start_resource = 4,
789 .num_resource = 24, 859 .num_resource = 4,
790 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 860 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
791 RESASG_SUBTYPE_UDMAP_RX_CHAN), 861 RESASG_SUBTYPE_UDMAP_RX_CHAN),
792 .host_id = HOST_ID_A72_2, 862 .host_id = HOST_ID_A72_2,
793 }, 863 },
794 { 864 {
795 .start_resource = 28, 865 .start_resource = 8,
796 .num_resource = 10, 866 .num_resource = 2,
797 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 867 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
798 RESASG_SUBTYPE_UDMAP_RX_CHAN), 868 RESASG_SUBTYPE_UDMAP_RX_CHAN),
799 .host_id = HOST_ID_A72_3, 869 .host_id = HOST_ID_A72_3,
800 }, 870 },
801 { 871 {
802 .start_resource = 38, 872 .start_resource = 10,
803 .num_resource = 2, 873 .num_resource = 2,
804 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 874 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
805 RESASG_SUBTYPE_UDMAP_RX_CHAN), 875 RESASG_SUBTYPE_UDMAP_RX_CHAN),
806 .host_id = HOST_ID_MCU_0_R5_0, 876 .host_id = HOST_ID_MCU_0_R5_0,
807 }, 877 },
808 { 878 {
809 .start_resource = 38, 879 .start_resource = 10,
810 .num_resource = 2, 880 .num_resource = 2,
811 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 881 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
812 RESASG_SUBTYPE_UDMAP_RX_CHAN), 882 RESASG_SUBTYPE_UDMAP_RX_CHAN),
813 .host_id = HOST_ID_MCU_0_R5_1, 883 .host_id = HOST_ID_MCU_0_R5_1,
814 }, 884 },
815 { 885 {
816 .start_resource = 40, 886 .start_resource = 12,
817 .num_resource = 2, 887 .num_resource = 2,
818 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 888 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
819 RESASG_SUBTYPE_UDMAP_RX_CHAN), 889 RESASG_SUBTYPE_UDMAP_RX_CHAN),
820 .host_id = HOST_ID_MCU_0_R5_2, 890 .host_id = HOST_ID_MCU_0_R5_2,
821 }, 891 },
822 { 892 {
893 .start_resource = 14,
894 .num_resource = 2,
895 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
896 RESASG_SUBTYPE_UDMAP_RX_CHAN),
897 .host_id = HOST_ID_MAIN_0_R5_0,
898 },
899 {
900 .start_resource = 16,
901 .num_resource = 2,
902 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
903 RESASG_SUBTYPE_UDMAP_RX_CHAN),
904 .host_id = HOST_ID_MAIN_0_R5_2,
905 },
906 {
907 .start_resource = 18,
908 .num_resource = 20,
909 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
910 RESASG_SUBTYPE_UDMAP_RX_CHAN),
911 .host_id = HOST_ID_A72_2,
912 },
913 {
914 .start_resource = 38,
915 .num_resource = 4,
916 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
917 RESASG_SUBTYPE_UDMAP_RX_CHAN),
918 .host_id = HOST_ID_A72_3,
919 },
920 {
823 .start_resource = 42, 921 .start_resource = 42,
824 .num_resource = 7, 922 .num_resource = 8,
825 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 923 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
826 RESASG_SUBTYPE_UDMAP_RX_CHAN), 924 RESASG_SUBTYPE_UDMAP_RX_CHAN),
827 .host_id = HOST_ID_MAIN_0_R5_0, 925 .host_id = HOST_ID_MAIN_0_R5_0,
828 }, 926 },
829 { 927 {
830 .start_resource = 49, 928 .start_resource = 50,
831 .num_resource = 8, 929 .num_resource = 8,
832 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 930 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
833 RESASG_SUBTYPE_UDMAP_RX_CHAN), 931 RESASG_SUBTYPE_UDMAP_RX_CHAN),
834 .host_id = HOST_ID_MAIN_0_R5_2, 932 .host_id = HOST_ID_MAIN_0_R5_2,
835 }, 933 },
836 { 934 {
837 .start_resource = 57, 935 .start_resource = 58,
838 .num_resource = 3, 936 .num_resource = 2,
839 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 937 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
840 RESASG_SUBTYPE_UDMAP_RX_CHAN), 938 RESASG_SUBTYPE_UDMAP_RX_CHAN),
841 .host_id = HOST_ID_ALL, 939 .host_id = HOST_ID_ALL,
@@ -859,56 +957,84 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
859 /* Main NAVSS UDMA Normal capacity Tx channels */ 957 /* Main NAVSS UDMA Normal capacity Tx channels */
860 { 958 {
861 .start_resource = 4, 959 .start_resource = 4,
862 .num_resource = 24, 960 .num_resource = 4,
863 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 961 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
864 RESASG_SUBTYPE_UDMAP_TX_CHAN), 962 RESASG_SUBTYPE_UDMAP_TX_CHAN),
865 .host_id = HOST_ID_A72_2, 963 .host_id = HOST_ID_A72_2,
866 }, 964 },
867 { 965 {
868 .start_resource = 28, 966 .start_resource = 8,
869 .num_resource = 10, 967 .num_resource = 2,
870 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 968 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
871 RESASG_SUBTYPE_UDMAP_TX_CHAN), 969 RESASG_SUBTYPE_UDMAP_TX_CHAN),
872 .host_id = HOST_ID_A72_3, 970 .host_id = HOST_ID_A72_3,
873 }, 971 },
874 { 972 {
875 .start_resource = 38, 973 .start_resource = 10,
876 .num_resource = 2, 974 .num_resource = 2,
877 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 975 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
878 RESASG_SUBTYPE_UDMAP_TX_CHAN), 976 RESASG_SUBTYPE_UDMAP_TX_CHAN),
879 .host_id = HOST_ID_MCU_0_R5_0, 977 .host_id = HOST_ID_MCU_0_R5_0,
880 }, 978 },
881 { 979 {
882 .start_resource = 38, 980 .start_resource = 10,
883 .num_resource = 2, 981 .num_resource = 2,
884 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 982 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
885 RESASG_SUBTYPE_UDMAP_TX_CHAN), 983 RESASG_SUBTYPE_UDMAP_TX_CHAN),
886 .host_id = HOST_ID_MCU_0_R5_1, 984 .host_id = HOST_ID_MCU_0_R5_1,
887 }, 985 },
888 { 986 {
889 .start_resource = 40, 987 .start_resource = 12,
890 .num_resource = 2, 988 .num_resource = 2,
891 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 989 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
892 RESASG_SUBTYPE_UDMAP_TX_CHAN), 990 RESASG_SUBTYPE_UDMAP_TX_CHAN),
893 .host_id = HOST_ID_MCU_0_R5_2, 991 .host_id = HOST_ID_MCU_0_R5_2,
894 }, 992 },
895 { 993 {
994 .start_resource = 14,
995 .num_resource = 2,
996 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
997 RESASG_SUBTYPE_UDMAP_TX_CHAN),
998 .host_id = HOST_ID_MAIN_0_R5_0,
999 },
1000 {
1001 .start_resource = 16,
1002 .num_resource = 2,
1003 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1004 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1005 .host_id = HOST_ID_MAIN_0_R5_2,
1006 },
1007 {
1008 .start_resource = 18,
1009 .num_resource = 20,
1010 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1011 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1012 .host_id = HOST_ID_A72_2,
1013 },
1014 {
1015 .start_resource = 38,
1016 .num_resource = 4,
1017 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1018 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1019 .host_id = HOST_ID_A72_3,
1020 },
1021 {
896 .start_resource = 42, 1022 .start_resource = 42,
897 .num_resource = 7, 1023 .num_resource = 8,
898 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1024 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
899 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1025 RESASG_SUBTYPE_UDMAP_TX_CHAN),
900 .host_id = HOST_ID_MAIN_0_R5_0, 1026 .host_id = HOST_ID_MAIN_0_R5_0,
901 }, 1027 },
902 { 1028 {
903 .start_resource = 49, 1029 .start_resource = 50,
904 .num_resource = 8, 1030 .num_resource = 8,
905 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1031 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
906 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1032 RESASG_SUBTYPE_UDMAP_TX_CHAN),
907 .host_id = HOST_ID_MAIN_0_R5_2, 1033 .host_id = HOST_ID_MAIN_0_R5_2,
908 }, 1034 },
909 { 1035 {
910 .start_resource = 57, 1036 .start_resource = 58,
911 .num_resource = 3, 1037 .num_resource = 2,
912 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1038 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
913 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1039 RESASG_SUBTYPE_UDMAP_TX_CHAN),
914 .host_id = HOST_ID_ALL, 1040 .host_id = HOST_ID_ALL,
@@ -1010,28 +1136,28 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1010 }, 1136 },
1011 { 1137 {
1012 .start_resource = 120, 1138 .start_resource = 120,
1013 .num_resource = 4, 1139 .num_resource = 32,
1014 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1140 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1015 RESASG_SUBTYPE_IA_VINT), 1141 RESASG_SUBTYPE_IA_VINT),
1016 .host_id = HOST_ID_MCU_0_R5_2, 1142 .host_id = HOST_ID_MCU_0_R5_2,
1017 }, 1143 },
1018 { 1144 {
1019 .start_resource = 124, 1145 .start_resource = 152,
1020 .num_resource = 16, 1146 .num_resource = 16,
1021 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1147 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1022 RESASG_SUBTYPE_IA_VINT), 1148 RESASG_SUBTYPE_IA_VINT),
1023 .host_id = HOST_ID_MAIN_0_R5_0, 1149 .host_id = HOST_ID_MAIN_0_R5_0,
1024 }, 1150 },
1025 { 1151 {
1026 .start_resource = 140, 1152 .start_resource = 168,
1027 .num_resource = 16, 1153 .num_resource = 16,
1028 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1154 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1029 RESASG_SUBTYPE_IA_VINT), 1155 RESASG_SUBTYPE_IA_VINT),
1030 .host_id = HOST_ID_MAIN_0_R5_2, 1156 .host_id = HOST_ID_MAIN_0_R5_2,
1031 }, 1157 },
1032 { 1158 {
1033 .start_resource = 156, 1159 .start_resource = 184,
1034 .num_resource = 100, 1160 .num_resource = 72,
1035 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1161 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1036 RESASG_SUBTYPE_IA_VINT), 1162 RESASG_SUBTYPE_IA_VINT),
1037 .host_id = HOST_ID_ALL, 1163 .host_id = HOST_ID_ALL,
@@ -1067,28 +1193,28 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1067 }, 1193 },
1068 { 1194 {
1069 .start_resource = 16904, 1195 .start_resource = 16904,
1070 .num_resource = 64, 1196 .num_resource = 128,
1071 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1197 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1072 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1198 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1073 .host_id = HOST_ID_MCU_0_R5_2, 1199 .host_id = HOST_ID_MCU_0_R5_2,
1074 }, 1200 },
1075 { 1201 {
1076 .start_resource = 16968, 1202 .start_resource = 17032,
1077 .num_resource = 128, 1203 .num_resource = 128,
1078 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1204 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1079 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1205 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1080 .host_id = HOST_ID_MAIN_0_R5_0, 1206 .host_id = HOST_ID_MAIN_0_R5_0,
1081 }, 1207 },
1082 { 1208 {
1083 .start_resource = 17096, 1209 .start_resource = 17160,
1084 .num_resource = 128, 1210 .num_resource = 128,
1085 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1211 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1086 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1212 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1087 .host_id = HOST_ID_MAIN_0_R5_2, 1213 .host_id = HOST_ID_MAIN_0_R5_2,
1088 }, 1214 },
1089 { 1215 {
1090 .start_resource = 17224, 1216 .start_resource = 17288,
1091 .num_resource = 696, 1217 .num_resource = 632,
1092 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1218 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1093 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1219 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1094 .host_id = HOST_ID_ALL, 1220 .host_id = HOST_ID_ALL,
@@ -1110,47 +1236,47 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1110 }, 1236 },
1111 { 1237 {
1112 .start_resource = 13, 1238 .start_resource = 13,
1113 .num_resource = 8, 1239 .num_resource = 16,
1114 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1240 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1115 RESASG_SUBTYPE_PROXY_PROXIES), 1241 RESASG_SUBTYPE_PROXY_PROXIES),
1116 .host_id = HOST_ID_MCU_0_R5_0, 1242 .host_id = HOST_ID_MCU_0_R5_0,
1117 }, 1243 },
1118 { 1244 {
1119 .start_resource = 13, 1245 .start_resource = 13,
1120 .num_resource = 8, 1246 .num_resource = 16,
1121 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1247 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1122 RESASG_SUBTYPE_PROXY_PROXIES), 1248 RESASG_SUBTYPE_PROXY_PROXIES),
1123 .host_id = HOST_ID_MCU_0_R5_1, 1249 .host_id = HOST_ID_MCU_0_R5_1,
1124 }, 1250 },
1125 { 1251 {
1126 .start_resource = 21, 1252 .start_resource = 29,
1127 .num_resource = 8, 1253 .num_resource = 16,
1128 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1254 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1129 RESASG_SUBTYPE_PROXY_PROXIES), 1255 RESASG_SUBTYPE_PROXY_PROXIES),
1130 .host_id = HOST_ID_MCU_0_R5_2, 1256 .host_id = HOST_ID_MCU_0_R5_2,
1131 }, 1257 },
1132 { 1258 {
1133 .start_resource = 29, 1259 .start_resource = 45,
1134 .num_resource = 16, 1260 .num_resource = 8,
1135 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1261 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1136 RESASG_SUBTYPE_PROXY_PROXIES), 1262 RESASG_SUBTYPE_PROXY_PROXIES),
1137 .host_id = HOST_ID_MAIN_0_R5_0, 1263 .host_id = HOST_ID_MAIN_0_R5_0,
1138 }, 1264 },
1139 { 1265 {
1140 .start_resource = 45, 1266 .start_resource = 53,
1141 .num_resource = 12, 1267 .num_resource = 8,
1142 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1268 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1143 RESASG_SUBTYPE_PROXY_PROXIES), 1269 RESASG_SUBTYPE_PROXY_PROXIES),
1144 .host_id = HOST_ID_MAIN_0_R5_2, 1270 .host_id = HOST_ID_MAIN_0_R5_2,
1145 }, 1271 },
1146 { 1272 {
1147 .start_resource = 57, 1273 .start_resource = 61,
1148 .num_resource = 7, 1274 .num_resource = 3,
1149 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1275 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1150 RESASG_SUBTYPE_PROXY_PROXIES), 1276 RESASG_SUBTYPE_PROXY_PROXIES),
1151 .host_id = HOST_ID_ALL, 1277 .host_id = HOST_ID_ALL,
1152 }, 1278 },
1153 /* MCU NAVSS Ringacc error event config */ 1279 /* MCU NAVSS Ring accelerator error event config */
1154 { 1280 {
1155 .start_resource = 0, 1281 .start_resource = 0,
1156 .num_resource = 1, 1282 .num_resource = 1,
@@ -1158,178 +1284,276 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1158 RESASG_SUBTYPE_RA_ERROR_OES), 1284 RESASG_SUBTYPE_RA_ERROR_OES),
1159 .host_id = HOST_ID_ALL, 1285 .host_id = HOST_ID_ALL,
1160 }, 1286 },
1161 /* MCU NAVSS Ringacc free rings */ 1287 /* MCU NAVSS Ring accelerator Free rings */
1162 { 1288 {
1163 .start_resource = 96, 1289 .start_resource = 96,
1164 .num_resource = 20, 1290 .num_resource = 32,
1165 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1291 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1166 RESASG_SUBTYPE_RA_GP), 1292 RESASG_SUBTYPE_RA_GP),
1167 .host_id = HOST_ID_A72_2, 1293 .host_id = HOST_ID_A72_2,
1168 }, 1294 },
1169 { 1295 {
1170 .start_resource = 116, 1296 .start_resource = 128,
1171 .num_resource = 8, 1297 .num_resource = 16,
1172 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1298 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1173 RESASG_SUBTYPE_RA_GP), 1299 RESASG_SUBTYPE_RA_GP),
1174 .host_id = HOST_ID_A72_3, 1300 .host_id = HOST_ID_A72_3,
1175 }, 1301 },
1176 { 1302 {
1177 .start_resource = 124, 1303 .start_resource = 144,
1178 .num_resource = 32, 1304 .num_resource = 32,
1179 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1305 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1180 RESASG_SUBTYPE_RA_GP), 1306 RESASG_SUBTYPE_RA_GP),
1181 .host_id = HOST_ID_MCU_0_R5_0, 1307 .host_id = HOST_ID_MCU_0_R5_0,
1182 }, 1308 },
1183 { 1309 {
1184 .start_resource = 124, 1310 .start_resource = 144,
1185 .num_resource = 32, 1311 .num_resource = 32,
1186 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1312 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1187 RESASG_SUBTYPE_RA_GP), 1313 RESASG_SUBTYPE_RA_GP),
1188 .host_id = HOST_ID_MCU_0_R5_1, 1314 .host_id = HOST_ID_MCU_0_R5_1,
1189 }, 1315 },
1190 { 1316 {
1191 .start_resource = 156, 1317 .start_resource = 176,
1192 .num_resource = 12, 1318 .num_resource = 32,
1193 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1319 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1194 RESASG_SUBTYPE_RA_GP), 1320 RESASG_SUBTYPE_RA_GP),
1195 .host_id = HOST_ID_MCU_0_R5_2, 1321 .host_id = HOST_ID_MCU_0_R5_2,
1196 }, 1322 },
1197 { 1323 {
1198 .start_resource = 168, 1324 .start_resource = 208,
1199 .num_resource = 16, 1325 .num_resource = 16,
1200 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1326 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1201 RESASG_SUBTYPE_RA_GP), 1327 RESASG_SUBTYPE_RA_GP),
1202 .host_id = HOST_ID_MAIN_0_R5_0, 1328 .host_id = HOST_ID_MAIN_0_R5_0,
1203 }, 1329 },
1204 { 1330 {
1205 .start_resource = 184, 1331 .start_resource = 224,
1206 .num_resource = 8, 1332 .num_resource = 16,
1207 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1333 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1208 RESASG_SUBTYPE_RA_GP), 1334 RESASG_SUBTYPE_RA_GP),
1209 .host_id = HOST_ID_MAIN_0_R5_2, 1335 .host_id = HOST_ID_MAIN_0_R5_2,
1210 }, 1336 },
1211 { 1337 {
1212 .start_resource = 192, 1338 .start_resource = 240,
1213 .num_resource = 60, 1339 .num_resource = 12,
1214 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1340 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1215 RESASG_SUBTYPE_RA_GP), 1341 RESASG_SUBTYPE_RA_GP),
1216 .host_id = HOST_ID_ALL, 1342 .host_id = HOST_ID_ALL,
1217 }, 1343 },
1218 /* MCU NAVSS Ringacc rings for Normal capacity Rx channels */ 1344 /* MCU NAVSS Rings for Normal capacity Rx channels */
1219 { 1345 {
1220 .start_resource = 50, 1346 .start_resource = 50,
1221 .num_resource = 12, 1347 .num_resource = 3,
1222 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1348 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1223 RESASG_SUBTYPE_RA_UDMAP_RX), 1349 RESASG_SUBTYPE_RA_UDMAP_RX),
1224 .host_id = HOST_ID_A72_2, 1350 .host_id = HOST_ID_A72_2,
1225 }, 1351 },
1226 { 1352 {
1227 .start_resource = 62, 1353 .start_resource = 53,
1228 .num_resource = 6, 1354 .num_resource = 2,
1229 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1355 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1230 RESASG_SUBTYPE_RA_UDMAP_RX), 1356 RESASG_SUBTYPE_RA_UDMAP_RX),
1231 .host_id = HOST_ID_A72_3, 1357 .host_id = HOST_ID_A72_3,
1232 }, 1358 },
1233 { 1359 {
1234 .start_resource = 68, 1360 .start_resource = 55,
1235 .num_resource = 5, 1361 .num_resource = 2,
1236 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1362 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1237 RESASG_SUBTYPE_RA_UDMAP_RX), 1363 RESASG_SUBTYPE_RA_UDMAP_RX),
1238 .host_id = HOST_ID_MCU_0_R5_0, 1364 .host_id = HOST_ID_MCU_0_R5_0,
1239 }, 1365 },
1240 { 1366 {
1241 .start_resource = 68, 1367 .start_resource = 55,
1242 .num_resource = 5, 1368 .num_resource = 2,
1243 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1369 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1244 RESASG_SUBTYPE_RA_UDMAP_RX), 1370 RESASG_SUBTYPE_RA_UDMAP_RX),
1245 .host_id = HOST_ID_MCU_0_R5_1, 1371 .host_id = HOST_ID_MCU_0_R5_1,
1246 }, 1372 },
1247 { 1373 {
1248 .start_resource = 73, 1374 .start_resource = 57,
1249 .num_resource = 2, 1375 .num_resource = 2,
1250 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1376 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1251 RESASG_SUBTYPE_RA_UDMAP_RX), 1377 RESASG_SUBTYPE_RA_UDMAP_RX),
1252 .host_id = HOST_ID_MCU_0_R5_2, 1378 .host_id = HOST_ID_MCU_0_R5_2,
1253 }, 1379 },
1254 { 1380 {
1255 .start_resource = 75, 1381 .start_resource = 59,
1256 .num_resource = 3, 1382 .num_resource = 2,
1257 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1383 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1258 RESASG_SUBTYPE_RA_UDMAP_RX), 1384 RESASG_SUBTYPE_RA_UDMAP_RX),
1259 .host_id = HOST_ID_MAIN_0_R5_0, 1385 .host_id = HOST_ID_MAIN_0_R5_0,
1260 }, 1386 },
1261 { 1387 {
1262 .start_resource = 78, 1388 .start_resource = 61,
1263 .num_resource = 2, 1389 .num_resource = 2,
1264 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1390 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1265 RESASG_SUBTYPE_RA_UDMAP_RX), 1391 RESASG_SUBTYPE_RA_UDMAP_RX),
1266 .host_id = HOST_ID_MAIN_0_R5_2, 1392 .host_id = HOST_ID_MAIN_0_R5_2,
1267 }, 1393 },
1268 { 1394 {
1395 .start_resource = 63,
1396 .num_resource = 9,
1397 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1398 RESASG_SUBTYPE_RA_UDMAP_RX),
1399 .host_id = HOST_ID_A72_2,
1400 },
1401 {
1402 .start_resource = 72,
1403 .num_resource = 4,
1404 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1405 RESASG_SUBTYPE_RA_UDMAP_RX),
1406 .host_id = HOST_ID_A72_3,
1407 },
1408 {
1409 .start_resource = 76,
1410 .num_resource = 4,
1411 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1412 RESASG_SUBTYPE_RA_UDMAP_RX),
1413 .host_id = HOST_ID_MCU_0_R5_0,
1414 },
1415 {
1416 .start_resource = 76,
1417 .num_resource = 4,
1418 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1419 RESASG_SUBTYPE_RA_UDMAP_RX),
1420 .host_id = HOST_ID_MCU_0_R5_1,
1421 },
1422 {
1269 .start_resource = 80, 1423 .start_resource = 80,
1270 .num_resource = 13, 1424 .num_resource = 4,
1425 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1426 RESASG_SUBTYPE_RA_UDMAP_RX),
1427 .host_id = HOST_ID_MCU_0_R5_2,
1428 },
1429 {
1430 .start_resource = 84,
1431 .num_resource = 4,
1432 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1433 RESASG_SUBTYPE_RA_UDMAP_RX),
1434 .host_id = HOST_ID_MAIN_0_R5_0,
1435 },
1436 {
1437 .start_resource = 88,
1438 .num_resource = 4,
1439 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1440 RESASG_SUBTYPE_RA_UDMAP_RX),
1441 .host_id = HOST_ID_MAIN_0_R5_2,
1442 },
1443 {
1444 .start_resource = 92,
1445 .num_resource = 1,
1271 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1446 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1272 RESASG_SUBTYPE_RA_UDMAP_RX), 1447 RESASG_SUBTYPE_RA_UDMAP_RX),
1273 .host_id = HOST_ID_ALL, 1448 .host_id = HOST_ID_ALL,
1274 }, 1449 },
1275 /* MCU NAVSS Ringacc rings for Normal capacity Tx channels */ 1450 /* MCU NAVSS Rings for Normal capacity Tx channels */
1276 { 1451 {
1277 .start_resource = 2, 1452 .start_resource = 2,
1278 .num_resource = 12, 1453 .num_resource = 3,
1279 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1454 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1280 RESASG_SUBTYPE_RA_UDMAP_TX), 1455 RESASG_SUBTYPE_RA_UDMAP_TX),
1281 .host_id = HOST_ID_A72_2, 1456 .host_id = HOST_ID_A72_2,
1282 }, 1457 },
1283 { 1458 {
1284 .start_resource = 14, 1459 .start_resource = 5,
1285 .num_resource = 6, 1460 .num_resource = 2,
1286 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1461 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1287 RESASG_SUBTYPE_RA_UDMAP_TX), 1462 RESASG_SUBTYPE_RA_UDMAP_TX),
1288 .host_id = HOST_ID_A72_3, 1463 .host_id = HOST_ID_A72_3,
1289 }, 1464 },
1290 { 1465 {
1291 .start_resource = 20, 1466 .start_resource = 7,
1292 .num_resource = 5, 1467 .num_resource = 2,
1293 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1468 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1294 RESASG_SUBTYPE_RA_UDMAP_TX), 1469 RESASG_SUBTYPE_RA_UDMAP_TX),
1295 .host_id = HOST_ID_MCU_0_R5_0, 1470 .host_id = HOST_ID_MCU_0_R5_0,
1296 }, 1471 },
1297 { 1472 {
1298 .start_resource = 20, 1473 .start_resource = 7,
1299 .num_resource = 5, 1474 .num_resource = 2,
1300 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1475 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1301 RESASG_SUBTYPE_RA_UDMAP_TX), 1476 RESASG_SUBTYPE_RA_UDMAP_TX),
1302 .host_id = HOST_ID_MCU_0_R5_1, 1477 .host_id = HOST_ID_MCU_0_R5_1,
1303 }, 1478 },
1304 { 1479 {
1305 .start_resource = 25, 1480 .start_resource = 9,
1306 .num_resource = 2, 1481 .num_resource = 2,
1307 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1482 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1308 RESASG_SUBTYPE_RA_UDMAP_TX), 1483 RESASG_SUBTYPE_RA_UDMAP_TX),
1309 .host_id = HOST_ID_MCU_0_R5_2, 1484 .host_id = HOST_ID_MCU_0_R5_2,
1310 }, 1485 },
1311 { 1486 {
1312 .start_resource = 27, 1487 .start_resource = 11,
1313 .num_resource = 3, 1488 .num_resource = 2,
1314 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1489 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1315 RESASG_SUBTYPE_RA_UDMAP_TX), 1490 RESASG_SUBTYPE_RA_UDMAP_TX),
1316 .host_id = HOST_ID_MAIN_0_R5_0, 1491 .host_id = HOST_ID_MAIN_0_R5_0,
1317 }, 1492 },
1318 { 1493 {
1319 .start_resource = 30, 1494 .start_resource = 13,
1320 .num_resource = 2, 1495 .num_resource = 2,
1321 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1496 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1322 RESASG_SUBTYPE_RA_UDMAP_TX), 1497 RESASG_SUBTYPE_RA_UDMAP_TX),
1323 .host_id = HOST_ID_MAIN_0_R5_2, 1498 .host_id = HOST_ID_MAIN_0_R5_2,
1324 }, 1499 },
1325 { 1500 {
1501 .start_resource = 15,
1502 .num_resource = 9,
1503 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1504 RESASG_SUBTYPE_RA_UDMAP_TX),
1505 .host_id = HOST_ID_A72_2,
1506 },
1507 {
1508 .start_resource = 24,
1509 .num_resource = 4,
1510 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1511 RESASG_SUBTYPE_RA_UDMAP_TX),
1512 .host_id = HOST_ID_A72_3,
1513 },
1514 {
1515 .start_resource = 28,
1516 .num_resource = 4,
1517 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1518 RESASG_SUBTYPE_RA_UDMAP_TX),
1519 .host_id = HOST_ID_MCU_0_R5_0,
1520 },
1521 {
1522 .start_resource = 28,
1523 .num_resource = 4,
1524 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1525 RESASG_SUBTYPE_RA_UDMAP_TX),
1526 .host_id = HOST_ID_MCU_0_R5_1,
1527 },
1528 {
1326 .start_resource = 32, 1529 .start_resource = 32,
1327 .num_resource = 14, 1530 .num_resource = 4,
1531 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1532 RESASG_SUBTYPE_RA_UDMAP_TX),
1533 .host_id = HOST_ID_MCU_0_R5_2,
1534 },
1535 {
1536 .start_resource = 36,
1537 .num_resource = 4,
1538 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1539 RESASG_SUBTYPE_RA_UDMAP_TX),
1540 .host_id = HOST_ID_MAIN_0_R5_0,
1541 },
1542 {
1543 .start_resource = 40,
1544 .num_resource = 4,
1545 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1546 RESASG_SUBTYPE_RA_UDMAP_TX),
1547 .host_id = HOST_ID_MAIN_0_R5_2,
1548 },
1549 {
1550 .start_resource = 44,
1551 .num_resource = 2,
1328 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1552 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1329 RESASG_SUBTYPE_RA_UDMAP_TX), 1553 RESASG_SUBTYPE_RA_UDMAP_TX),
1330 .host_id = HOST_ID_ALL, 1554 .host_id = HOST_ID_ALL,
1331 }, 1555 },
1332 /* MCU NAVSS Ringacc rings for High capacity Rx channels */ 1556 /* MCU NAVSS Rings for High capacity Rx channels */
1333 { 1557 {
1334 .start_resource = 48, 1558 .start_resource = 48,
1335 .num_resource = 2, 1559 .num_resource = 2,
@@ -1344,7 +1568,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1344 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1568 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1345 .host_id = HOST_ID_MCU_0_R5_1, 1569 .host_id = HOST_ID_MCU_0_R5_1,
1346 }, 1570 },
1347 /* MCU NAVSS Ringacc rings for High capacity Tx channels */ 1571 /* MCU NAVSS Rings for High capacity Tx channels */
1348 { 1572 {
1349 .start_resource = 0, 1573 .start_resource = 0,
1350 .num_resource = 2, 1574 .num_resource = 2,
@@ -1359,7 +1583,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1359 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1583 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1360 .host_id = HOST_ID_MCU_0_R5_1, 1584 .host_id = HOST_ID_MCU_0_R5_1,
1361 }, 1585 },
1362 /* MCU NAVSS Ringacc virt_id range */ 1586 /* MCU NAVSS Ring accelerator virt_id range */
1363 { 1587 {
1364 .start_resource = 2, 1588 .start_resource = 2,
1365 .num_resource = 1, 1589 .num_resource = 1,
@@ -1374,7 +1598,7 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1374 RESASG_SUBTYPE_RA_VIRTID), 1598 RESASG_SUBTYPE_RA_VIRTID),
1375 .host_id = HOST_ID_A72_3, 1599 .host_id = HOST_ID_A72_3,
1376 }, 1600 },
1377 /* MCU NAVSS Ringacc ring monitors */ 1601 /* MCU NAVSS Ring accelerator ring monitors */
1378 { 1602 {
1379 .start_resource = 0, 1603 .start_resource = 0,
1380 .num_resource = 3, 1604 .num_resource = 3,
@@ -1391,42 +1615,42 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1391 }, 1615 },
1392 { 1616 {
1393 .start_resource = 5, 1617 .start_resource = 5,
1394 .num_resource = 3, 1618 .num_resource = 6,
1395 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1619 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1396 RESASG_SUBTYPE_RA_MONITORS), 1620 RESASG_SUBTYPE_RA_MONITORS),
1397 .host_id = HOST_ID_MCU_0_R5_0, 1621 .host_id = HOST_ID_MCU_0_R5_0,
1398 }, 1622 },
1399 { 1623 {
1400 .start_resource = 5, 1624 .start_resource = 5,
1401 .num_resource = 3, 1625 .num_resource = 6,
1402 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1626 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1403 RESASG_SUBTYPE_RA_MONITORS), 1627 RESASG_SUBTYPE_RA_MONITORS),
1404 .host_id = HOST_ID_MCU_0_R5_1, 1628 .host_id = HOST_ID_MCU_0_R5_1,
1405 }, 1629 },
1406 { 1630 {
1407 .start_resource = 8, 1631 .start_resource = 11,
1408 .num_resource = 3, 1632 .num_resource = 6,
1409 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1633 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1410 RESASG_SUBTYPE_RA_MONITORS), 1634 RESASG_SUBTYPE_RA_MONITORS),
1411 .host_id = HOST_ID_MCU_0_R5_2, 1635 .host_id = HOST_ID_MCU_0_R5_2,
1412 }, 1636 },
1413 { 1637 {
1414 .start_resource = 11, 1638 .start_resource = 17,
1415 .num_resource = 3, 1639 .num_resource = 5,
1416 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1640 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1417 RESASG_SUBTYPE_RA_MONITORS), 1641 RESASG_SUBTYPE_RA_MONITORS),
1418 .host_id = HOST_ID_MAIN_0_R5_0, 1642 .host_id = HOST_ID_MAIN_0_R5_0,
1419 }, 1643 },
1420 { 1644 {
1421 .start_resource = 14, 1645 .start_resource = 22,
1422 .num_resource = 3, 1646 .num_resource = 5,
1423 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1647 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1424 RESASG_SUBTYPE_RA_MONITORS), 1648 RESASG_SUBTYPE_RA_MONITORS),
1425 .host_id = HOST_ID_MAIN_0_R5_2, 1649 .host_id = HOST_ID_MAIN_0_R5_2,
1426 }, 1650 },
1427 { 1651 {
1428 .start_resource = 17, 1652 .start_resource = 27,
1429 .num_resource = 15, 1653 .num_resource = 5,
1430 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1654 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1431 RESASG_SUBTYPE_RA_MONITORS), 1655 RESASG_SUBTYPE_RA_MONITORS),
1432 .host_id = HOST_ID_ALL, 1656 .host_id = HOST_ID_ALL,
@@ -1515,56 +1739,105 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1515 /* MCU NAVSS UDMA Normal capacity Rx channels */ 1739 /* MCU NAVSS UDMA Normal capacity Rx channels */
1516 { 1740 {
1517 .start_resource = 2, 1741 .start_resource = 2,
1518 .num_resource = 12, 1742 .num_resource = 3,
1519 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1743 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1520 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1744 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1521 .host_id = HOST_ID_A72_2, 1745 .host_id = HOST_ID_A72_2,
1522 }, 1746 },
1523 { 1747 {
1524 .start_resource = 14, 1748 .start_resource = 5,
1525 .num_resource = 6, 1749 .num_resource = 2,
1526 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1750 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1527 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1751 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1528 .host_id = HOST_ID_A72_3, 1752 .host_id = HOST_ID_A72_3,
1529 }, 1753 },
1530 { 1754 {
1531 .start_resource = 20, 1755 .start_resource = 7,
1532 .num_resource = 5, 1756 .num_resource = 2,
1533 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1757 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1534 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1758 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1535 .host_id = HOST_ID_MCU_0_R5_0, 1759 .host_id = HOST_ID_MCU_0_R5_0,
1536 }, 1760 },
1537 { 1761 {
1538 .start_resource = 20, 1762 .start_resource = 7,
1539 .num_resource = 5, 1763 .num_resource = 2,
1540 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1764 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1541 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1765 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1542 .host_id = HOST_ID_MCU_0_R5_1, 1766 .host_id = HOST_ID_MCU_0_R5_1,
1543 }, 1767 },
1544 { 1768 {
1545 .start_resource = 25, 1769 .start_resource = 9,
1546 .num_resource = 2, 1770 .num_resource = 2,
1547 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1771 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1548 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1772 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1549 .host_id = HOST_ID_MCU_0_R5_2, 1773 .host_id = HOST_ID_MCU_0_R5_2,
1550 }, 1774 },
1551 { 1775 {
1552 .start_resource = 27, 1776 .start_resource = 11,
1553 .num_resource = 3, 1777 .num_resource = 2,
1554 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1778 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1555 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1779 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1556 .host_id = HOST_ID_MAIN_0_R5_0, 1780 .host_id = HOST_ID_MAIN_0_R5_0,
1557 }, 1781 },
1558 { 1782 {
1559 .start_resource = 30, 1783 .start_resource = 13,
1560 .num_resource = 2, 1784 .num_resource = 2,
1561 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1785 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1562 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1786 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1563 .host_id = HOST_ID_MAIN_0_R5_2, 1787 .host_id = HOST_ID_MAIN_0_R5_2,
1564 }, 1788 },
1565 { 1789 {
1790 .start_resource = 15,
1791 .num_resource = 9,
1792 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1793 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1794 .host_id = HOST_ID_A72_2,
1795 },
1796 {
1797 .start_resource = 24,
1798 .num_resource = 4,
1799 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1800 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1801 .host_id = HOST_ID_A72_3,
1802 },
1803 {
1804 .start_resource = 28,
1805 .num_resource = 4,
1806 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1807 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1808 .host_id = HOST_ID_MCU_0_R5_0,
1809 },
1810 {
1811 .start_resource = 28,
1812 .num_resource = 4,
1813 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1814 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1815 .host_id = HOST_ID_MCU_0_R5_1,
1816 },
1817 {
1566 .start_resource = 32, 1818 .start_resource = 32,
1567 .num_resource = 13, 1819 .num_resource = 4,
1820 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1821 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1822 .host_id = HOST_ID_MCU_0_R5_2,
1823 },
1824 {
1825 .start_resource = 36,
1826 .num_resource = 4,
1827 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1828 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1829 .host_id = HOST_ID_MAIN_0_R5_0,
1830 },
1831 {
1832 .start_resource = 40,
1833 .num_resource = 4,
1834 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1835 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1836 .host_id = HOST_ID_MAIN_0_R5_2,
1837 },
1838 {
1839 .start_resource = 44,
1840 .num_resource = 1,
1568 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1841 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1569 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1842 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1570 .host_id = HOST_ID_ALL, 1843 .host_id = HOST_ID_ALL,
@@ -1587,56 +1860,105 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1587 /* MCU NAVSS UDMA Normal capacity Tx channels */ 1860 /* MCU NAVSS UDMA Normal capacity Tx channels */
1588 { 1861 {
1589 .start_resource = 2, 1862 .start_resource = 2,
1590 .num_resource = 12, 1863 .num_resource = 3,
1591 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1864 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1592 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1865 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1593 .host_id = HOST_ID_A72_2, 1866 .host_id = HOST_ID_A72_2,
1594 }, 1867 },
1595 { 1868 {
1596 .start_resource = 14, 1869 .start_resource = 5,
1597 .num_resource = 6, 1870 .num_resource = 2,
1598 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1871 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1599 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1872 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1600 .host_id = HOST_ID_A72_3, 1873 .host_id = HOST_ID_A72_3,
1601 }, 1874 },
1602 { 1875 {
1603 .start_resource = 20, 1876 .start_resource = 7,
1604 .num_resource = 5, 1877 .num_resource = 2,
1605 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1878 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1606 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1879 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1607 .host_id = HOST_ID_MCU_0_R5_0, 1880 .host_id = HOST_ID_MCU_0_R5_0,
1608 }, 1881 },
1609 { 1882 {
1610 .start_resource = 20, 1883 .start_resource = 7,
1611 .num_resource = 5, 1884 .num_resource = 2,
1612 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1885 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1613 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1886 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1614 .host_id = HOST_ID_MCU_0_R5_1, 1887 .host_id = HOST_ID_MCU_0_R5_1,
1615 }, 1888 },
1616 { 1889 {
1617 .start_resource = 25, 1890 .start_resource = 9,
1618 .num_resource = 2, 1891 .num_resource = 2,
1619 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1892 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1620 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1893 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1621 .host_id = HOST_ID_MCU_0_R5_2, 1894 .host_id = HOST_ID_MCU_0_R5_2,
1622 }, 1895 },
1623 { 1896 {
1624 .start_resource = 27, 1897 .start_resource = 11,
1625 .num_resource = 3, 1898 .num_resource = 2,
1626 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1899 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1627 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1900 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1628 .host_id = HOST_ID_MAIN_0_R5_0, 1901 .host_id = HOST_ID_MAIN_0_R5_0,
1629 }, 1902 },
1630 { 1903 {
1631 .start_resource = 30, 1904 .start_resource = 13,
1632 .num_resource = 2, 1905 .num_resource = 2,
1633 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1906 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1634 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1907 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1635 .host_id = HOST_ID_MAIN_0_R5_2, 1908 .host_id = HOST_ID_MAIN_0_R5_2,
1636 }, 1909 },
1637 { 1910 {
1911 .start_resource = 15,
1912 .num_resource = 9,
1913 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1914 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1915 .host_id = HOST_ID_A72_2,
1916 },
1917 {
1918 .start_resource = 24,
1919 .num_resource = 4,
1920 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1921 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1922 .host_id = HOST_ID_A72_3,
1923 },
1924 {
1925 .start_resource = 28,
1926 .num_resource = 4,
1927 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1928 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1929 .host_id = HOST_ID_MCU_0_R5_0,
1930 },
1931 {
1932 .start_resource = 28,
1933 .num_resource = 4,
1934 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1935 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1936 .host_id = HOST_ID_MCU_0_R5_1,
1937 },
1938 {
1638 .start_resource = 32, 1939 .start_resource = 32,
1639 .num_resource = 14, 1940 .num_resource = 4,
1941 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1942 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1943 .host_id = HOST_ID_MCU_0_R5_2,
1944 },
1945 {
1946 .start_resource = 36,
1947 .num_resource = 4,
1948 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1949 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1950 .host_id = HOST_ID_MAIN_0_R5_0,
1951 },
1952 {
1953 .start_resource = 40,
1954 .num_resource = 4,
1955 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1956 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1957 .host_id = HOST_ID_MAIN_0_R5_2,
1958 },
1959 {
1960 .start_resource = 44,
1961 .num_resource = 2,
1640 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1962 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1641 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1963 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1642 .host_id = HOST_ID_ALL, 1964 .host_id = HOST_ID_ALL,
diff --git a/soc/j7200/evm/sysfw_img_cfg.h b/soc/j7200/evm/sysfw_img_cfg.h
index 82c3ad53e..7392fe41a 100644
--- a/soc/j7200/evm/sysfw_img_cfg.h
+++ b/soc/j7200/evm/sysfw_img_cfg.h
@@ -3,7 +3,7 @@
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * 5 *
6 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 215 40#define BOARDCFG_RM_RESASG_ENTRIES 261
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */
generated by cgit v1.2.3 (git 2.39.2)