aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorNikhil Devshatwar2020-10-19 10:41:08 -0500
committerDave Gerlach2020-10-19 11:25:42 -0500
commit529cba75e8e08084d011cc7ce73c618e1e18e069 (patch)
tree8dd52d63e57b8bf28fe03f769c454336fc01b8b8
parent6d85d589f1b1c0917bd42281f46ff74833bcf264 (diff)
downloadk3-image-gen-529cba75e8e08084d011cc7ce73c618e1e18e069.tar.gz
k3-image-gen-529cba75e8e08084d011cc7ce73c618e1e18e069.tar.xz
k3-image-gen-529cba75e8e08084d011cc7ce73c618e1e18e069.zip
soc: j7200: Update block copy allocation for UDMA channels
To use UDMA channels for block copy, the Tx and Rx channel number has to be the same. When UDMA channels are allocated with just a single range, sometimes it is not possible to allocate the ranges such that the channels can be used for block copy usecase. Fix this by allocating the channels in two ranges, first range for block copy and second range for other usage. When there are no channels for block copy, an entry with 0 count is added. This is to maintain consistency when querying SYSFW about the ranges allocated for a host. Also adjust the MCU NAVSS INTA/INTR allocation after the HSM re architecture Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rw-r--r--soc/j7200/evm/rm-cfg.c214
-rw-r--r--soc/j7200/evm/sysfw_img_cfg.h4
2 files changed, 193 insertions, 25 deletions
diff --git a/soc/j7200/evm/rm-cfg.c b/soc/j7200/evm/rm-cfg.c
index 3fe2ff777..fd0ff414c 100644
--- a/soc/j7200/evm/rm-cfg.c
+++ b/soc/j7200/evm/rm-cfg.c
@@ -2,7 +2,7 @@
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -699,12 +699,26 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
699 /* Main NAVSS Rings for High capacity Rx channels */ 699 /* Main NAVSS Rings for High capacity Rx channels */
700 { 700 {
701 .start_resource = 62, 701 .start_resource = 62,
702 .num_resource = 0,
703 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
704 RESASG_SUBTYPE_RA_UDMAP_RX_H),
705 .host_id = HOST_ID_A72_2,
706 },
707 {
708 .start_resource = 62,
702 .num_resource = 1, 709 .num_resource = 1,
703 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 710 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
704 RESASG_SUBTYPE_RA_UDMAP_RX_H), 711 RESASG_SUBTYPE_RA_UDMAP_RX_H),
705 .host_id = HOST_ID_A72_2, 712 .host_id = HOST_ID_A72_2,
706 }, 713 },
707 { 714 {
715 .start_resource = 62,
716 .num_resource = 0,
717 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
718 RESASG_SUBTYPE_RA_UDMAP_RX_H),
719 .host_id = HOST_ID_MAIN_0_R5_0,
720 },
721 {
708 .start_resource = 63, 722 .start_resource = 63,
709 .num_resource = 1, 723 .num_resource = 1,
710 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 724 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -714,6 +728,13 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
714 /* Main NAVSS Rings for Ultra high capacity Rx channels */ 728 /* Main NAVSS Rings for Ultra high capacity Rx channels */
715 { 729 {
716 .start_resource = 60, 730 .start_resource = 60,
731 .num_resource = 0,
732 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
733 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
734 .host_id = HOST_ID_MAIN_0_R5_2,
735 },
736 {
737 .start_resource = 60,
717 .num_resource = 2, 738 .num_resource = 2,
718 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 739 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
719 RESASG_SUBTYPE_RA_UDMAP_RX_UH), 740 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
@@ -722,12 +743,26 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
722 /* Main NAVSS Rings for High capacity Tx channels */ 743 /* Main NAVSS Rings for High capacity Tx channels */
723 { 744 {
724 .start_resource = 2, 745 .start_resource = 2,
746 .num_resource = 0,
747 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
748 RESASG_SUBTYPE_RA_UDMAP_TX_H),
749 .host_id = HOST_ID_A72_2,
750 },
751 {
752 .start_resource = 2,
725 .num_resource = 1, 753 .num_resource = 1,
726 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 754 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
727 RESASG_SUBTYPE_RA_UDMAP_TX_H), 755 RESASG_SUBTYPE_RA_UDMAP_TX_H),
728 .host_id = HOST_ID_A72_2, 756 .host_id = HOST_ID_A72_2,
729 }, 757 },
730 { 758 {
759 .start_resource = 2,
760 .num_resource = 0,
761 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
762 RESASG_SUBTYPE_RA_UDMAP_TX_H),
763 .host_id = HOST_ID_MAIN_0_R5_0,
764 },
765 {
731 .start_resource = 3, 766 .start_resource = 3,
732 .num_resource = 1, 767 .num_resource = 1,
733 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 768 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -737,6 +772,13 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
737 /* Main NAVSS Rings for Ultra high capacity Tx channels */ 772 /* Main NAVSS Rings for Ultra high capacity Tx channels */
738 { 773 {
739 .start_resource = 0, 774 .start_resource = 0,
775 .num_resource = 0,
776 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
777 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
778 .host_id = HOST_ID_MAIN_0_R5_2,
779 },
780 {
781 .start_resource = 0,
740 .num_resource = 2, 782 .num_resource = 2,
741 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 783 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
742 RESASG_SUBTYPE_RA_UDMAP_TX_UH), 784 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
@@ -955,12 +997,26 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
955 /* Main NAVSS UDMA High capacity Rx channels */ 997 /* Main NAVSS UDMA High capacity Rx channels */
956 { 998 {
957 .start_resource = 2, 999 .start_resource = 2,
1000 .num_resource = 0,
1001 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1002 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1003 .host_id = HOST_ID_A72_2,
1004 },
1005 {
1006 .start_resource = 2,
958 .num_resource = 1, 1007 .num_resource = 1,
959 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1008 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
960 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1009 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
961 .host_id = HOST_ID_A72_2, 1010 .host_id = HOST_ID_A72_2,
962 }, 1011 },
963 { 1012 {
1013 .start_resource = 2,
1014 .num_resource = 0,
1015 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1016 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1017 .host_id = HOST_ID_MAIN_0_R5_0,
1018 },
1019 {
964 .start_resource = 3, 1020 .start_resource = 3,
965 .num_resource = 1, 1021 .num_resource = 1,
966 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1022 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
@@ -970,6 +1026,13 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
970 /* Main NAVSS UDMA Ultra high capacity Rx channels */ 1026 /* Main NAVSS UDMA Ultra high capacity Rx channels */
971 { 1027 {
972 .start_resource = 0, 1028 .start_resource = 0,
1029 .num_resource = 0,
1030 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1031 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
1032 .host_id = HOST_ID_MAIN_0_R5_2,
1033 },
1034 {
1035 .start_resource = 0,
973 .num_resource = 2, 1036 .num_resource = 2,
974 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1037 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
975 RESASG_SUBTYPE_UDMAP_RX_UHCHAN), 1038 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
@@ -1063,12 +1126,26 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1063 /* Main NAVSS UDMA High capacity Tx channels */ 1126 /* Main NAVSS UDMA High capacity Tx channels */
1064 { 1127 {
1065 .start_resource = 2, 1128 .start_resource = 2,
1129 .num_resource = 0,
1130 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1131 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1132 .host_id = HOST_ID_A72_2,
1133 },
1134 {
1135 .start_resource = 2,
1066 .num_resource = 1, 1136 .num_resource = 1,
1067 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1137 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1068 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 1138 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1069 .host_id = HOST_ID_A72_2, 1139 .host_id = HOST_ID_A72_2,
1070 }, 1140 },
1071 { 1141 {
1142 .start_resource = 2,
1143 .num_resource = 0,
1144 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1145 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1146 .host_id = HOST_ID_MAIN_0_R5_0,
1147 },
1148 {
1072 .start_resource = 3, 1149 .start_resource = 3,
1073 .num_resource = 1, 1150 .num_resource = 1,
1074 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1151 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
@@ -1078,6 +1155,13 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1078 /* Main NAVSS UDMA Ultra high capacity Tx channels */ 1155 /* Main NAVSS UDMA Ultra high capacity Tx channels */
1079 { 1156 {
1080 .start_resource = 0, 1157 .start_resource = 0,
1158 .num_resource = 0,
1159 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1160 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
1161 .host_id = HOST_ID_MAIN_0_R5_2,
1162 },
1163 {
1164 .start_resource = 0,
1081 .num_resource = 2, 1165 .num_resource = 2,
1082 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1166 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1083 RESASG_SUBTYPE_UDMAP_TX_UHCHAN), 1167 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
@@ -1135,114 +1219,114 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1135 }, 1219 },
1136 /* MCU NAVSS Interrupt aggregator Virtual interrupts */ 1220 /* MCU NAVSS Interrupt aggregator Virtual interrupts */
1137 { 1221 {
1138 .start_resource = 8, 1222 .start_resource = 15,
1139 .num_resource = 32, 1223 .num_resource = 32,
1140 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1224 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1141 RESASG_SUBTYPE_IA_VINT), 1225 RESASG_SUBTYPE_IA_VINT),
1142 .host_id = HOST_ID_A72_2, 1226 .host_id = HOST_ID_A72_2,
1143 }, 1227 },
1144 { 1228 {
1145 .start_resource = 40, 1229 .start_resource = 47,
1146 .num_resource = 16, 1230 .num_resource = 16,
1147 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1231 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1148 RESASG_SUBTYPE_IA_VINT), 1232 RESASG_SUBTYPE_IA_VINT),
1149 .host_id = HOST_ID_A72_3, 1233 .host_id = HOST_ID_A72_3,
1150 }, 1234 },
1151 { 1235 {
1152 .start_resource = 56, 1236 .start_resource = 63,
1153 .num_resource = 64, 1237 .num_resource = 64,
1154 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1238 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1155 RESASG_SUBTYPE_IA_VINT), 1239 RESASG_SUBTYPE_IA_VINT),
1156 .host_id = HOST_ID_MCU_0_R5_0, 1240 .host_id = HOST_ID_MCU_0_R5_0,
1157 }, 1241 },
1158 { 1242 {
1159 .start_resource = 56, 1243 .start_resource = 63,
1160 .num_resource = 64, 1244 .num_resource = 64,
1161 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1245 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1162 RESASG_SUBTYPE_IA_VINT), 1246 RESASG_SUBTYPE_IA_VINT),
1163 .host_id = HOST_ID_MCU_0_R5_1, 1247 .host_id = HOST_ID_MCU_0_R5_1,
1164 }, 1248 },
1165 { 1249 {
1166 .start_resource = 120, 1250 .start_resource = 127,
1167 .num_resource = 32, 1251 .num_resource = 32,
1168 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1252 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1169 RESASG_SUBTYPE_IA_VINT), 1253 RESASG_SUBTYPE_IA_VINT),
1170 .host_id = HOST_ID_MCU_0_R5_2, 1254 .host_id = HOST_ID_MCU_0_R5_2,
1171 }, 1255 },
1172 { 1256 {
1173 .start_resource = 152, 1257 .start_resource = 159,
1174 .num_resource = 16, 1258 .num_resource = 16,
1175 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1259 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1176 RESASG_SUBTYPE_IA_VINT), 1260 RESASG_SUBTYPE_IA_VINT),
1177 .host_id = HOST_ID_MAIN_0_R5_0, 1261 .host_id = HOST_ID_MAIN_0_R5_0,
1178 }, 1262 },
1179 { 1263 {
1180 .start_resource = 168, 1264 .start_resource = 175,
1181 .num_resource = 16, 1265 .num_resource = 16,
1182 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1266 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1183 RESASG_SUBTYPE_IA_VINT), 1267 RESASG_SUBTYPE_IA_VINT),
1184 .host_id = HOST_ID_MAIN_0_R5_2, 1268 .host_id = HOST_ID_MAIN_0_R5_2,
1185 }, 1269 },
1186 { 1270 {
1187 .start_resource = 184, 1271 .start_resource = 191,
1188 .num_resource = 72, 1272 .num_resource = 65,
1189 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1273 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1190 RESASG_SUBTYPE_IA_VINT), 1274 RESASG_SUBTYPE_IA_VINT),
1191 .host_id = HOST_ID_ALL, 1275 .host_id = HOST_ID_ALL,
1192 }, 1276 },
1193 /* MCU NAVSS Interrupt aggregator Global events */ 1277 /* MCU NAVSS Interrupt aggregator Global events */
1194 { 1278 {
1195 .start_resource = 16392, 1279 .start_resource = 16399,
1196 .num_resource = 128, 1280 .num_resource = 128,
1197 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1281 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1198 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1282 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1199 .host_id = HOST_ID_A72_2, 1283 .host_id = HOST_ID_A72_2,
1200 }, 1284 },
1201 { 1285 {
1202 .start_resource = 16520, 1286 .start_resource = 16527,
1203 .num_resource = 128, 1287 .num_resource = 128,
1204 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1288 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1205 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1289 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1206 .host_id = HOST_ID_A72_3, 1290 .host_id = HOST_ID_A72_3,
1207 }, 1291 },
1208 { 1292 {
1209 .start_resource = 16648, 1293 .start_resource = 16655,
1210 .num_resource = 256, 1294 .num_resource = 256,
1211 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1295 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1212 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1296 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1213 .host_id = HOST_ID_MCU_0_R5_0, 1297 .host_id = HOST_ID_MCU_0_R5_0,
1214 }, 1298 },
1215 { 1299 {
1216 .start_resource = 16648, 1300 .start_resource = 16655,
1217 .num_resource = 256, 1301 .num_resource = 256,
1218 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1302 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1219 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1303 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1220 .host_id = HOST_ID_MCU_0_R5_1, 1304 .host_id = HOST_ID_MCU_0_R5_1,
1221 }, 1305 },
1222 { 1306 {
1223 .start_resource = 16904, 1307 .start_resource = 16911,
1224 .num_resource = 128, 1308 .num_resource = 128,
1225 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1309 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1226 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1310 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1227 .host_id = HOST_ID_MCU_0_R5_2, 1311 .host_id = HOST_ID_MCU_0_R5_2,
1228 }, 1312 },
1229 { 1313 {
1230 .start_resource = 17032, 1314 .start_resource = 17039,
1231 .num_resource = 128, 1315 .num_resource = 128,
1232 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1316 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1233 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1317 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1234 .host_id = HOST_ID_MAIN_0_R5_0, 1318 .host_id = HOST_ID_MAIN_0_R5_0,
1235 }, 1319 },
1236 { 1320 {
1237 .start_resource = 17160, 1321 .start_resource = 17167,
1238 .num_resource = 128, 1322 .num_resource = 128,
1239 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1323 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1240 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1324 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1241 .host_id = HOST_ID_MAIN_0_R5_2, 1325 .host_id = HOST_ID_MAIN_0_R5_2,
1242 }, 1326 },
1243 { 1327 {
1244 .start_resource = 17288, 1328 .start_resource = 17295,
1245 .num_resource = 632, 1329 .num_resource = 625,
1246 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1330 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1247 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1331 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1248 .host_id = HOST_ID_ALL, 1332 .host_id = HOST_ID_ALL,
@@ -1584,6 +1668,27 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1584 /* MCU NAVSS Rings for High capacity Rx channels */ 1668 /* MCU NAVSS Rings for High capacity Rx channels */
1585 { 1669 {
1586 .start_resource = 48, 1670 .start_resource = 48,
1671 .num_resource = 0,
1672 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1673 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1674 .host_id = HOST_ID_MCU_0_R5_0,
1675 },
1676 {
1677 .start_resource = 48,
1678 .num_resource = 0,
1679 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1680 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1681 .host_id = HOST_ID_MCU_0_R5_1,
1682 },
1683 {
1684 .start_resource = 48,
1685 .num_resource = 0,
1686 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1687 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1688 .host_id = HOST_ID_A72_2,
1689 },
1690 {
1691 .start_resource = 48,
1587 .num_resource = 1, 1692 .num_resource = 1,
1588 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1693 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1589 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1694 RESASG_SUBTYPE_RA_UDMAP_RX_H),
@@ -1606,6 +1711,27 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1606 /* MCU NAVSS Rings for High capacity Tx channels */ 1711 /* MCU NAVSS Rings for High capacity Tx channels */
1607 { 1712 {
1608 .start_resource = 0, 1713 .start_resource = 0,
1714 .num_resource = 0,
1715 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1716 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1717 .host_id = HOST_ID_MCU_0_R5_0,
1718 },
1719 {
1720 .start_resource = 0,
1721 .num_resource = 0,
1722 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1723 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1724 .host_id = HOST_ID_MCU_0_R5_1,
1725 },
1726 {
1727 .start_resource = 0,
1728 .num_resource = 0,
1729 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1730 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1731 .host_id = HOST_ID_A72_2,
1732 },
1733 {
1734 .start_resource = 0,
1609 .num_resource = 1, 1735 .num_resource = 1,
1610 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1736 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1611 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1737 RESASG_SUBTYPE_RA_UDMAP_TX_H),
@@ -1887,6 +2013,27 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1887 /* MCU NAVSS UDMA High capacity Rx channels */ 2013 /* MCU NAVSS UDMA High capacity Rx channels */
1888 { 2014 {
1889 .start_resource = 0, 2015 .start_resource = 0,
2016 .num_resource = 0,
2017 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2018 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2019 .host_id = HOST_ID_MCU_0_R5_0,
2020 },
2021 {
2022 .start_resource = 0,
2023 .num_resource = 0,
2024 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2025 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2026 .host_id = HOST_ID_MCU_0_R5_1,
2027 },
2028 {
2029 .start_resource = 0,
2030 .num_resource = 0,
2031 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2032 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2033 .host_id = HOST_ID_A72_2,
2034 },
2035 {
2036 .start_resource = 0,
1890 .num_resource = 1, 2037 .num_resource = 1,
1891 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 2038 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1892 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 2039 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
@@ -2015,6 +2162,27 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2015 /* MCU NAVSS UDMA High capacity Tx channels */ 2162 /* MCU NAVSS UDMA High capacity Tx channels */
2016 { 2163 {
2017 .start_resource = 0, 2164 .start_resource = 0,
2165 .num_resource = 0,
2166 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2167 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2168 .host_id = HOST_ID_MCU_0_R5_0,
2169 },
2170 {
2171 .start_resource = 0,
2172 .num_resource = 0,
2173 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2174 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2175 .host_id = HOST_ID_MCU_0_R5_1,
2176 },
2177 {
2178 .start_resource = 0,
2179 .num_resource = 0,
2180 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2181 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2182 .host_id = HOST_ID_A72_2,
2183 },
2184 {
2185 .start_resource = 0,
2018 .num_resource = 1, 2186 .num_resource = 1,
2019 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 2187 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2020 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 2188 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
@@ -2036,15 +2204,15 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2036 }, 2204 },
2037 /* MCU NAVSS Interrupt router */ 2205 /* MCU NAVSS Interrupt router */
2038 { 2206 {
2039 .start_resource = 4, 2207 .start_resource = 11,
2040 .num_resource = 28, 2208 .num_resource = 20,
2041 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0, 2209 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
2042 RESASG_SUBTYPE_IR_OUTPUT), 2210 RESASG_SUBTYPE_IR_OUTPUT),
2043 .host_id = HOST_ID_MCU_0_R5_0, 2211 .host_id = HOST_ID_MCU_0_R5_0,
2044 }, 2212 },
2045 { 2213 {
2046 .start_resource = 4, 2214 .start_resource = 11,
2047 .num_resource = 28, 2215 .num_resource = 20,
2048 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0, 2216 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
2049 RESASG_SUBTYPE_IR_OUTPUT), 2217 RESASG_SUBTYPE_IR_OUTPUT),
2050 .host_id = HOST_ID_MCU_0_R5_1, 2218 .host_id = HOST_ID_MCU_0_R5_1,
diff --git a/soc/j7200/evm/sysfw_img_cfg.h b/soc/j7200/evm/sysfw_img_cfg.h
index c206c2653..87a6d8bc2 100644
--- a/soc/j7200/evm/sysfw_img_cfg.h
+++ b/soc/j7200/evm/sysfw_img_cfg.h
@@ -3,7 +3,7 @@
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * 5 *
6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 269 40#define BOARDCFG_RM_RESASG_ENTRIES 293
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */