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authorDave Gerlach2020-09-28 23:57:05 -0500
committerDave Gerlach2020-12-14 12:27:50 -0600
commit02197201493794935cf564ab1b424b7a9145df06 (patch)
tree5e59e4103fc9a75496947d5d02d0e7100cdcbb1a
parent11a1ec133dab0f7c86551300b406a680156bfc55 (diff)
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k3-image-gen-02197201493794935cf564ab1b424b7a9145df06.tar.xz
k3-image-gen-02197201493794935cf564ab1b424b7a9145df06.zip
soc: am64x: Introduce support for evm
Add support for AM64x SoCs. Base the baseport, PM, and security boardcfg off of other platforms and use generated RM config provided by the sysconfig tool. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
-rw-r--r--include/soc/am64x/devices.h193
-rw-r--r--include/soc/am64x/hosts.h78
-rw-r--r--include/soc/am64x/resasg_types.h157
-rw-r--r--soc/am64x/Makefile37
-rw-r--r--soc/am64x/evm/board-cfg.c92
-rw-r--r--soc/am64x/evm/pm-cfg.c43
-rw-r--r--soc/am64x/evm/rm-cfg.c1451
-rw-r--r--soc/am64x/evm/sec-cfg.c115
-rw-r--r--soc/am64x/evm/sysfw_img_cfg.h42
9 files changed, 2208 insertions, 0 deletions
diff --git a/include/soc/am64x/devices.h b/include/soc/am64x/devices.h
new file mode 100644
index 0000000..06690e5
--- /dev/null
+++ b/include/soc/am64x/devices.h
@@ -0,0 +1,193 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SOC_AM64X_DEVICES_H
36#define SOC_AM64X_DEVICES_H
37
38#define AM64X_DEV_ADC0 0
39#define AM64X_DEV_CMP_EVENT_INTROUTER0 1
40#define AM64X_DEV_DBGSUSPENDROUTER0 2
41#define AM64X_DEV_MAIN_GPIOMUX_INTROUTER0 3
42#define AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5
43#define AM64X_DEV_TIMESYNC_EVENT_INTROUTER0 6
44#define AM64X_DEV_MCU_M4FSS0 7
45#define AM64X_DEV_MCU_M4FSS0_CORE0 9
46#define AM64X_DEV_CPSW0 13
47#define AM64X_DEV_CPT2_AGGR0 14
48#define AM64X_DEV_STM0 15
49#define AM64X_DEV_DCC0 16
50#define AM64X_DEV_DCC1 17
51#define AM64X_DEV_DCC2 18
52#define AM64X_DEV_DCC3 19
53#define AM64X_DEV_DCC4 20
54#define AM64X_DEV_DCC5 21
55#define AM64X_DEV_DMSC0 22
56#define AM64X_DEV_MCU_DCC0 23
57#define AM64X_DEV_DEBUGSS_WRAP0 24
58#define AM64X_DEV_DMASS0 25
59#define AM64X_DEV_DMASS0_BCDMA_0 26
60#define AM64X_DEV_DMASS0_CBASS_0 27
61#define AM64X_DEV_DMASS0_INTAGGR_0 28
62#define AM64X_DEV_DMASS0_IPCSS_0 29
63#define AM64X_DEV_DMASS0_PKTDMA_0 30
64#define AM64X_DEV_DMASS0_PSILCFG_0 31
65#define AM64X_DEV_DMASS0_PSILSS_0 32
66#define AM64X_DEV_DMASS0_RINGACC_0 33
67#define AM64X_DEV_MCU_TIMER0 35
68#define AM64X_DEV_TIMER0 36
69#define AM64X_DEV_TIMER1 37
70#define AM64X_DEV_TIMER2 38
71#define AM64X_DEV_TIMER3 39
72#define AM64X_DEV_TIMER4 40
73#define AM64X_DEV_TIMER5 41
74#define AM64X_DEV_TIMER6 42
75#define AM64X_DEV_TIMER7 43
76#define AM64X_DEV_TIMER8 44
77#define AM64X_DEV_TIMER9 45
78#define AM64X_DEV_TIMER10 46
79#define AM64X_DEV_TIMER11 47
80#define AM64X_DEV_MCU_TIMER1 48
81#define AM64X_DEV_MCU_TIMER2 49
82#define AM64X_DEV_MCU_TIMER3 50
83#define AM64X_DEV_ECAP0 51
84#define AM64X_DEV_ECAP1 52
85#define AM64X_DEV_ECAP2 53
86#define AM64X_DEV_ELM0 54
87#define AM64X_DEV_EMIF_DATA_0_VD 55
88#define AM64X_DEV_MMCSD0 57
89#define AM64X_DEV_MMCSD1 58
90#define AM64X_DEV_EQEP0 59
91#define AM64X_DEV_EQEP1 60
92#define AM64X_DEV_GTC0 61
93#define AM64X_DEV_EQEP2 62
94#define AM64X_DEV_ESM0 63
95#define AM64X_DEV_MCU_ESM0 64
96#define AM64X_DEV_FSIRX0 65
97#define AM64X_DEV_FSIRX1 66
98#define AM64X_DEV_FSIRX2 67
99#define AM64X_DEV_FSIRX3 68
100#define AM64X_DEV_FSIRX4 69
101#define AM64X_DEV_FSIRX5 70
102#define AM64X_DEV_FSITX0 71
103#define AM64X_DEV_FSITX1 72
104#define AM64X_DEV_FSS0 73
105#define AM64X_DEV_FSS0_FSAS_0 74
106#define AM64X_DEV_FSS0_OSPI_0 75
107#define AM64X_DEV_GICSS0 76
108#define AM64X_DEV_GPIO0 77
109#define AM64X_DEV_GPIO1 78
110#define AM64X_DEV_MCU_GPIO0 79
111#define AM64X_DEV_GPMC0 80
112#define AM64X_DEV_PRU_ICSSG0 81
113#define AM64X_DEV_PRU_ICSSG1 82
114#define AM64X_DEV_LED0 83
115#define AM64X_DEV_CPTS0 84
116#define AM64X_DEV_DDPA0 85
117#define AM64X_DEV_EPWM0 86
118#define AM64X_DEV_EPWM1 87
119#define AM64X_DEV_EPWM2 88
120#define AM64X_DEV_EPWM3 89
121#define AM64X_DEV_EPWM4 90
122#define AM64X_DEV_EPWM5 91
123#define AM64X_DEV_EPWM6 92
124#define AM64X_DEV_EPWM7 93
125#define AM64X_DEV_EPWM8 94
126#define AM64X_DEV_VTM0 95
127#define AM64X_DEV_MAILBOX0 96
128#define AM64X_DEV_MAIN2MCU_VD 97
129#define AM64X_DEV_MCAN0 98
130#define AM64X_DEV_MCAN1 99
131#define AM64X_DEV_MCU_MCRC64_0 100
132#define AM64X_DEV_MCU2MAIN_VD 101
133#define AM64X_DEV_I2C0 102
134#define AM64X_DEV_I2C1 103
135#define AM64X_DEV_I2C2 104
136#define AM64X_DEV_I2C3 105
137#define AM64X_DEV_MCU_I2C0 106
138#define AM64X_DEV_MCU_I2C1 107
139#define AM64X_DEV_MSRAM_256K0 108
140#define AM64X_DEV_MSRAM_256K1 109
141#define AM64X_DEV_MSRAM_256K2 110
142#define AM64X_DEV_MSRAM_256K3 111
143#define AM64X_DEV_MSRAM_256K4 112
144#define AM64X_DEV_MSRAM_256K5 113
145#define AM64X_DEV_PCIE0 114
146#define AM64X_DEV_POSTDIV1_16FFT1 115
147#define AM64X_DEV_POSTDIV4_16FF0 116
148#define AM64X_DEV_POSTDIV4_16FF2 117
149#define AM64X_DEV_PSRAMECC0 118
150#define AM64X_DEV_R5FSS0 119
151#define AM64X_DEV_R5FSS1 120
152#define AM64X_DEV_R5FSS0_CORE0 121
153#define AM64X_DEV_R5FSS0_CORE1 122
154#define AM64X_DEV_R5FSS1_CORE0 123
155#define AM64X_DEV_R5FSS1_CORE1 124
156#define AM64X_DEV_RTI0 125
157#define AM64X_DEV_RTI1 126
158#define AM64X_DEV_RTI8 127
159#define AM64X_DEV_RTI9 128
160#define AM64X_DEV_RTI10 130
161#define AM64X_DEV_RTI11 131
162#define AM64X_DEV_MCU_RTI0 132
163#define AM64X_DEV_SA2_UL0 133
164#define AM64X_DEV_COMPUTE_CLUSTER0 134
165#define AM64X_DEV_A53SS0_CORE_0 135
166#define AM64X_DEV_A53SS0_CORE_1 136
167#define AM64X_DEV_A53SS0 137
168#define AM64X_DEV_DDR16SS0 138
169#define AM64X_DEV_PSC0 139
170#define AM64X_DEV_MCU_PSC0 140
171#define AM64X_DEV_MCSPI0 141
172#define AM64X_DEV_MCSPI1 142
173#define AM64X_DEV_MCSPI2 143
174#define AM64X_DEV_MCSPI3 144
175#define AM64X_DEV_MCSPI4 145
176#define AM64X_DEV_UART0 146
177#define AM64X_DEV_MCU_MCSPI0 147
178#define AM64X_DEV_MCU_MCSPI1 148
179#define AM64X_DEV_MCU_UART0 149
180#define AM64X_DEV_SPINLOCK0 150
181#define AM64X_DEV_TIMERMGR0 151
182#define AM64X_DEV_UART1 152
183#define AM64X_DEV_UART2 153
184#define AM64X_DEV_UART3 154
185#define AM64X_DEV_UART4 155
186#define AM64X_DEV_UART5 156
187#define AM64X_DEV_BOARD0 157
188#define AM64X_DEV_UART6 158
189#define AM64X_DEV_MCU_UART1 160
190#define AM64X_DEV_USB0 161
191#define AM64X_DEV_SERDES_10G0 162
192
193#endif /* SOC_AM64X_DEVICES_H */
diff --git a/include/soc/am64x/hosts.h b/include/soc/am64x/hosts.h
new file mode 100644
index 0000000..446d834
--- /dev/null
+++ b/include/soc/am64x/hosts.h
@@ -0,0 +1,78 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef AM64X_HOSTS_H
36#define AM64X_HOSTS_H
37
38/** DMSC(Secure): Device Management and Security Control */
39#define HOST_ID_DMSC (0U)
40/** MAIN_0_R5_0(Secure): Cortex R5_0 context 0 on Main island(BOOT) */
41#define HOST_ID_MAIN_0_R5_0 (35U)
42/** MAIN_0_R5_1(Non Secure): Cortex R5_0 context 1 on Main island */
43#define HOST_ID_MAIN_0_R5_1 (36U)
44/** MAIN_0_R5_2(Secure): Cortex R5_0 context 2 on Main island */
45#define HOST_ID_MAIN_0_R5_2 (37U)
46/** MAIN_0_R5_3(Non Secure): Cortex R5_0 context 3 on Main island */
47#define HOST_ID_MAIN_0_R5_3 (38U)
48/** A53_0(Secure): Cortex a53 context 0 on Main islana - ATF */
49#define HOST_ID_A53_0 (10U)
50/** A53_1(Non Secure): Cortex A72 context 1 on Main island - EL2/Hyp */
51#define HOST_ID_A53_1 (11U)
52/** A53_2(Non Secure): Cortex A53 context 2 on Main island - VM/OS1 */
53#define HOST_ID_A53_2 (12U)
54/** A53_3(Non Secure): Cortex A53 context 3 on Main island - VM2/OS2 */
55#define HOST_ID_A53_3 (13U)
56/** M4_0(Non Secure): M4 */
57#define HOST_ID_M4_0 (30U)
58/** MAIN_1_R5_0(Secure): Cortex R5_1 context 0 on Main island */
59#define HOST_ID_MAIN_1_R5_0 (40U)
60/** MAIN_1_R5_1(Non Secure): Cortex R5_1 context 1 on Main island */
61#define HOST_ID_MAIN_1_R5_1 (41U)
62/** MAIN_1_R5_2(Secure): Cortex R5_1 context 2 on Main island */
63#define HOST_ID_MAIN_1_R5_2 (42U)
64/** MAIN_1_R5_3(Non Secure): Cortex R5_1 context 3 on Main island */
65#define HOST_ID_MAIN_1_R5_3 (43U)
66/** ICSSG_0(Non Secure): ICSSG context 0 on Main island */
67#define HOST_ID_ICSSG_0 (50U)
68
69/**
70 * Host catch all. Used in board configuration resource assignments to define
71 * resource ranges useable by all hosts. Cannot be used
72 */
73#define HOST_ID_ALL (128U)
74
75/** Number of unique hosts on the SoC */
76#define HOST_ID_CNT (15U)
77
78#endif /* AM64X_HOSTS_H */
diff --git a/include/soc/am64x/resasg_types.h b/include/soc/am64x/resasg_types.h
new file mode 100644
index 0000000..f5ec123
--- /dev/null
+++ b/include/soc/am64x/resasg_types.h
@@ -0,0 +1,157 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef RESASG_TYPES_H
36#define RESASG_TYPES_H
37
38/**
39 * Resource assignment type shift
40 */
41#define RESASG_TYPE_SHIFT (0x0006U)
42/**
43 * Resource assignment type mask
44 */
45#define RESASG_TYPE_MASK (0xFFC0U)
46/**
47 * Resource assignment subtype shift
48 */
49#define RESASG_SUBTYPE_SHIFT (0x0000U)
50/**
51 * Resource assignment subtype mask
52 */
53#define RESASG_SUBTYPE_MASK (0x003FU)
54/**
55 * Macro to create unique resource assignment types using type and subtype
56 */
57
58#define RESASG_UTYPE(type, subtype) \
59 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) |\
60 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
61
62/**
63 * IA subtypes definitions
64 */
65#define RESASG_SUBTYPE_IA_VINT (0x000AU)
66#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
67#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
68#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
69#define RESASG_SUBTYPE_GLOBAL_EVENT_LEVT (0x000EU)
70#define RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES (0x000FU)
71#define RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES (0x0010U)
72#define RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES (0x0011U)
73#define RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES (0x0012U)
74#define RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES (0x0013U)
75#define RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES (0x0014U)
76#define RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES (0x0015U)
77#define RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES (0x0016U)
78#define RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES (0x0017U)
79#define RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES (0x0018U)
80#define RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES (0x0019U)
81#define RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES (0x001AU)
82#define RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES (0x001BU)
83#define RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES (0x001CU)
84#define RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES (0x001DU)
85#define RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES (0x001EU)
86#define RESASG_SUBTYPES_IA_CNT (0x0015U)
87
88/**
89 * IR subtypes definitions
90 */
91#define RESASG_SUBTYPE_IR_OUTPUT (0x0000U)
92#define RESASG_SUBTYPES_IR_CNT (0x0001U)
93
94/**
95 * RA subtypes definitions
96 */
97#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
98#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
99#define RESASG_SUBTYPE_RA_GENERIC_IPC (0x000CU)
100#define RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN (0x000DU)
101#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN (0x000EU)
102#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN (0x000FU)
103#define RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN (0x0010U)
104#define RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN (0x0011U)
105#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN (0x0012U)
106#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN (0x0013U)
107#define RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN (0x0014U)
108#define RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN (0x0015U)
109#define RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN (0x0016U)
110#define RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN (0x0017U)
111#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN (0x0018U)
112#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN (0x0019U)
113#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN (0x001AU)
114#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN (0x001BU)
115#define RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN (0x001CU)
116#define RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN (0x001DU)
117#define RESASG_SUBTYPES_RA_CNT (0x0014U)
118
119/**
120 * UDMAP subtypes definitions
121 */
122#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
123#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
124#define RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN (0x0020U)
125#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN (0x0021U)
126#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN (0x0022U)
127#define RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN (0x0023U)
128#define RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN (0x0024U)
129#define RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN (0x0025U)
130#define RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN (0x0026U)
131#define RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN (0x0027U)
132#define RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN (0x0028U)
133#define RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN (0x0029U)
134#define RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN (0x002AU)
135#define RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN (0x002BU)
136#define RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN (0x002CU)
137#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN (0x002DU)
138#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN (0x002EU)
139#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN (0x002FU)
140#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN (0x0030U)
141#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN (0x0031U)
142#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN (0x0032U)
143#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN (0x0033U)
144#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN (0x0034U)
145#define RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN (0x0035U)
146#define RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN (0x0036U)
147#define RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN (0x0037U)
148#define RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN (0x0038U)
149#define RESASG_SUBTYPES_UDMAP_CNT (0x001BU)
150
151
152/**
153 * Total number of unique resource types for SoC
154 */
155#define RESASG_UTYPE_CNT 72U
156
157#endif /* RESASG_TYPES_H */
diff --git a/soc/am64x/Makefile b/soc/am64x/Makefile
new file mode 100644
index 0000000..43bcad8
--- /dev/null
+++ b/soc/am64x/Makefile
@@ -0,0 +1,37 @@
1#
2# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions
6# are met:
7#
8# Redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer.
10#
11# Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the
14# distribution.
15#
16# Neither the name of Texas Instruments Incorporated nor the names of
17# its contributors may be used to endorse or promote products derived
18# from this software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31#
32
33LOADADDR ?= 0x44000
34SCIFS = sci
35
36.PHONY: all
37all: _objtree_build $(ITB) sysfw.itb
diff --git a/soc/am64x/evm/board-cfg.c b/soc/am64x/evm/board-cfg.c
new file mode 100644
index 0000000..fa46212
--- /dev/null
+++ b/soc/am64x/evm/board-cfg.c
@@ -0,0 +1,92 @@
1/*
2 * K3 System Firmware Board Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg am64x_boardcfg_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_control */
45 .control = {
46 .subhdr = {
47 .magic = BOARDCFG_CONTROL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_control),
49 },
50 .main_isolation_enable = 0x5A,
51 .main_isolation_hostid = 0x2,
52 },
53
54 /* boardcfg sec_proxy */
55 .secproxy = {
56 .subhdr = {
57 .magic = BOARDCFG_SECPROXY_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_secproxy),
59 },
60 .scaling_factor = 0x1,
61 .scaling_profile = 0x1,
62 .disable_main_nav_secure_proxy = 0,
63 },
64
65 /* boardcfg_msmc */
66 .msmc = {
67 .subhdr = {
68 .magic = BOARDCFG_MSMC_MAGIC_NUM,
69 .size = sizeof(struct boardcfg_msmc),
70 },
71 .msmc_cache_size = 0x0,
72 },
73
74 /* boardcfg_dbg_cfg */
75 .debug_cfg = {
76 .subhdr = {
77 .magic = BOARDCFG_DBG_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dbg_cfg),
79 },
80#ifdef ENABLE_TRACE
81 .trace_dst_enables = BOARDCFG_TRACE_DST_UART0 |
82 BOARDCFG_TRACE_DST_ITM |
83 BOARDCFG_TRACE_DST_MEM,
84 .trace_src_enables = BOARDCFG_TRACE_SRC_PM |
85 BOARDCFG_TRACE_SRC_RM |
86 BOARDCFG_TRACE_SRC_SEC |
87 BOARDCFG_TRACE_SRC_BASE |
88 BOARDCFG_TRACE_SRC_USER |
89 BOARDCFG_TRACE_SRC_SUPR,
90#endif
91 },
92};
diff --git a/soc/am64x/evm/pm-cfg.c b/soc/am64x/evm/pm-cfg.c
new file mode 100644
index 0000000..7c6e156
--- /dev/null
+++ b/soc/am64x/evm/pm-cfg.c
@@ -0,0 +1,43 @@
1/*
2 * K3 System Firmware Power Management Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_pm am64x_boardcfg_pm_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43};
diff --git a/soc/am64x/evm/rm-cfg.c b/soc/am64x/evm/rm-cfg.c
new file mode 100644
index 0000000..5ca838f
--- /dev/null
+++ b/soc/am64x/evm/rm-cfg.c
@@ -0,0 +1,1451 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37#include <hosts.h>
38#include <devices.h>
39#include <resasg_types.h>
40
41const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
42 .rm_boardcfg = {
43 /* boardcfg_abi_rev */
44 .rev = {
45 .boardcfg_abi_maj = 0x0,
46 .boardcfg_abi_min = 0x1,
47 },
48
49 /* boardcfg_rm_host_cfg */
50 .host_cfg = {
51 .subhdr = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 },
55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_A53_2,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_M4_0,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_MAIN_0_R5_1,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 {
81 .host_id = HOST_ID_MAIN_0_R5_3,
82 .allowed_atype = 0b101010,
83 .allowed_qos = 0xAAAA,
84 .allowed_orderid = 0xAAAAAAAA,
85 .allowed_priority = 0xAAAA,
86 .allowed_sched_priority = 0xAA,
87 },
88 {
89 .host_id = HOST_ID_MAIN_1_R5_1,
90 .allowed_atype = 0b101010,
91 .allowed_qos = 0xAAAA,
92 .allowed_orderid = 0xAAAAAAAA,
93 .allowed_priority = 0xAAAA,
94 .allowed_sched_priority = 0xAA,
95 },
96 {
97 .host_id = HOST_ID_MAIN_1_R5_3,
98 .allowed_atype = 0b101010,
99 .allowed_qos = 0xAAAA,
100 .allowed_orderid = 0xAAAAAAAA,
101 .allowed_priority = 0xAAAA,
102 .allowed_sched_priority = 0xAA,
103 },
104 }
105 },
106
107 /* boardcfg_rm_resasg */
108 .resasg = {
109 .subhdr = {
110 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
111 .size = sizeof (struct boardcfg_rm_resasg),
112 },
113 .resasg_entries_size =
114 BOARDCFG_RM_RESASG_ENTRIES *
115 sizeof (struct boardcfg_rm_resasg_entry),
116 .reserved = 0,
117 /* .resasg_entries is set via boardcfg_rm_local */
118 },
119 },
120
121 /* This is actually part of .resasg */
122 .resasg_entries = {
123 /* Compare event Interrupt Router */
124 {
125 .start_resource = 0,
126 .num_resource = 16,
127 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
128 RESASG_SUBTYPE_IR_OUTPUT),
129 .host_id = HOST_ID_A53_2,
130 },
131 {
132 .start_resource = 16,
133 .num_resource = 4,
134 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
135 RESASG_SUBTYPE_IR_OUTPUT),
136 .host_id = HOST_ID_MAIN_0_R5_0,
137 },
138 {
139 .start_resource = 16,
140 .num_resource = 4,
141 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
142 RESASG_SUBTYPE_IR_OUTPUT),
143 .host_id = HOST_ID_MAIN_0_R5_1,
144 },
145 {
146 .start_resource = 20,
147 .num_resource = 4,
148 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
149 RESASG_SUBTYPE_IR_OUTPUT),
150 .host_id = HOST_ID_MAIN_0_R5_3,
151 },
152 {
153 .start_resource = 24,
154 .num_resource = 4,
155 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
156 RESASG_SUBTYPE_IR_OUTPUT),
157 .host_id = HOST_ID_MAIN_1_R5_1,
158 },
159 {
160 .start_resource = 28,
161 .num_resource = 4,
162 .type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
163 RESASG_SUBTYPE_IR_OUTPUT),
164 .host_id = HOST_ID_MAIN_1_R5_3,
165 },
166 /* Main GPIO Interrupt Router */
167 {
168 .start_resource = 0,
169 .num_resource = 8,
170 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
171 RESASG_SUBTYPE_IR_OUTPUT),
172 .host_id = HOST_ID_A53_2,
173 },
174 {
175 .start_resource = 8,
176 .num_resource = 2,
177 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
178 RESASG_SUBTYPE_IR_OUTPUT),
179 .host_id = HOST_ID_MAIN_0_R5_0,
180 },
181 {
182 .start_resource = 8,
183 .num_resource = 2,
184 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
185 RESASG_SUBTYPE_IR_OUTPUT),
186 .host_id = HOST_ID_MAIN_0_R5_1,
187 },
188 {
189 .start_resource = 10,
190 .num_resource = 2,
191 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
192 RESASG_SUBTYPE_IR_OUTPUT),
193 .host_id = HOST_ID_MAIN_0_R5_3,
194 },
195 {
196 .start_resource = 12,
197 .num_resource = 2,
198 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
199 RESASG_SUBTYPE_IR_OUTPUT),
200 .host_id = HOST_ID_MAIN_1_R5_1,
201 },
202 {
203 .start_resource = 14,
204 .num_resource = 2,
205 .type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
206 RESASG_SUBTYPE_IR_OUTPUT),
207 .host_id = HOST_ID_MAIN_1_R5_3,
208 },
209 /* MCU GPIO Interrupt Router */
210 {
211 .start_resource = 0,
212 .num_resource = 4,
213 .type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
214 RESASG_SUBTYPE_IR_OUTPUT),
215 .host_id = HOST_ID_A53_2,
216 },
217 {
218 .start_resource = 4,
219 .num_resource = 4,
220 .type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
221 RESASG_SUBTYPE_IR_OUTPUT),
222 .host_id = HOST_ID_M4_0,
223 },
224 /* Timesync Interrupt Router */
225 {
226 .start_resource = 0,
227 .num_resource = 41,
228 .type = RESASG_UTYPE (AM64X_DEV_TIMESYNC_EVENT_INTROUTER0,
229 RESASG_SUBTYPE_IR_OUTPUT),
230 .host_id = HOST_ID_ALL,
231 },
232 /* Block Copy DMA Global event trigger */
233 {
234 .start_resource = 50176,
235 .num_resource = 136,
236 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
237 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
238 .host_id = HOST_ID_ALL,
239 },
240 /* Block Copy DMA Global config */
241 {
242 .start_resource = 0,
243 .num_resource = 1,
244 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
245 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
246 .host_id = HOST_ID_ALL,
247 },
248 /* Block Copy DMA Rings for Block copy channels */
249 {
250 .start_resource = 0,
251 .num_resource = 12,
252 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
253 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
254 .host_id = HOST_ID_A53_2,
255 },
256 {
257 .start_resource = 12,
258 .num_resource = 6,
259 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
260 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
261 .host_id = HOST_ID_MAIN_0_R5_0,
262 },
263 {
264 .start_resource = 12,
265 .num_resource = 6,
266 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
267 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
268 .host_id = HOST_ID_MAIN_0_R5_1,
269 },
270 {
271 .start_resource = 18,
272 .num_resource = 2,
273 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
274 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
275 .host_id = HOST_ID_MAIN_0_R5_3,
276 },
277 {
278 .start_resource = 20,
279 .num_resource = 4,
280 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
281 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
282 .host_id = HOST_ID_MAIN_1_R5_1,
283 },
284 {
285 .start_resource = 24,
286 .num_resource = 2,
287 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
288 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
289 .host_id = HOST_ID_MAIN_1_R5_3,
290 },
291 {
292 .start_resource = 26,
293 .num_resource = 1,
294 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
295 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
296 .host_id = HOST_ID_M4_0,
297 },
298 {
299 .start_resource = 27,
300 .num_resource = 1,
301 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
302 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
303 .host_id = HOST_ID_ALL,
304 },
305 /* Block Copy DMA Rings for Split TR Rx channel */
306 {
307 .start_resource = 48,
308 .num_resource = 6,
309 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
310 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
311 .host_id = HOST_ID_A53_2,
312 },
313 {
314 .start_resource = 54,
315 .num_resource = 6,
316 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
317 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
318 .host_id = HOST_ID_MAIN_0_R5_0,
319 },
320 {
321 .start_resource = 54,
322 .num_resource = 6,
323 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
324 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
325 .host_id = HOST_ID_MAIN_0_R5_1,
326 },
327 {
328 .start_resource = 60,
329 .num_resource = 2,
330 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
331 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
332 .host_id = HOST_ID_MAIN_0_R5_3,
333 },
334 {
335 .start_resource = 62,
336 .num_resource = 4,
337 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
338 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
339 .host_id = HOST_ID_MAIN_1_R5_1,
340 },
341 {
342 .start_resource = 66,
343 .num_resource = 2,
344 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
345 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
346 .host_id = HOST_ID_MAIN_1_R5_3,
347 },
348 /* Block Copy DMA Rings for Split TR Tx channel */
349 {
350 .start_resource = 28,
351 .num_resource = 6,
352 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
353 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
354 .host_id = HOST_ID_A53_2,
355 },
356 {
357 .start_resource = 34,
358 .num_resource = 6,
359 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
360 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
361 .host_id = HOST_ID_MAIN_0_R5_0,
362 },
363 {
364 .start_resource = 34,
365 .num_resource = 6,
366 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
367 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
368 .host_id = HOST_ID_MAIN_0_R5_1,
369 },
370 {
371 .start_resource = 40,
372 .num_resource = 2,
373 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
374 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
375 .host_id = HOST_ID_MAIN_0_R5_3,
376 },
377 {
378 .start_resource = 42,
379 .num_resource = 4,
380 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
381 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
382 .host_id = HOST_ID_MAIN_1_R5_1,
383 },
384 {
385 .start_resource = 46,
386 .num_resource = 2,
387 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
388 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
389 .host_id = HOST_ID_MAIN_1_R5_3,
390 },
391 /* Block Copy DMA Block copy channels */
392 {
393 .start_resource = 0,
394 .num_resource = 12,
395 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
396 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
397 .host_id = HOST_ID_A53_2,
398 },
399 {
400 .start_resource = 12,
401 .num_resource = 6,
402 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
403 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
404 .host_id = HOST_ID_MAIN_0_R5_0,
405 },
406 {
407 .start_resource = 12,
408 .num_resource = 6,
409 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
410 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
411 .host_id = HOST_ID_MAIN_0_R5_1,
412 },
413 {
414 .start_resource = 18,
415 .num_resource = 2,
416 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
417 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
418 .host_id = HOST_ID_MAIN_0_R5_3,
419 },
420 {
421 .start_resource = 20,
422 .num_resource = 4,
423 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
424 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
425 .host_id = HOST_ID_MAIN_1_R5_1,
426 },
427 {
428 .start_resource = 24,
429 .num_resource = 2,
430 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
431 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
432 .host_id = HOST_ID_MAIN_1_R5_3,
433 },
434 {
435 .start_resource = 26,
436 .num_resource = 1,
437 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
438 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
439 .host_id = HOST_ID_M4_0,
440 },
441 {
442 .start_resource = 27,
443 .num_resource = 1,
444 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
445 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
446 .host_id = HOST_ID_ALL,
447 },
448 /* Block Copy DMA Split TR Rx channels */
449 {
450 .start_resource = 0,
451 .num_resource = 6,
452 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
453 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
454 .host_id = HOST_ID_A53_2,
455 },
456 {
457 .start_resource = 6,
458 .num_resource = 6,
459 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
460 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
461 .host_id = HOST_ID_MAIN_0_R5_0,
462 },
463 {
464 .start_resource = 6,
465 .num_resource = 6,
466 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
467 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
468 .host_id = HOST_ID_MAIN_0_R5_1,
469 },
470 {
471 .start_resource = 12,
472 .num_resource = 2,
473 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
474 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
475 .host_id = HOST_ID_MAIN_0_R5_3,
476 },
477 {
478 .start_resource = 14,
479 .num_resource = 4,
480 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
481 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
482 .host_id = HOST_ID_MAIN_1_R5_1,
483 },
484 {
485 .start_resource = 18,
486 .num_resource = 2,
487 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
488 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
489 .host_id = HOST_ID_MAIN_1_R5_3,
490 },
491 /* Block Copy DMA Split TR Tx channels */
492 {
493 .start_resource = 0,
494 .num_resource = 6,
495 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
496 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
497 .host_id = HOST_ID_A53_2,
498 },
499 {
500 .start_resource = 6,
501 .num_resource = 6,
502 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
503 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
504 .host_id = HOST_ID_MAIN_0_R5_0,
505 },
506 {
507 .start_resource = 6,
508 .num_resource = 6,
509 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
510 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
511 .host_id = HOST_ID_MAIN_0_R5_1,
512 },
513 {
514 .start_resource = 12,
515 .num_resource = 2,
516 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
517 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
518 .host_id = HOST_ID_MAIN_0_R5_3,
519 },
520 {
521 .start_resource = 14,
522 .num_resource = 4,
523 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
524 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
525 .host_id = HOST_ID_MAIN_1_R5_1,
526 },
527 {
528 .start_resource = 18,
529 .num_resource = 2,
530 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
531 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
532 .host_id = HOST_ID_MAIN_1_R5_3,
533 },
534 /* DMASS Interrupt aggregator Virtual interrupts */
535 {
536 .start_resource = 4,
537 .num_resource = 36,
538 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
539 RESASG_SUBTYPE_IA_VINT),
540 .host_id = HOST_ID_A53_2,
541 },
542 {
543 .start_resource = 44,
544 .num_resource = 14,
545 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
546 RESASG_SUBTYPE_IA_VINT),
547 .host_id = HOST_ID_MAIN_0_R5_0,
548 },
549 {
550 .start_resource = 44,
551 .num_resource = 14,
552 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
553 RESASG_SUBTYPE_IA_VINT),
554 .host_id = HOST_ID_MAIN_0_R5_1,
555 },
556 {
557 .start_resource = 58,
558 .num_resource = 14,
559 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
560 RESASG_SUBTYPE_IA_VINT),
561 .host_id = HOST_ID_MAIN_0_R5_3,
562 },
563 {
564 .start_resource = 92,
565 .num_resource = 14,
566 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
567 RESASG_SUBTYPE_IA_VINT),
568 .host_id = HOST_ID_MAIN_1_R5_1,
569 },
570 {
571 .start_resource = 106,
572 .num_resource = 14,
573 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
574 RESASG_SUBTYPE_IA_VINT),
575 .host_id = HOST_ID_MAIN_1_R5_3,
576 },
577 {
578 .start_resource = 168,
579 .num_resource = 16,
580 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
581 RESASG_SUBTYPE_IA_VINT),
582 .host_id = HOST_ID_M4_0,
583 },
584 /* DMASS Interrupt aggregator Global events */
585 {
586 .start_resource = 15,
587 .num_resource = 512,
588 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
589 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
590 .host_id = HOST_ID_A53_2,
591 },
592 {
593 .start_resource = 527,
594 .num_resource = 256,
595 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
596 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
597 .host_id = HOST_ID_MAIN_0_R5_0,
598 },
599 {
600 .start_resource = 527,
601 .num_resource = 256,
602 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
603 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
604 .host_id = HOST_ID_MAIN_0_R5_1,
605 },
606 {
607 .start_resource = 783,
608 .num_resource = 192,
609 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
610 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
611 .host_id = HOST_ID_MAIN_0_R5_3,
612 },
613 {
614 .start_resource = 975,
615 .num_resource = 256,
616 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
617 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
618 .host_id = HOST_ID_MAIN_1_R5_1,
619 },
620 {
621 .start_resource = 1231,
622 .num_resource = 192,
623 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
624 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
625 .host_id = HOST_ID_MAIN_1_R5_3,
626 },
627 {
628 .start_resource = 1423,
629 .num_resource = 96,
630 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
631 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
632 .host_id = HOST_ID_M4_0,
633 },
634 {
635 .start_resource = 1519,
636 .num_resource = 17,
637 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
638 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
639 .host_id = HOST_ID_ALL,
640 },
641 /* DMASS timer manager event */
642 {
643 .start_resource = 0,
644 .num_resource = 1024,
645 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
646 RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
647 .host_id = HOST_ID_ALL,
648 },
649 /* Packet DMA Tx channel error event */
650 {
651 .start_resource = 4096,
652 .num_resource = 42,
653 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
654 RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
655 .host_id = HOST_ID_ALL,
656 },
657 /* Packet DMA Tx flow completion event */
658 {
659 .start_resource = 4608,
660 .num_resource = 112,
661 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
662 RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
663 .host_id = HOST_ID_ALL,
664 },
665 /* Packet DMA Rx channel error event */
666 {
667 .start_resource = 5120,
668 .num_resource = 29,
669 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
670 RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
671 .host_id = HOST_ID_ALL,
672 },
673 /* Packet DMA Rx flow completion event */
674 {
675 .start_resource = 5632,
676 .num_resource = 176,
677 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
678 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
679 .host_id = HOST_ID_ALL,
680 },
681 /* Packet DMA Rx flow starvation event */
682 {
683 .start_resource = 6144,
684 .num_resource = 176,
685 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
686 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
687 .host_id = HOST_ID_ALL,
688 },
689 /* Packet DMA Rx flow firewall event */
690 {
691 .start_resource = 6656,
692 .num_resource = 176,
693 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
694 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
695 .host_id = HOST_ID_ALL,
696 },
697 /* Block copy DMA BC channel error event */
698 {
699 .start_resource = 8192,
700 .num_resource = 28,
701 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
702 RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
703 .host_id = HOST_ID_ALL,
704 },
705 /* Block copy DMA BC channel data completion event */
706 {
707 .start_resource = 8704,
708 .num_resource = 28,
709 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
710 RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
711 .host_id = HOST_ID_ALL,
712 },
713 /* Block copy DMA BC channel ring completion event */
714 {
715 .start_resource = 9216,
716 .num_resource = 28,
717 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
718 RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
719 .host_id = HOST_ID_ALL,
720 },
721 /* Block copy DMA Tx channel error event */
722 {
723 .start_resource = 9728,
724 .num_resource = 20,
725 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
726 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
727 .host_id = HOST_ID_ALL,
728 },
729 /* Block copy DMA Tx channel data completion event */
730 {
731 .start_resource = 10240,
732 .num_resource = 20,
733 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
734 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
735 .host_id = HOST_ID_ALL,
736 },
737 /* Block copy DMA Tx channel ring completion event */
738 {
739 .start_resource = 10752,
740 .num_resource = 20,
741 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
742 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
743 .host_id = HOST_ID_ALL,
744 },
745 /* Block copy DMA Rx channel error event */
746 {
747 .start_resource = 11264,
748 .num_resource = 20,
749 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
750 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
751 .host_id = HOST_ID_ALL,
752 },
753 /* Block copy DMA Rx channel data completion event */
754 {
755 .start_resource = 11776,
756 .num_resource = 20,
757 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
758 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
759 .host_id = HOST_ID_ALL,
760 },
761 /* Block copy DMA Rx channel ring completion event */
762 {
763 .start_resource = 12288,
764 .num_resource = 20,
765 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
766 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
767 .host_id = HOST_ID_ALL,
768 },
769 /* DMASS UDMA global config */
770 {
771 .start_resource = 0,
772 .num_resource = 1,
773 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
774 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
775 .host_id = HOST_ID_ALL,
776 },
777 /* Packet DMA Free rings for Tx channel */
778 {
779 .start_resource = 0,
780 .num_resource = 4,
781 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
782 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
783 .host_id = HOST_ID_A53_2,
784 },
785 {
786 .start_resource = 4,
787 .num_resource = 3,
788 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
789 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
790 .host_id = HOST_ID_MAIN_0_R5_0,
791 },
792 {
793 .start_resource = 4,
794 .num_resource = 3,
795 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
796 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
797 .host_id = HOST_ID_MAIN_0_R5_1,
798 },
799 {
800 .start_resource = 7,
801 .num_resource = 2,
802 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
803 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
804 .host_id = HOST_ID_MAIN_0_R5_3,
805 },
806 {
807 .start_resource = 9,
808 .num_resource = 4,
809 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
810 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
811 .host_id = HOST_ID_MAIN_1_R5_1,
812 },
813 {
814 .start_resource = 13,
815 .num_resource = 2,
816 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
817 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
818 .host_id = HOST_ID_MAIN_1_R5_3,
819 },
820 {
821 .start_resource = 15,
822 .num_resource = 1,
823 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
824 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
825 .host_id = HOST_ID_M4_0,
826 },
827 /* Packet DMA Rings for CPSW Tx channel */
828 {
829 .start_resource = 16,
830 .num_resource = 64,
831 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
832 RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
833 .host_id = HOST_ID_A53_2,
834 },
835 /* Packet DMA Rings for SA2UL Tx channel0 */
836 {
837 .start_resource = 81,
838 .num_resource = 7,
839 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
840 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
841 .host_id = HOST_ID_ALL,
842 },
843 /* Packet DMA Rings for SA2UL Tx channel1 */
844 {
845 .start_resource = 88,
846 .num_resource = 8,
847 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
848 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
849 .host_id = HOST_ID_A53_2,
850 },
851 /* Packet DMA Rings for ICSSG0 Tx channel */
852 {
853 .start_resource = 96,
854 .num_resource = 4,
855 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
856 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
857 .host_id = HOST_ID_A53_2,
858 },
859 {
860 .start_resource = 100,
861 .num_resource = 4,
862 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
863 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
864 .host_id = HOST_ID_MAIN_0_R5_0,
865 },
866 {
867 .start_resource = 100,
868 .num_resource = 4,
869 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
870 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
871 .host_id = HOST_ID_MAIN_0_R5_1,
872 },
873 /* Packet DMA Rings for ICSSG1 Tx channel */
874 {
875 .start_resource = 104,
876 .num_resource = 4,
877 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
878 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
879 .host_id = HOST_ID_A53_2,
880 },
881 {
882 .start_resource = 108,
883 .num_resource = 4,
884 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
885 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
886 .host_id = HOST_ID_MAIN_0_R5_0,
887 },
888 {
889 .start_resource = 108,
890 .num_resource = 4,
891 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
892 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
893 .host_id = HOST_ID_MAIN_0_R5_1,
894 },
895 /* Packet DMA Free rings for Rx channel */
896 {
897 .start_resource = 112,
898 .num_resource = 4,
899 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
900 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
901 .host_id = HOST_ID_A53_2,
902 },
903 {
904 .start_resource = 116,
905 .num_resource = 3,
906 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
907 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
908 .host_id = HOST_ID_MAIN_0_R5_0,
909 },
910 {
911 .start_resource = 116,
912 .num_resource = 3,
913 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
914 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
915 .host_id = HOST_ID_MAIN_0_R5_1,
916 },
917 {
918 .start_resource = 119,
919 .num_resource = 2,
920 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
921 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
922 .host_id = HOST_ID_MAIN_0_R5_3,
923 },
924 {
925 .start_resource = 121,
926 .num_resource = 4,
927 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
928 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
929 .host_id = HOST_ID_MAIN_1_R5_1,
930 },
931 {
932 .start_resource = 125,
933 .num_resource = 2,
934 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
935 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
936 .host_id = HOST_ID_MAIN_1_R5_3,
937 },
938 {
939 .start_resource = 127,
940 .num_resource = 1,
941 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
942 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
943 .host_id = HOST_ID_M4_0,
944 },
945 /* Packet DMA Rings for CPSW Rx channel */
946 {
947 .start_resource = 128,
948 .num_resource = 16,
949 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
950 RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
951 .host_id = HOST_ID_A53_2,
952 },
953 /* Packet DMA Rings for SA2UL Rx channel0 */
954 {
955 .start_resource = 145,
956 .num_resource = 7,
957 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
958 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
959 .host_id = HOST_ID_ALL,
960 },
961 /* Packet DMA Rings for SA2UL Rx channel1 */
962 {
963 .start_resource = 144,
964 .num_resource = 8,
965 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
966 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
967 .host_id = HOST_ID_ALL,
968 },
969 /* Packet DMA Rings for SA2UL Rx channel2 */
970 {
971 .start_resource = 152,
972 .num_resource = 8,
973 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
974 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
975 .host_id = HOST_ID_A53_2,
976 },
977 /* Packet DMA Rings for SA2UL Rx channel3 */
978 {
979 .start_resource = 152,
980 .num_resource = 8,
981 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
982 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
983 .host_id = HOST_ID_A53_2,
984 },
985 /* Packet DMA Rings for ICSSG0 Rx channel */
986 {
987 .start_resource = 160,
988 .num_resource = 32,
989 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
990 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
991 .host_id = HOST_ID_A53_2,
992 },
993 {
994 .start_resource = 192,
995 .num_resource = 32,
996 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
997 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
998 .host_id = HOST_ID_MAIN_0_R5_0,
999 },
1000 {
1001 .start_resource = 192,
1002 .num_resource = 32,
1003 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1004 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
1005 .host_id = HOST_ID_MAIN_0_R5_1,
1006 },
1007 /* Packet DMA Rings for ICSSG1 Rx channel */
1008 {
1009 .start_resource = 224,
1010 .num_resource = 32,
1011 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1012 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
1013 .host_id = HOST_ID_A53_2,
1014 },
1015 {
1016 .start_resource = 256,
1017 .num_resource = 32,
1018 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1019 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
1020 .host_id = HOST_ID_MAIN_0_R5_0,
1021 },
1022 {
1023 .start_resource = 256,
1024 .num_resource = 32,
1025 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1026 RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
1027 .host_id = HOST_ID_MAIN_0_R5_1,
1028 },
1029 /* Packet DMA Free Tx channels */
1030 {
1031 .start_resource = 0,
1032 .num_resource = 4,
1033 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1034 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1035 .host_id = HOST_ID_A53_2,
1036 },
1037 {
1038 .start_resource = 4,
1039 .num_resource = 3,
1040 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1041 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1042 .host_id = HOST_ID_MAIN_0_R5_0,
1043 },
1044 {
1045 .start_resource = 4,
1046 .num_resource = 3,
1047 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1048 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1049 .host_id = HOST_ID_MAIN_0_R5_1,
1050 },
1051 {
1052 .start_resource = 7,
1053 .num_resource = 2,
1054 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1055 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1056 .host_id = HOST_ID_MAIN_0_R5_3,
1057 },
1058 {
1059 .start_resource = 9,
1060 .num_resource = 4,
1061 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1062 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1063 .host_id = HOST_ID_MAIN_1_R5_1,
1064 },
1065 {
1066 .start_resource = 13,
1067 .num_resource = 2,
1068 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1069 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1070 .host_id = HOST_ID_MAIN_1_R5_3,
1071 },
1072 {
1073 .start_resource = 15,
1074 .num_resource = 1,
1075 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1076 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
1077 .host_id = HOST_ID_M4_0,
1078 },
1079 /* Packet DMA CPSW Tx channels */
1080 {
1081 .start_resource = 16,
1082 .num_resource = 8,
1083 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1084 RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
1085 .host_id = HOST_ID_A53_2,
1086 },
1087 /* Packet DMA SA2UL Tx channel1 */
1088 {
1089 .start_resource = 25,
1090 .num_resource = 1,
1091 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1092 RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
1093 .host_id = HOST_ID_A53_2,
1094 },
1095 /* Packet DMA ICSSG0 Tx channels */
1096 {
1097 .start_resource = 26,
1098 .num_resource = 4,
1099 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1100 RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
1101 .host_id = HOST_ID_A53_2,
1102 },
1103 {
1104 .start_resource = 30,
1105 .num_resource = 4,
1106 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1107 RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
1108 .host_id = HOST_ID_MAIN_0_R5_0,
1109 },
1110 {
1111 .start_resource = 30,
1112 .num_resource = 4,
1113 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1114 RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
1115 .host_id = HOST_ID_MAIN_0_R5_1,
1116 },
1117 /* Packet DMA ICSSG1 Tx channels */
1118 {
1119 .start_resource = 34,
1120 .num_resource = 4,
1121 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1122 RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
1123 .host_id = HOST_ID_A53_2,
1124 },
1125 {
1126 .start_resource = 38,
1127 .num_resource = 4,
1128 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1129 RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
1130 .host_id = HOST_ID_MAIN_0_R5_0,
1131 },
1132 {
1133 .start_resource = 38,
1134 .num_resource = 4,
1135 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1136 RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
1137 .host_id = HOST_ID_MAIN_0_R5_1,
1138 },
1139 /* Packet DMA Free Rx channels */
1140 {
1141 .start_resource = 0,
1142 .num_resource = 4,
1143 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1144 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1145 .host_id = HOST_ID_A53_2,
1146 },
1147 {
1148 .start_resource = 4,
1149 .num_resource = 3,
1150 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1151 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1152 .host_id = HOST_ID_MAIN_0_R5_0,
1153 },
1154 {
1155 .start_resource = 4,
1156 .num_resource = 3,
1157 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1158 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1159 .host_id = HOST_ID_MAIN_0_R5_1,
1160 },
1161 {
1162 .start_resource = 7,
1163 .num_resource = 2,
1164 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1165 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1166 .host_id = HOST_ID_MAIN_0_R5_3,
1167 },
1168 {
1169 .start_resource = 9,
1170 .num_resource = 4,
1171 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1172 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1173 .host_id = HOST_ID_MAIN_1_R5_1,
1174 },
1175 {
1176 .start_resource = 13,
1177 .num_resource = 2,
1178 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1179 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1180 .host_id = HOST_ID_MAIN_1_R5_3,
1181 },
1182 {
1183 .start_resource = 15,
1184 .num_resource = 1,
1185 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1186 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
1187 .host_id = HOST_ID_M4_0,
1188 },
1189 /* Packet DMA Free flows for Rx channels */
1190 {
1191 .start_resource = 0,
1192 .num_resource = 4,
1193 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1194 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1195 .host_id = HOST_ID_A53_2,
1196 },
1197 {
1198 .start_resource = 4,
1199 .num_resource = 3,
1200 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1201 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1202 .host_id = HOST_ID_MAIN_0_R5_0,
1203 },
1204 {
1205 .start_resource = 4,
1206 .num_resource = 3,
1207 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1208 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1209 .host_id = HOST_ID_MAIN_0_R5_1,
1210 },
1211 {
1212 .start_resource = 7,
1213 .num_resource = 2,
1214 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1215 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1216 .host_id = HOST_ID_MAIN_0_R5_3,
1217 },
1218 {
1219 .start_resource = 9,
1220 .num_resource = 4,
1221 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1222 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1223 .host_id = HOST_ID_MAIN_1_R5_1,
1224 },
1225 {
1226 .start_resource = 13,
1227 .num_resource = 2,
1228 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1229 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1230 .host_id = HOST_ID_MAIN_1_R5_3,
1231 },
1232 {
1233 .start_resource = 15,
1234 .num_resource = 1,
1235 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1236 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
1237 .host_id = HOST_ID_M4_0,
1238 },
1239 /* Packet DMA CPSW Rx channel */
1240 {
1241 .start_resource = 16,
1242 .num_resource = 1,
1243 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1244 RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
1245 .host_id = HOST_ID_A53_2,
1246 },
1247 /* Packet DMA CPSW Rx flows */
1248 {
1249 .start_resource = 16,
1250 .num_resource = 16,
1251 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1252 RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
1253 .host_id = HOST_ID_A53_2,
1254 },
1255 /* Packet DMA SA2UL Rx channel0 flows */
1256 {
1257 .start_resource = 32,
1258 .num_resource = 8,
1259 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1260 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
1261 .host_id = HOST_ID_ALL,
1262 },
1263 /* Packet DMA SA2UL Rx channel1 flows */
1264 {
1265 .start_resource = 32,
1266 .num_resource = 8,
1267 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1268 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
1269 .host_id = HOST_ID_ALL,
1270 },
1271 /* Packet DMA SA2UL Rx channel2 */
1272 {
1273 .start_resource = 19,
1274 .num_resource = 1,
1275 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1276 RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
1277 .host_id = HOST_ID_A53_2,
1278 },
1279 /* Packet DMA SA2UL Rx channel2 flows */
1280 {
1281 .start_resource = 40,
1282 .num_resource = 8,
1283 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1284 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
1285 .host_id = HOST_ID_A53_2,
1286 },
1287 /* Packet DMA SA2UL Rx channel3 */
1288 {
1289 .start_resource = 20,
1290 .num_resource = 1,
1291 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1292 RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
1293 .host_id = HOST_ID_A53_2,
1294 },
1295 /* Packet DMA SA2UL Rx channel3 flows */
1296 {
1297 .start_resource = 40,
1298 .num_resource = 8,
1299 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1300 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
1301 .host_id = HOST_ID_A53_2,
1302 },
1303 /* Packet DMA ICSSG0 Rx channel */
1304 {
1305 .start_resource = 21,
1306 .num_resource = 2,
1307 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1308 RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
1309 .host_id = HOST_ID_A53_2,
1310 },
1311 {
1312 .start_resource = 23,
1313 .num_resource = 2,
1314 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1315 RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
1316 .host_id = HOST_ID_MAIN_0_R5_0,
1317 },
1318 {
1319 .start_resource = 23,
1320 .num_resource = 2,
1321 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1322 RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
1323 .host_id = HOST_ID_MAIN_0_R5_1,
1324 },
1325 /* Packet DMA ICSSG0 Rx flows */
1326 {
1327 .start_resource = 48,
1328 .num_resource = 32,
1329 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1330 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
1331 .host_id = HOST_ID_A53_2,
1332 },
1333 {
1334 .start_resource = 80,
1335 .num_resource = 32,
1336 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1337 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
1338 .host_id = HOST_ID_MAIN_0_R5_0,
1339 },
1340 {
1341 .start_resource = 80,
1342 .num_resource = 32,
1343 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1344 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
1345 .host_id = HOST_ID_MAIN_0_R5_1,
1346 },
1347 /* Packet DMA ICSSG1 Rx channel */
1348 {
1349 .start_resource = 25,
1350 .num_resource = 2,
1351 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1352 RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
1353 .host_id = HOST_ID_A53_2,
1354 },
1355 {
1356 .start_resource = 27,
1357 .num_resource = 2,
1358 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1359 RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
1360 .host_id = HOST_ID_MAIN_0_R5_0,
1361 },
1362 {
1363 .start_resource = 27,
1364 .num_resource = 2,
1365 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1366 RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
1367 .host_id = HOST_ID_MAIN_0_R5_1,
1368 },
1369 /* Packet DMA ICSSG1 Rx flows */
1370 {
1371 .start_resource = 112,
1372 .num_resource = 32,
1373 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1374 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
1375 .host_id = HOST_ID_A53_2,
1376 },
1377 {
1378 .start_resource = 144,
1379 .num_resource = 32,
1380 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1381 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
1382 .host_id = HOST_ID_MAIN_0_R5_0,
1383 },
1384 {
1385 .start_resource = 144,
1386 .num_resource = 32,
1387 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
1388 RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
1389 .host_id = HOST_ID_MAIN_0_R5_1,
1390 },
1391 /* Packet DMA Ring accelerator error event */
1392 {
1393 .start_resource = 0,
1394 .num_resource = 1,
1395 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1396 RESASG_SUBTYPE_RA_ERROR_OES),
1397 .host_id = HOST_ID_ALL,
1398 },
1399 /* Packet DMA virt_id range */
1400 {
1401 .start_resource = 2,
1402 .num_resource = 2,
1403 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1404 RESASG_SUBTYPE_RA_VIRTID),
1405 .host_id = HOST_ID_A53_2,
1406 },
1407 /* Packet DMA Rings for IPC */
1408 {
1409 .start_resource = 20,
1410 .num_resource = 2,
1411 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1412 RESASG_SUBTYPE_RA_GENERIC_IPC),
1413 .host_id = HOST_ID_MAIN_0_R5_0,
1414 },
1415 {
1416 .start_resource = 20,
1417 .num_resource = 2,
1418 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1419 RESASG_SUBTYPE_RA_GENERIC_IPC),
1420 .host_id = HOST_ID_MAIN_0_R5_1,
1421 },
1422 {
1423 .start_resource = 22,
1424 .num_resource = 2,
1425 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1426 RESASG_SUBTYPE_RA_GENERIC_IPC),
1427 .host_id = HOST_ID_MAIN_0_R5_3,
1428 },
1429 {
1430 .start_resource = 24,
1431 .num_resource = 2,
1432 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1433 RESASG_SUBTYPE_RA_GENERIC_IPC),
1434 .host_id = HOST_ID_MAIN_1_R5_1,
1435 },
1436 {
1437 .start_resource = 26,
1438 .num_resource = 2,
1439 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1440 RESASG_SUBTYPE_RA_GENERIC_IPC),
1441 .host_id = HOST_ID_MAIN_1_R5_3,
1442 },
1443 {
1444 .start_resource = 28,
1445 .num_resource = 4,
1446 .type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
1447 RESASG_SUBTYPE_RA_GENERIC_IPC),
1448 .host_id = HOST_ID_ALL,
1449 },
1450 },
1451};
diff --git a/soc/am64x/evm/sec-cfg.c b/soc/am64x/evm/sec-cfg.c
new file mode 100644
index 0000000..f5abf07
--- /dev/null
+++ b/soc/am64x/evm/sec-cfg.c
@@ -0,0 +1,115 @@
1/*
2 * K3 System Firmware Security Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_security am64_boardcfg_security_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_proc_acl */
45 .processor_acl_list = {
46 .subhdr = {
47 .magic = BOARDCFG_PROC_ACL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_proc_acl),
49 },
50 .proc_acl_entries = {{ 0 } },
51 },
52
53 /* boardcfg_host_hierarchy */
54 .host_hierarchy = {
55 .subhdr = {
56 .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
57 .size = sizeof(struct boardcfg_host_hierarchy),
58 },
59 .host_hierarchy_entries = {{ 0 } },
60 },
61
62 /* OTP access configuration */
63 .otp_config = {
64 .subhdr = {
65 .magic = BOARDCFG_OTP_CFG_MAGIC_NUM,
66 .size = sizeof(struct boardcfg_extended_otp),
67 },
68 /* Host ID 0 is DMSC. This means no host has write access to OTP array */
69 .write_host_id = 0,
70 /* This is an array with 32 entries */
71 .otp_entry = {{ 0 } },
72 },
73
74 /* DKEK configuration */
75 .dkek_config = {
76 .subhdr = {
77 .magic = BOARDCFG_DKEK_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dkek),
79 },
80 .allowed_hosts = { HOST_ID_ALL, 0, 0, 0 },
81 .allow_dkek_export_tisci = 0x5A,
82 .rsvd = {0, 0, 0},
83 },
84
85 /* SA2UL configuration */
86 .sa2ul_cfg = {
87 .subhdr = {
88 .magic = BOARDCFG_SA2UL_CFG_MAGIC_NUM_RSVD,
89 .size = 0,
90 },
91 .rsvd = {0, 0, 0, 0},
92 },
93
94 /* Secure JTAG Unlock Configuration */
95 .sec_dbg_config = {
96 .subhdr = {
97 .magic = BOARDCFG_SEC_DBG_CTRL_MAGIC_NUM,
98 .size = sizeof(struct boardcfg_secure_debug_config),
99 },
100 .allow_jtag_unlock = 0x5A,
101 .allow_wildcard_unlock = 0x5A,
102 .min_cert_rev = 0x0,
103 .jtag_unlock_hosts = {0, 0, 0, 0},
104 },
105
106 .sec_handover_cfg = {
107 .subhdr = {
108 .magic = BOARDCFG_SEC_HANDOVER_CFG_MAGIC_NUM,
109 .size = sizeof(struct boardcfg_sec_handover),
110 },
111 .handover_msg_sender = 0,
112 .handover_to_host_id = 0,
113 .rsvd = {0,0,0,0},
114 },
115};
diff --git a/soc/am64x/evm/sysfw_img_cfg.h b/soc/am64x/evm/sysfw_img_cfg.h
new file mode 100644
index 0000000..f028ed6
--- /dev/null
+++ b/soc/am64x/evm/sysfw_img_cfg.h
@@ -0,0 +1,42 @@
1/*
2 * K3 System Firmware Resource Management Board Config Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 *
6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H
39
40#define BOARDCFG_RM_RESASG_ENTRIES 180
41
42#endif /* SYSFW_IMG_CFG_H */