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authorJai Luthra2023-01-11 07:09:49 -0600
committerVignesh Raghavendra2023-01-11 12:07:54 -0600
commit07aaa8ba3601c6f3c90ba90d0e898b6682c3f968 (patch)
treeb5b59adfabe67a032c7db714c3c708d8918b8b1b
parent7e550d7624b682f03b3155d08439d9e34bc01b15 (diff)
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soc: evm: am62ax: Allocate all DMASS1 chanscicd.dunfell.202301120721
DMASS1 is the dedicated DMA subsystem for CSI-RX (cameras), and A53 is the only user of CSI-RX on AM62a - so allocate all 6 channels to A53. This is also required due to a bug in CSI-RX SHIM IP, where chan0 acts as the default "dump" channel where frames not filtered by any other channel end up. We want to avoid using chan0 for customer usecases, and thus need all channels available for multi camera (4 channel) support. Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--soc/am62ax/evm/rm-cfg.c18
-rw-r--r--soc/am62ax/evm/sysfw_img_cfg.h4
-rw-r--r--soc/am62ax/evm/tifs-rm-cfg.c18
3 files changed, 6 insertions, 34 deletions
diff --git a/soc/am62ax/evm/rm-cfg.c b/soc/am62ax/evm/rm-cfg.c
index 73fe32b2f..4e88dd0d2 100644
--- a/soc/am62ax/evm/rm-cfg.c
+++ b/soc/am62ax/evm/rm-cfg.c
@@ -1014,33 +1014,19 @@ const struct boardcfg_rm_local am62a_boardcfg_rm_data = {
1014 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */ 1014 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */
1015 { 1015 {
1016 .start_resource = 0, 1016 .start_resource = 0,
1017 .num_resource = 4, 1017 .num_resource = 6,
1018 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0, 1018 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1019 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN), 1019 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
1020 .host_id = HOST_ID_A53_2, 1020 .host_id = HOST_ID_A53_2,
1021 }, 1021 },
1022 {
1023 .start_resource = 4,
1024 .num_resource = 2,
1025 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1026 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
1027 .host_id = HOST_ID_ALL,
1028 },
1029 /* Block Copy DMA DMASS1 Split TR Rx channel */ 1022 /* Block Copy DMA DMASS1 Split TR Rx channel */
1030 { 1023 {
1031 .start_resource = 0, 1024 .start_resource = 0,
1032 .num_resource = 4, 1025 .num_resource = 6,
1033 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0, 1026 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1034 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN), 1027 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
1035 .host_id = HOST_ID_A53_2, 1028 .host_id = HOST_ID_A53_2,
1036 }, 1029 },
1037 {
1038 .start_resource = 4,
1039 .num_resource = 2,
1040 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1041 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
1042 .host_id = HOST_ID_ALL,
1043 },
1044 /* DMASS1 Interrupt aggregator Virtual interrupts */ 1030 /* DMASS1 Interrupt aggregator Virtual interrupts */
1045 { 1031 {
1046 .start_resource = 0, 1032 .start_resource = 0,
diff --git a/soc/am62ax/evm/sysfw_img_cfg.h b/soc/am62ax/evm/sysfw_img_cfg.h
index bd1c7d7e0..580370f8f 100644
--- a/soc/am62ax/evm/sysfw_img_cfg.h
+++ b/soc/am62ax/evm/sysfw_img_cfg.h
@@ -37,7 +37,7 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 131 40#define BOARDCFG_RM_RESASG_ENTRIES 129
41#define BOARDCFG_TIFS_RM_RESASG_ENTRIES 111 41#define BOARDCFG_TIFS_RM_RESASG_ENTRIES 109
42 42
43#endif /* SYSFW_IMG_CFG_H */ 43#endif /* SYSFW_IMG_CFG_H */
diff --git a/soc/am62ax/evm/tifs-rm-cfg.c b/soc/am62ax/evm/tifs-rm-cfg.c
index d50f11080..171b16096 100644
--- a/soc/am62ax/evm/tifs-rm-cfg.c
+++ b/soc/am62ax/evm/tifs-rm-cfg.c
@@ -891,33 +891,19 @@ const struct boardcfg_tifs_rm_local am62a_boardcfg_rm_data = {
891 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */ 891 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */
892 { 892 {
893 .start_resource = 0, 893 .start_resource = 0,
894 .num_resource = 4, 894 .num_resource = 6,
895 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0, 895 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
896 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN), 896 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
897 .host_id = HOST_ID_A53_2, 897 .host_id = HOST_ID_A53_2,
898 }, 898 },
899 {
900 .start_resource = 4,
901 .num_resource = 2,
902 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
903 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
904 .host_id = HOST_ID_ALL,
905 },
906 /* Block Copy DMA DMASS1 Split TR Rx channel */ 899 /* Block Copy DMA DMASS1 Split TR Rx channel */
907 { 900 {
908 .start_resource = 0, 901 .start_resource = 0,
909 .num_resource = 4, 902 .num_resource = 6,
910 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0, 903 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
911 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN), 904 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
912 .host_id = HOST_ID_A53_2, 905 .host_id = HOST_ID_A53_2,
913 }, 906 },
914 {
915 .start_resource = 4,
916 .num_resource = 2,
917 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
918 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
919 .host_id = HOST_ID_ALL,
920 },
921 /* DMASS1 Interrupt aggregator Virtual interrupts */ 907 /* DMASS1 Interrupt aggregator Virtual interrupts */
922 { 908 {
923 .start_resource = 0, 909 .start_resource = 0,