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authorNeha Malcom Francis2022-05-09 03:43:52 -0500
committerVignesh Raghavendra2022-05-13 09:07:33 -0500
commit2206dfc77590b96846c47243c6986a5e7c06b738 (patch)
treea6316fadd4ba3fdd87e1d3d9d3b57d2b0f78d218
parent486006d067e925139e92fa776069f41c616f0197 (diff)
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include: j721s2: Update devices.h, hosts.h, resasg_types.h
Changes to RM data require syncing with include files. Updating files from system firmware for j721s2 to align with these changes. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--include/soc/j721s2/devices.h47
-rw-r--r--include/soc/j721s2/hosts.h4
-rw-r--r--include/soc/j721s2/resasg_types.h16
3 files changed, 21 insertions, 46 deletions
diff --git a/include/soc/j721s2/devices.h b/include/soc/j721s2/devices.h
index b3f0605b6..27d2f60ec 100644
--- a/include/soc/j721s2/devices.h
+++ b/include/soc/j721s2/devices.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Data version: 210712_144506 2 * Data version: 220323_094332
3 * 3 *
4 * Copyright (C) 2017-2022 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2017-2022 Texas Instruments Incorporated - http://www.ti.com/
5 * ALL RIGHTS RESERVED 5 * ALL RIGHTS RESERVED
@@ -141,16 +141,16 @@
141#define J721S2_DEV_J7AM_32_64_ATB_FUNNEL2 133 141#define J721S2_DEV_J7AM_32_64_ATB_FUNNEL2 133
142#define J721S2_DEV_AGGR_ATB0 134 142#define J721S2_DEV_AGGR_ATB0 134
143#define J721S2_DEV_J7AM_BOLT_PGD0 135 143#define J721S2_DEV_J7AM_BOLT_PGD0 135
144#define J721S2_DEV_J7AM_CSI_PSILSS0 136 144#define J721S2_DEV_CSI_PSILSS0 136
145#define J721S2_DEV_DEBUGSUSPENDRTR0 137 145#define J721S2_DEV_DEBUGSUSPENDRTR0 137
146#define J721S2_DEV_DDR0 138 146#define J721S2_DEV_DDR0 138
147#define J721S2_DEV_DDR1 139 147#define J721S2_DEV_DDR1 139
148#define J721S2_DEV_J7AM_DMPAC_VPAC_PSILSS0 140 148#define J721S2_DEV_DMPAC_VPAC_PSILSS0 140
149#define J721S2_DEV_J7AM_HWA_ATB_FUNNEL0 141 149#define J721S2_DEV_J7AM_HWA_ATB_FUNNEL0 141
150#define J721S2_DEV_J7AM_MAIN_16FF0 142 150#define J721S2_DEV_J7AM_MAIN_16FF0 142
151#define J721S2_DEV_PSC0 143 151#define J721S2_DEV_PSC0 143
152#define J721S2_DEV_J7AM_PULSAR_ATB_FUNNEL0 144 152#define J721S2_DEV_J7AM_PULSAR_ATB_FUNNEL0 144
153#define J721S2_DEV_J7AM_SA2_CPSW_PSILSS0 145 153#define J721S2_DEV_SA2_CPSW_PSILSS0 145
154#define J721S2_DEV_UART0 146 154#define J721S2_DEV_UART0 146
155#define J721S2_DEV_WKUP_J7AM_WAKEUP_16FF0 147 155#define J721S2_DEV_WKUP_J7AM_WAKEUP_16FF0 147
156#define J721S2_DEV_GPIOMUX_INTRTR0 148 156#define J721S2_DEV_GPIOMUX_INTRTR0 148
@@ -183,7 +183,7 @@
183#define J721S2_DEV_MCU_PBIST0 176 183#define J721S2_DEV_MCU_PBIST0 176
184#define J721S2_DEV_MCU_PBIST1 177 184#define J721S2_DEV_MCU_PBIST1 177
185#define J721S2_DEV_MCU_PBIST2 178 185#define J721S2_DEV_MCU_PBIST2 178
186#define J721S2_DEV_K3_VPU_WAVE521CL0 179 186#define J721S2_DEV_CODEC0 179
187#define J721S2_DEV_WKUP_VTM0 180 187#define J721S2_DEV_WKUP_VTM0 180
188#define J721S2_DEV_MAIN2WKUPMCU_VD 181 188#define J721S2_DEV_MAIN2WKUPMCU_VD 181
189#define J721S2_DEV_MCAN0 182 189#define J721S2_DEV_MCAN0 182
@@ -303,41 +303,6 @@
303#define J721S2_DEV_MCU_SA3_SS0_PKTDMA_0 301 303#define J721S2_DEV_MCU_SA3_SS0_PKTDMA_0 301
304#define J721S2_DEV_MCU_SA3_SS0_RINGACC_0 302 304#define J721S2_DEV_MCU_SA3_SS0_RINGACC_0 302
305#define J721S2_DEV_MCU_SA3_SS0_SA_UL_0 303 305#define J721S2_DEV_MCU_SA3_SS0_SA_UL_0 303
306#define J721S2_DEV_WKUP_SMS0_AESEIP38T_0 304
307#define J721S2_DEV_WKUP_TIFS0 305
308#define J721S2_DEV_WKUP_HSM0 306
309#define J721S2_DEV_WKUP_SMS0_CORTEX_M4F_SS_0 307
310#define J721S2_DEV_WKUP_SMS0_CORTEX_M4F_SS_1 308
311#define J721S2_DEV_WKUP_SMS0_CTI_0 309
312#define J721S2_DEV_WKUP_SMS0_CTI_1 310
313#define J721S2_DEV_WKUP_SMS0_DBG_AUTH_0 311
314#define J721S2_DEV_WKUP_SMS0_DMTIMER_0 312
315#define J721S2_DEV_WKUP_SMS0_DMTIMER_1 313
316#define J721S2_DEV_WKUP_SMS0_DMTIMER_2 314
317#define J721S2_DEV_WKUP_SMS0_DMTIMER_3 315
318#define J721S2_DEV_WKUP_SMS0_DWT_0 316
319#define J721S2_DEV_WKUP_SMS0_DWT_1 317
320#define J721S2_DEV_WKUP_SMS0_FBP_0 318
321#define J721S2_DEV_WKUP_SMS0_FBP_1 319
322#define J721S2_DEV_WKUP_SMS0_FWMGR_0 320
323#define J721S2_DEV_WKUP_SMS0_HSM_SRAM_0 321
324#define J721S2_DEV_WKUP_SMS0_HSM_SRAM_1 322
325#define J721S2_DEV_WKUP_SMS0_ITM_0 323
326#define J721S2_DEV_WKUP_SMS0_ITM_1 324
327#define J721S2_DEV_WKUP_SMS0_PWRCTRL_0 325
328#define J721S2_DEV_WKUP_SMS0_RAT_0 326
329#define J721S2_DEV_WKUP_SMS0_RAT_1 327
330#define J721S2_DEV_WKUP_SMS0_ROM_0 328
331#define J721S2_DEV_WKUP_SMS0_RTI_0 329
332#define J721S2_DEV_WKUP_SMS0_RTI_1 330
333#define J721S2_DEV_WKUP_SMS0_SCS_0 331
334#define J721S2_DEV_WKUP_SMS0_SCS_1 332
335#define J721S2_DEV_WKUP_SMS0_SEC_MGR_0 333
336#define J721S2_DEV_WKUP_SMS0_SECCTRL_0 334
337#define J721S2_DEV_WKUP_SMS0_TIFS_SRAM_0 335
338#define J721S2_DEV_WKUP_SMS0_TIFS_SRAM_1 336
339#define J721S2_DEV_WKUP_SMS0_WDTCTRL_0 337
340#define J721S2_DEV_WKUP_SMS0_WDTCTRL_1 338
341#define J721S2_DEV_MCSPI0 339 306#define J721S2_DEV_MCSPI0 339
342#define J721S2_DEV_MCSPI1 340 307#define J721S2_DEV_MCSPI1 340
343#define J721S2_DEV_MCSPI2 341 308#define J721S2_DEV_MCSPI2 341
@@ -372,5 +337,7 @@
372#define J721S2_DEV_FFI_MAIN_INFRA_CBASS_VD 370 337#define J721S2_DEV_FFI_MAIN_INFRA_CBASS_VD 370
373#define J721S2_DEV_FFI_MAIN_IP_CBASS_VD 371 338#define J721S2_DEV_FFI_MAIN_IP_CBASS_VD 371
374#define J721S2_DEV_FFI_MAIN_RC_CBASS_VD 372 339#define J721S2_DEV_FFI_MAIN_RC_CBASS_VD 372
340#define J721S2_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0 373
341#define J721S2_DEV_DMPAC0_UTC_0 374
375 342
376#endif /* SOC_J721S2_DEVICES_H */ 343#endif /* SOC_J721S2_DEVICES_H */
diff --git a/include/soc/j721s2/hosts.h b/include/soc/j721s2/hosts.h
index 321f04e38..8d9c06a12 100644
--- a/include/soc/j721s2/hosts.h
+++ b/include/soc/j721s2/hosts.h
@@ -3,9 +3,9 @@
3 * 3 *
4 * Host IDs for J721S2 device 4 * Host IDs for J721S2 device
5 * 5 *
6 * Data version: 210528_144358 6 * Data version: 220323_094332
7 * 7 *
8 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 8 * Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/
9 * ALL RIGHTS RESERVED 9 * ALL RIGHTS RESERVED
10 */ 10 */
11#ifndef J721S2_HOSTS_H 11#ifndef J721S2_HOSTS_H
diff --git a/include/soc/j721s2/resasg_types.h b/include/soc/j721s2/resasg_types.h
index fab8cdb70..ca6cb1f1b 100644
--- a/include/soc/j721s2/resasg_types.h
+++ b/include/soc/j721s2/resasg_types.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Resource Assignment Subtype definitions 4 * Resource Assignment Subtype definitions
5 * 5 *
6 * Data version: 210712_144506 6 * Data version: 220323_094332
7 * 7 *
8 * Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/ 8 * Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/
9 * ALL RIGHTS RESERVED 9 * ALL RIGHTS RESERVED
@@ -86,9 +86,12 @@
86#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN (0x000EU) 86#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN (0x000EU)
87#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN (0x000FU) 87#define RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN (0x000FU)
88#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN (0x0012U) 88#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN (0x0012U)
89#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN (0x0013U)
89#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN (0x0018U) 90#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN (0x0018U)
90#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN (0x0019U) 91#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN (0x0019U)
91#define RESASG_SUBTYPES_RA_CNT (0x0010U) 92#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN (0x001AU)
93#define RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN (0x001BU)
94#define RESASG_SUBTYPES_RA_CNT (0x0013U)
92 95
93/** 96/**
94 * UDMAP subtypes definitions 97 * UDMAP subtypes definitions
@@ -107,17 +110,22 @@
107#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN (0x0021U) 110#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN (0x0021U)
108#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN (0x0022U) 111#define RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN (0x0022U)
109#define RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN (0x0025U) 112#define RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN (0x0025U)
113#define RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN (0x0026U)
110#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN (0x002DU) 114#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN (0x002DU)
111#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN (0x002EU) 115#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN (0x002EU)
112#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN (0x002FU) 116#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN (0x002FU)
113#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN (0x0030U) 117#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN (0x0030U)
114#define RESASG_SUBTYPES_UDMAP_CNT (0x0012U) 118#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN (0x0031U)
119#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN (0x0032U)
120#define RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN (0x0033U)
121#define RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN (0x0034U)
122#define RESASG_SUBTYPES_UDMAP_CNT (0x0017U)
115 123
116 124
117/** 125/**
118 * Total number of unique resource types for SoC 126 * Total number of unique resource types for SoC
119 */ 127 */
120#define RESASG_UTYPE_CNT 90U 128#define RESASG_UTYPE_CNT 98U
121 129
122/** 130/**
123 * Total number of resource entries allowed for SoC 131 * Total number of resource entries allowed for SoC