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authorLokesh Vutla2020-08-11 16:33:02 -0500
committerDave Gerlach2020-08-14 12:11:07 -0500
commit5ab440cacdd0ae62da3c06c28965f2fb520da113 (patch)
treeabab7bf082bc9ba93a6ee25b55950153f899f7c8
parent339852e73d79d6f282ab6be690063116baa8b642 (diff)
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include: j7200: Add sysfw board config data definitions
Add the following board config data definitions for j7200: - Devices - hosts - RM assignment types Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rw-r--r--include/soc/j7200/devices.h280
-rw-r--r--include/soc/j7200/hosts.h76
-rw-r--r--include/soc/j7200/resasg_types.h124
3 files changed, 480 insertions, 0 deletions
diff --git a/include/soc/j7200/devices.h b/include/soc/j7200/devices.h
new file mode 100644
index 0000000..bf8e60e
--- /dev/null
+++ b/include/soc/j7200/devices.h
@@ -0,0 +1,280 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SOC_J7200_DEVICES_H
36#define SOC_J7200_DEVICES_H
37
38#define J7200_DEV_MCU_ADC0 0
39#define J7200_DEV_MCU_ADC1 1
40#define J7200_DEV_ATL0 2
41#define J7200_DEV_COMPUTE_CLUSTER0 3
42#define J7200_DEV_A72SS0 4
43#define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
44#define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6
45#define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7
46#define J7200_DEV_DDR0 8
47#define J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP 9
48#define J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 10
49#define J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 11
50#define J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP 12
51#define J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN 13
52#define J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14
53#define J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP 17
54#define J7200_DEV_MCU_CPSW0 18
55#define J7200_DEV_CPSW0 19
56#define J7200_DEV_CPT2_AGGR0 20
57#define J7200_DEV_CPT2_AGGR1 21
58#define J7200_DEV_WKUP_DMSC0 22
59#define J7200_DEV_CPT2_AGGR2 23
60#define J7200_DEV_MCU_CPT2_AGGR0 24
61#define J7200_DEV_CPT2_AGGR3 25
62#define J7200_DEV_CPSW_TX_RGMII0 26
63#define J7200_DEV_STM0 29
64#define J7200_DEV_DCC0 30
65#define J7200_DEV_DCC1 31
66#define J7200_DEV_DCC2 32
67#define J7200_DEV_DCC3 33
68#define J7200_DEV_DCC4 34
69#define J7200_DEV_MCU_TIMER0 35
70#define J7200_DEV_DCC5 36
71#define J7200_DEV_DCC6 37
72#define J7200_DEV_MAIN0 39
73#define J7200_DEV_WKUP_WAKEUP0 40
74#define J7200_DEV_MCU_DCC0 44
75#define J7200_DEV_MCU_DCC1 45
76#define J7200_DEV_MCU_DCC2 46
77#define J7200_DEV_TIMER0 49
78#define J7200_DEV_TIMER1 50
79#define J7200_DEV_TIMER2 51
80#define J7200_DEV_TIMER3 52
81#define J7200_DEV_TIMER4 53
82#define J7200_DEV_TIMER5 54
83#define J7200_DEV_TIMER6 55
84#define J7200_DEV_TIMER7 57
85#define J7200_DEV_TIMER8 58
86#define J7200_DEV_TIMER9 59
87#define J7200_DEV_TIMER10 60
88#define J7200_DEV_GTC0 61
89#define J7200_DEV_TIMER11 62
90#define J7200_DEV_TIMER12 63
91#define J7200_DEV_TIMER13 64
92#define J7200_DEV_TIMER14 65
93#define J7200_DEV_TIMER15 66
94#define J7200_DEV_TIMER16 67
95#define J7200_DEV_TIMER17 68
96#define J7200_DEV_TIMER18 69
97#define J7200_DEV_TIMER19 70
98#define J7200_DEV_MCU_TIMER1 71
99#define J7200_DEV_MCU_TIMER2 72
100#define J7200_DEV_MCU_TIMER3 73
101#define J7200_DEV_MCU_TIMER4 74
102#define J7200_DEV_MCU_TIMER5 75
103#define J7200_DEV_MCU_TIMER6 76
104#define J7200_DEV_MCU_TIMER7 77
105#define J7200_DEV_MCU_TIMER8 78
106#define J7200_DEV_MCU_TIMER9 79
107#define J7200_DEV_ECAP0 80
108#define J7200_DEV_ECAP1 81
109#define J7200_DEV_ECAP2 82
110#define J7200_DEV_EHRPWM0 83
111#define J7200_DEV_EHRPWM1 84
112#define J7200_DEV_EHRPWM2 85
113#define J7200_DEV_EHRPWM3 86
114#define J7200_DEV_EHRPWM4 87
115#define J7200_DEV_EHRPWM5 88
116#define J7200_DEV_ELM0 89
117#define J7200_DEV_EMIF_DATA_0_VD 90
118#define J7200_DEV_MMCSD0 91
119#define J7200_DEV_MMCSD1 92
120#define J7200_DEV_EQEP0 94
121#define J7200_DEV_EQEP1 95
122#define J7200_DEV_EQEP2 96
123#define J7200_DEV_ESM0 97
124#define J7200_DEV_MCU_ESM0 98
125#define J7200_DEV_WKUP_ESM0 99
126#define J7200_DEV_MCU_FSS0 100
127#define J7200_DEV_MCU_FSS0_FSAS_0 101
128#define J7200_DEV_MCU_FSS0_HYPERBUS1P0_0 102
129#define J7200_DEV_MCU_FSS0_OSPI_0 103
130#define J7200_DEV_MCU_FSS0_OSPI_1 104
131#define J7200_DEV_GPIO0 105
132#define J7200_DEV_GPIO2 107
133#define J7200_DEV_GPIO4 109
134#define J7200_DEV_GPIO6 111
135#define J7200_DEV_WKUP_GPIO0 113
136#define J7200_DEV_WKUP_GPIO1 114
137#define J7200_DEV_GPMC0 115
138#define J7200_DEV_I3C0 116
139#define J7200_DEV_MCU_I3C0 117
140#define J7200_DEV_MCU_I3C1 118
141#define J7200_DEV_CMPEVENT_INTRTR0 123
142#define J7200_DEV_LED0 127
143#define J7200_DEV_MAIN2MCU_LVL_INTRTR0 128
144#define J7200_DEV_MAIN2MCU_PLS_INTRTR0 130
145#define J7200_DEV_GPIOMUX_INTRTR0 131
146#define J7200_DEV_WKUP_PORZ_SYNC0 132
147#define J7200_DEV_PSC0 133
148#define J7200_DEV_TIMESYNC_INTRTR0 136
149#define J7200_DEV_WKUP_GPIOMUX_INTRTR0 137
150#define J7200_DEV_WKUP_PSC0 138
151#define J7200_DEV_PBIST0 139
152#define J7200_DEV_PBIST1 140
153#define J7200_DEV_PBIST2 141
154#define J7200_DEV_MCU_PBIST0 142
155#define J7200_DEV_MCU_PBIST1 143
156#define J7200_DEV_MCU_PBIST2 144
157#define J7200_DEV_WKUP_DDPA0 145
158#define J7200_DEV_UART0 146
159#define J7200_DEV_MCU_UART0 149
160#define J7200_DEV_MCAN14 150
161#define J7200_DEV_MCAN15 151
162#define J7200_DEV_MCAN16 152
163#define J7200_DEV_MCAN17 153
164#define J7200_DEV_WKUP_VTM0 154
165#define J7200_DEV_MAIN2WKUPMCU_VD 155
166#define J7200_DEV_MCAN0 156
167#define J7200_DEV_BOARD0 157
168#define J7200_DEV_MCAN1 158
169#define J7200_DEV_MCAN2 160
170#define J7200_DEV_MCAN3 161
171#define J7200_DEV_MCAN4 162
172#define J7200_DEV_MCAN5 163
173#define J7200_DEV_MCAN6 164
174#define J7200_DEV_MCAN7 165
175#define J7200_DEV_MCAN8 166
176#define J7200_DEV_MCAN9 167
177#define J7200_DEV_MCAN10 168
178#define J7200_DEV_MCAN11 169
179#define J7200_DEV_MCAN12 170
180#define J7200_DEV_MCAN13 171
181#define J7200_DEV_MCU_MCAN0 172
182#define J7200_DEV_MCU_MCAN1 173
183#define J7200_DEV_MCASP0 174
184#define J7200_DEV_MCASP1 175
185#define J7200_DEV_MCASP2 176
186#define J7200_DEV_I2C0 187
187#define J7200_DEV_I2C1 188
188#define J7200_DEV_I2C2 189
189#define J7200_DEV_I2C3 190
190#define J7200_DEV_I2C4 191
191#define J7200_DEV_I2C5 192
192#define J7200_DEV_I2C6 193
193#define J7200_DEV_MCU_I2C0 194
194#define J7200_DEV_MCU_I2C1 195
195#define J7200_DEV_WKUP_I2C0 197
196#define J7200_DEV_NAVSS0 199
197#define J7200_DEV_NAVSS0_CPTS_0 201
198#define J7200_DEV_A72SS0_CORE0 202
199#define J7200_DEV_A72SS0_CORE1 203
200#define J7200_DEV_NAVSS0_DTI_0 206
201#define J7200_DEV_NAVSS0_MODSS_INTA_0 207
202#define J7200_DEV_NAVSS0_MODSS_INTA_1 208
203#define J7200_DEV_NAVSS0_UDMASS_INTA_0 209
204#define J7200_DEV_NAVSS0_PROXY_0 210
205#define J7200_DEV_NAVSS0_RINGACC_0 211
206#define J7200_DEV_NAVSS0_UDMAP_0 212
207#define J7200_DEV_NAVSS0_INTR_ROUTER_0 213
208#define J7200_DEV_NAVSS0_MAILBOX_0 214
209#define J7200_DEV_NAVSS0_MAILBOX_1 215
210#define J7200_DEV_NAVSS0_MAILBOX_2 216
211#define J7200_DEV_NAVSS0_MAILBOX_3 217
212#define J7200_DEV_NAVSS0_MAILBOX_4 218
213#define J7200_DEV_NAVSS0_MAILBOX_5 219
214#define J7200_DEV_NAVSS0_MAILBOX_6 220
215#define J7200_DEV_NAVSS0_MAILBOX_7 221
216#define J7200_DEV_NAVSS0_MAILBOX_8 222
217#define J7200_DEV_NAVSS0_MAILBOX_9 223
218#define J7200_DEV_NAVSS0_MAILBOX_10 224
219#define J7200_DEV_NAVSS0_MAILBOX_11 225
220#define J7200_DEV_NAVSS0_SPINLOCK_0 226
221#define J7200_DEV_NAVSS0_MCRC_0 227
222#define J7200_DEV_NAVSS0_TBU_0 228
223#define J7200_DEV_NAVSS0_TIMERMGR_0 230
224#define J7200_DEV_NAVSS0_TIMERMGR_1 231
225#define J7200_DEV_MCU_NAVSS0 232
226#define J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233
227#define J7200_DEV_MCU_NAVSS0_PROXY0 234
228#define J7200_DEV_MCU_NAVSS0_RINGACC0 235
229#define J7200_DEV_MCU_NAVSS0_UDMAP_0 236
230#define J7200_DEV_MCU_NAVSS0_INTR_0 237
231#define J7200_DEV_MCU_NAVSS0_MCRC_0 238
232#define J7200_DEV_PCIE1 240
233#define J7200_DEV_R5FSS0 243
234#define J7200_DEV_R5FSS0_CORE0 245
235#define J7200_DEV_R5FSS0_CORE1 246
236#define J7200_DEV_MCU_R5FSS0 249
237#define J7200_DEV_MCU_R5FSS0_CORE0 250
238#define J7200_DEV_MCU_R5FSS0_CORE1 251
239#define J7200_DEV_RTI0 252
240#define J7200_DEV_RTI1 253
241#define J7200_DEV_RTI28 258
242#define J7200_DEV_RTI29 259
243#define J7200_DEV_MCU_RTI0 262
244#define J7200_DEV_MCU_RTI1 263
245#define J7200_DEV_MCU_SA2_UL0 265
246#define J7200_DEV_MCSPI0 266
247#define J7200_DEV_MCSPI1 267
248#define J7200_DEV_MCSPI2 268
249#define J7200_DEV_MCSPI3 269
250#define J7200_DEV_MCSPI4 270
251#define J7200_DEV_MCSPI5 271
252#define J7200_DEV_MCSPI6 272
253#define J7200_DEV_MCSPI7 273
254#define J7200_DEV_MCU_MCSPI0 274
255#define J7200_DEV_MCU_MCSPI1 275
256#define J7200_DEV_MCU_MCSPI2 276
257#define J7200_DEV_UART1 278
258#define J7200_DEV_UART2 279
259#define J7200_DEV_UART3 280
260#define J7200_DEV_UART4 281
261#define J7200_DEV_UART5 282
262#define J7200_DEV_UART6 283
263#define J7200_DEV_UART7 284
264#define J7200_DEV_UART8 285
265#define J7200_DEV_UART9 286
266#define J7200_DEV_WKUP_UART0 287
267#define J7200_DEV_USB0 288
268#define J7200_DEV_SERDES_10G1 292
269#define J7200_DEV_WKUPMCU2MAIN_VD 298
270#define J7200_DEV_NAVSS0_MODSS 299
271#define J7200_DEV_NAVSS0_UDMASS 300
272#define J7200_DEV_NAVSS0_VIRTSS 301
273#define J7200_DEV_MCU_NAVSS0_MODSS 302
274#define J7200_DEV_MCU_NAVSS0_UDMASS 303
275#define J7200_DEV_DEBUGSS_WRAP0 304
276#define J7200_DEV_FFI_MAIN_INFRA_CBASS_VD 305
277#define J7200_DEV_FFI_MAIN_IP_CBASS_VD 306
278#define J7200_DEV_FFI_MAIN_RC_CBASS_VD 307
279
280#endif /* SOC_J7200_DEVICES_H */
diff --git a/include/soc/j7200/hosts.h b/include/soc/j7200/hosts.h
new file mode 100644
index 0000000..35210d4
--- /dev/null
+++ b/include/soc/j7200/hosts.h
@@ -0,0 +1,76 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef J7200_HOSTS_H
36#define J7200_HOSTS_H
37
38/** DMSC(Secure): Device Management and Security Control */
39#define HOST_ID_DMSC (0U)
40/** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */
41#define HOST_ID_MCU_0_R5_0 (3U)
42/** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */
43#define HOST_ID_MCU_0_R5_1 (4U)
44/** MCU_0_R5_2(Non Secure): Cortex R5 context 2 on MCU island */
45#define HOST_ID_MCU_0_R5_2 (5U)
46/** MCU_0_R5_3(Secure): Cortex R5 context 3 on MCU island */
47#define HOST_ID_MCU_0_R5_3 (6U)
48/** A72_0(Secure): Cortex A72 context 0 on Main island */
49#define HOST_ID_A72_0 (10U)
50/** A72_1(Secure): Cortex A72 context 1 on Main island */
51#define HOST_ID_A72_1 (11U)
52/** A72_2(Non Secure): Cortex A72 context 2 on Main island */
53#define HOST_ID_A72_2 (12U)
54/** A72_3(Non Secure): Cortex A72 context 3 on Main island */
55#define HOST_ID_A72_3 (13U)
56/** A72_4(Non Secure): Cortex A72 context 4 on Main island */
57#define HOST_ID_A72_4 (14U)
58/** MAIN_0_R5_0(Non Secure): Cortex R5_0 context 0 on Main island */
59#define HOST_ID_MAIN_0_R5_0 (35U)
60/** MAIN_0_R5_1(Secure): Cortex R5_0 context 1 on Main island */
61#define HOST_ID_MAIN_0_R5_1 (36U)
62/** MAIN_0_R5_2(Non Secure): Cortex R5_0 context 2 on Main island */
63#define HOST_ID_MAIN_0_R5_2 (37U)
64/** MAIN_0_R5_3(Secure): Cortex R5_0 context 3 on MCU island */
65#define HOST_ID_MAIN_0_R5_3 (38U)
66
67/**
68 * Host catch all. Used in board configuration resource assignments to define
69 * resource ranges useable by all hosts. Cannot be used
70 */
71#define HOST_ID_ALL (128U)
72
73/** Number of unique hosts on the SoC */
74#define HOST_ID_CNT (14U)
75
76#endif /* J7200_HOSTS_H */
diff --git a/include/soc/j7200/resasg_types.h b/include/soc/j7200/resasg_types.h
new file mode 100644
index 0000000..418f5fc
--- /dev/null
+++ b/include/soc/j7200/resasg_types.h
@@ -0,0 +1,124 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef RESASG_TYPES_H
36#define RESASG_TYPES_H
37
38/**
39 * Resource assignment type shift
40 */
41#define RESASG_TYPE_SHIFT (0x0006U)
42/**
43 * Resource assignment type mask
44 */
45#define RESASG_TYPE_MASK (0xFFC0U)
46/**
47 * Resource assignment subtype shift
48 */
49#define RESASG_SUBTYPE_SHIFT (0x0000U)
50/**
51 * Resource assignment subtype mask
52 */
53#define RESASG_SUBTYPE_MASK (0x003FU)
54/**
55 * Macro to create unique resource assignment types using type and subtype
56 */
57
58#define RESASG_UTYPE(type, subtype) \
59 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) |\
60 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
61
62/**
63 * IA subtypes definitions
64 */
65#define RESASG_SUBTYPE_IA_VINT (0x000AU)
66#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
67#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
68#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
69#define RESASG_SUBTYPES_IA_CNT (0x0004U)
70
71/**
72 * IR subtypes definitions
73 */
74#define RESASG_SUBTYPE_IR_OUTPUT (0x0000U)
75#define RESASG_SUBTYPES_IR_CNT (0x0001U)
76
77/**
78 * Proxy subtypes definitions
79 */
80#define RESASG_SUBTYPE_PROXY_PROXIES (0x0000U)
81#define RESASG_SUBTYPES_PROXY_CNT (0x0001U)
82
83/**
84 * RA subtypes definitions
85 */
86#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
87#define RESASG_SUBTYPE_RA_GP (0x0001U)
88#define RESASG_SUBTYPE_RA_UDMAP_RX (0x0002U)
89#define RESASG_SUBTYPE_RA_UDMAP_TX (0x0003U)
90#define RESASG_SUBTYPE_RA_UDMAP_RX_H (0x0005U)
91#define RESASG_SUBTYPE_RA_UDMAP_RX_UH (0x0006U)
92#define RESASG_SUBTYPE_RA_UDMAP_TX_H (0x0007U)
93#define RESASG_SUBTYPE_RA_UDMAP_TX_UH (0x0008U)
94#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
95#define RESASG_SUBTYPE_RA_MONITORS (0x000BU)
96#define RESASG_SUBTYPES_RA_CNT (0x000AU)
97
98/**
99 * UDMAP subtypes definitions
100 */
101#define RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON (0x0000U)
102#define RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES (0x0001U)
103#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
104#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
105#define RESASG_SUBTYPE_UDMAP_RX_CHAN (0x000AU)
106#define RESASG_SUBTYPE_UDMAP_RX_HCHAN (0x000BU)
107#define RESASG_SUBTYPE_UDMAP_RX_UHCHAN (0x000CU)
108#define RESASG_SUBTYPE_UDMAP_TX_CHAN (0x000DU)
109#define RESASG_SUBTYPE_UDMAP_TX_HCHAN (0x000FU)
110#define RESASG_SUBTYPE_UDMAP_TX_UHCHAN (0x0010U)
111#define RESASG_SUBTYPES_UDMAP_CNT (0x000AU)
112
113
114/**
115 * Total number of unique resource types for SoC
116 */
117#define RESASG_UTYPE_CNT 54U
118
119/**
120 * Total number of resource entries allowed for SoC
121 */
122#define RESASG_ENTRIES_MAX (RESASG_UTYPE_CNT * 5U)
123
124#endif /* RESASG_TYPES_H */