include: j7200: Add sysfw board config data definitions

Add the following board config data definitions for j7200:
- Devices
- hosts
- RM assignment types

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

3 files changed, 480 insertions, 0 deletions

diff --git a/include/soc/j7200/devices.h b/include/soc/j7200/devices.h
new file mode 100644
index 0000000..bf8e60e
--- /dev/null
+++ b/include/soc/j7200/devices.h
@@ -0,0 +1,280 @@
+/*
+ * K3 System Firmware Board Configuration Data Definitions
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SOC_J7200_DEVICES_H
+#define SOC_J7200_DEVICES_H
+
+#define J7200_DEV_MCU_ADC0 0
+#define J7200_DEV_MCU_ADC1 1
+#define J7200_DEV_ATL0 2
+#define J7200_DEV_COMPUTE_CLUSTER0 3
+#define J7200_DEV_A72SS0 4
+#define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
+#define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6
+#define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7
+#define J7200_DEV_DDR0 8
+#define J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP 9
+#define J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 10
+#define J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 11
+#define J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP 12
+#define J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN 13
+#define J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14
+#define J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP 17
+#define J7200_DEV_MCU_CPSW0 18
+#define J7200_DEV_CPSW0 19
+#define J7200_DEV_CPT2_AGGR0 20
+#define J7200_DEV_CPT2_AGGR1 21
+#define J7200_DEV_WKUP_DMSC0 22
+#define J7200_DEV_CPT2_AGGR2 23
+#define J7200_DEV_MCU_CPT2_AGGR0 24
+#define J7200_DEV_CPT2_AGGR3 25
+#define J7200_DEV_CPSW_TX_RGMII0 26
+#define J7200_DEV_STM0 29
+#define J7200_DEV_DCC0 30
+#define J7200_DEV_DCC1 31
+#define J7200_DEV_DCC2 32
+#define J7200_DEV_DCC3 33
+#define J7200_DEV_DCC4 34
+#define J7200_DEV_MCU_TIMER0 35
+#define J7200_DEV_DCC5 36
+#define J7200_DEV_DCC6 37
+#define J7200_DEV_MAIN0 39
+#define J7200_DEV_WKUP_WAKEUP0 40
+#define J7200_DEV_MCU_DCC0 44
+#define J7200_DEV_MCU_DCC1 45
+#define J7200_DEV_MCU_DCC2 46
+#define J7200_DEV_TIMER0 49
+#define J7200_DEV_TIMER1 50
+#define J7200_DEV_TIMER2 51
+#define J7200_DEV_TIMER3 52
+#define J7200_DEV_TIMER4 53
+#define J7200_DEV_TIMER5 54
+#define J7200_DEV_TIMER6 55
+#define J7200_DEV_TIMER7 57
+#define J7200_DEV_TIMER8 58
+#define J7200_DEV_TIMER9 59
+#define J7200_DEV_TIMER10 60
+#define J7200_DEV_GTC0 61
+#define J7200_DEV_TIMER11 62
+#define J7200_DEV_TIMER12 63
+#define J7200_DEV_TIMER13 64
+#define J7200_DEV_TIMER14 65
+#define J7200_DEV_TIMER15 66
+#define J7200_DEV_TIMER16 67
+#define J7200_DEV_TIMER17 68
+#define J7200_DEV_TIMER18 69
+#define J7200_DEV_TIMER19 70
+#define J7200_DEV_MCU_TIMER1 71
+#define J7200_DEV_MCU_TIMER2 72
+#define J7200_DEV_MCU_TIMER3 73
+#define J7200_DEV_MCU_TIMER4 74
+#define J7200_DEV_MCU_TIMER5 75
+#define J7200_DEV_MCU_TIMER6 76
+#define J7200_DEV_MCU_TIMER7 77
+#define J7200_DEV_MCU_TIMER8 78
+#define J7200_DEV_MCU_TIMER9 79
+#define J7200_DEV_ECAP0 80
+#define J7200_DEV_ECAP1 81
+#define J7200_DEV_ECAP2 82
+#define J7200_DEV_EHRPWM0 83
+#define J7200_DEV_EHRPWM1 84
+#define J7200_DEV_EHRPWM2 85
+#define J7200_DEV_EHRPWM3 86
+#define J7200_DEV_EHRPWM4 87
+#define J7200_DEV_EHRPWM5 88
+#define J7200_DEV_ELM0 89
+#define J7200_DEV_EMIF_DATA_0_VD 90
+#define J7200_DEV_MMCSD0 91
+#define J7200_DEV_MMCSD1 92
+#define J7200_DEV_EQEP0 94
+#define J7200_DEV_EQEP1 95
+#define J7200_DEV_EQEP2 96
+#define J7200_DEV_ESM0 97
+#define J7200_DEV_MCU_ESM0 98
+#define J7200_DEV_WKUP_ESM0 99
+#define J7200_DEV_MCU_FSS0 100
+#define J7200_DEV_MCU_FSS0_FSAS_0 101
+#define J7200_DEV_MCU_FSS0_HYPERBUS1P0_0 102
+#define J7200_DEV_MCU_FSS0_OSPI_0 103
+#define J7200_DEV_MCU_FSS0_OSPI_1 104
+#define J7200_DEV_GPIO0 105
+#define J7200_DEV_GPIO2 107
+#define J7200_DEV_GPIO4 109
+#define J7200_DEV_GPIO6 111
+#define J7200_DEV_WKUP_GPIO0 113
+#define J7200_DEV_WKUP_GPIO1 114
+#define J7200_DEV_GPMC0 115
+#define J7200_DEV_I3C0 116
+#define J7200_DEV_MCU_I3C0 117
+#define J7200_DEV_MCU_I3C1 118
+#define J7200_DEV_CMPEVENT_INTRTR0 123
+#define J7200_DEV_LED0 127
+#define J7200_DEV_MAIN2MCU_LVL_INTRTR0 128
+#define J7200_DEV_MAIN2MCU_PLS_INTRTR0 130
+#define J7200_DEV_GPIOMUX_INTRTR0 131
+#define J7200_DEV_WKUP_PORZ_SYNC0 132
+#define J7200_DEV_PSC0 133
+#define J7200_DEV_TIMESYNC_INTRTR0 136
+#define J7200_DEV_WKUP_GPIOMUX_INTRTR0 137
+#define J7200_DEV_WKUP_PSC0 138
+#define J7200_DEV_PBIST0 139
+#define J7200_DEV_PBIST1 140
+#define J7200_DEV_PBIST2 141
+#define J7200_DEV_MCU_PBIST0 142
+#define J7200_DEV_MCU_PBIST1 143
+#define J7200_DEV_MCU_PBIST2 144
+#define J7200_DEV_WKUP_DDPA0 145
+#define J7200_DEV_UART0 146
+#define J7200_DEV_MCU_UART0 149
+#define J7200_DEV_MCAN14 150
+#define J7200_DEV_MCAN15 151
+#define J7200_DEV_MCAN16 152
+#define J7200_DEV_MCAN17 153
+#define J7200_DEV_WKUP_VTM0 154
+#define J7200_DEV_MAIN2WKUPMCU_VD 155
+#define J7200_DEV_MCAN0 156
+#define J7200_DEV_BOARD0 157
+#define J7200_DEV_MCAN1 158
+#define J7200_DEV_MCAN2 160
+#define J7200_DEV_MCAN3 161
+#define J7200_DEV_MCAN4 162
+#define J7200_DEV_MCAN5 163
+#define J7200_DEV_MCAN6 164
+#define J7200_DEV_MCAN7 165
+#define J7200_DEV_MCAN8 166
+#define J7200_DEV_MCAN9 167
+#define J7200_DEV_MCAN10 168
+#define J7200_DEV_MCAN11 169
+#define J7200_DEV_MCAN12 170
+#define J7200_DEV_MCAN13 171
+#define J7200_DEV_MCU_MCAN0 172
+#define J7200_DEV_MCU_MCAN1 173
+#define J7200_DEV_MCASP0 174
+#define J7200_DEV_MCASP1 175
+#define J7200_DEV_MCASP2 176
+#define J7200_DEV_I2C0 187
+#define J7200_DEV_I2C1 188
+#define J7200_DEV_I2C2 189
+#define J7200_DEV_I2C3 190
+#define J7200_DEV_I2C4 191
+#define J7200_DEV_I2C5 192
+#define J7200_DEV_I2C6 193
+#define J7200_DEV_MCU_I2C0 194
+#define J7200_DEV_MCU_I2C1 195
+#define J7200_DEV_WKUP_I2C0 197
+#define J7200_DEV_NAVSS0 199
+#define J7200_DEV_NAVSS0_CPTS_0 201
+#define J7200_DEV_A72SS0_CORE0 202
+#define J7200_DEV_A72SS0_CORE1 203
+#define J7200_DEV_NAVSS0_DTI_0 206
+#define J7200_DEV_NAVSS0_MODSS_INTA_0 207
+#define J7200_DEV_NAVSS0_MODSS_INTA_1 208
+#define J7200_DEV_NAVSS0_UDMASS_INTA_0 209
+#define J7200_DEV_NAVSS0_PROXY_0 210
+#define J7200_DEV_NAVSS0_RINGACC_0 211
+#define J7200_DEV_NAVSS0_UDMAP_0 212
+#define J7200_DEV_NAVSS0_INTR_ROUTER_0 213
+#define J7200_DEV_NAVSS0_MAILBOX_0 214
+#define J7200_DEV_NAVSS0_MAILBOX_1 215
+#define J7200_DEV_NAVSS0_MAILBOX_2 216
+#define J7200_DEV_NAVSS0_MAILBOX_3 217
+#define J7200_DEV_NAVSS0_MAILBOX_4 218
+#define J7200_DEV_NAVSS0_MAILBOX_5 219
+#define J7200_DEV_NAVSS0_MAILBOX_6 220
+#define J7200_DEV_NAVSS0_MAILBOX_7 221
+#define J7200_DEV_NAVSS0_MAILBOX_8 222
+#define J7200_DEV_NAVSS0_MAILBOX_9 223
+#define J7200_DEV_NAVSS0_MAILBOX_10 224
+#define J7200_DEV_NAVSS0_MAILBOX_11 225
+#define J7200_DEV_NAVSS0_SPINLOCK_0 226
+#define J7200_DEV_NAVSS0_MCRC_0 227
+#define J7200_DEV_NAVSS0_TBU_0 228
+#define J7200_DEV_NAVSS0_TIMERMGR_0 230
+#define J7200_DEV_NAVSS0_TIMERMGR_1 231
+#define J7200_DEV_MCU_NAVSS0 232
+#define J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233
+#define J7200_DEV_MCU_NAVSS0_PROXY0 234
+#define J7200_DEV_MCU_NAVSS0_RINGACC0 235
+#define J7200_DEV_MCU_NAVSS0_UDMAP_0 236
+#define J7200_DEV_MCU_NAVSS0_INTR_0 237
+#define J7200_DEV_MCU_NAVSS0_MCRC_0 238
+#define J7200_DEV_PCIE1 240
+#define J7200_DEV_R5FSS0 243
+#define J7200_DEV_R5FSS0_CORE0 245
+#define J7200_DEV_R5FSS0_CORE1 246
+#define J7200_DEV_MCU_R5FSS0 249
+#define J7200_DEV_MCU_R5FSS0_CORE0 250
+#define J7200_DEV_MCU_R5FSS0_CORE1 251
+#define J7200_DEV_RTI0 252
+#define J7200_DEV_RTI1 253
+#define J7200_DEV_RTI28 258
+#define J7200_DEV_RTI29 259
+#define J7200_DEV_MCU_RTI0 262
+#define J7200_DEV_MCU_RTI1 263
+#define J7200_DEV_MCU_SA2_UL0 265
+#define J7200_DEV_MCSPI0 266
+#define J7200_DEV_MCSPI1 267
+#define J7200_DEV_MCSPI2 268
+#define J7200_DEV_MCSPI3 269
+#define J7200_DEV_MCSPI4 270
+#define J7200_DEV_MCSPI5 271
+#define J7200_DEV_MCSPI6 272
+#define J7200_DEV_MCSPI7 273
+#define J7200_DEV_MCU_MCSPI0 274
+#define J7200_DEV_MCU_MCSPI1 275
+#define J7200_DEV_MCU_MCSPI2 276
+#define J7200_DEV_UART1 278
+#define J7200_DEV_UART2 279
+#define J7200_DEV_UART3 280
+#define J7200_DEV_UART4 281
+#define J7200_DEV_UART5 282
+#define J7200_DEV_UART6 283
+#define J7200_DEV_UART7 284
+#define J7200_DEV_UART8 285
+#define J7200_DEV_UART9 286
+#define J7200_DEV_WKUP_UART0 287
+#define J7200_DEV_USB0 288
+#define J7200_DEV_SERDES_10G1 292
+#define J7200_DEV_WKUPMCU2MAIN_VD 298
+#define J7200_DEV_NAVSS0_MODSS 299
+#define J7200_DEV_NAVSS0_UDMASS 300
+#define J7200_DEV_NAVSS0_VIRTSS 301
+#define J7200_DEV_MCU_NAVSS0_MODSS 302
+#define J7200_DEV_MCU_NAVSS0_UDMASS 303
+#define J7200_DEV_DEBUGSS_WRAP0 304
+#define J7200_DEV_FFI_MAIN_INFRA_CBASS_VD 305
+#define J7200_DEV_FFI_MAIN_IP_CBASS_VD 306
+#define J7200_DEV_FFI_MAIN_RC_CBASS_VD 307
+
+#endif /* SOC_J7200_DEVICES_H */
diff --git a/include/soc/j7200/hosts.h b/include/soc/j7200/hosts.h
new file mode 100644
index 0000000..35210d4
--- /dev/null
+++ b/include/soc/j7200/hosts.h
@@ -0,0 +1,76 @@
+/*
+ * K3 System Firmware Board Configuration Data Definitions
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef J7200_HOSTS_H
+#define J7200_HOSTS_H
+
+/** DMSC(Secure): Device Management and Security Control */
+#define HOST_ID_DMSC (0U)
+/** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */
+#define HOST_ID_MCU_0_R5_0 (3U)
+/** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */
+#define HOST_ID_MCU_0_R5_1 (4U)
+/** MCU_0_R5_2(Non Secure): Cortex R5 context 2 on MCU island */
+#define HOST_ID_MCU_0_R5_2 (5U)
+/** MCU_0_R5_3(Secure): Cortex R5 context 3 on MCU island */
+#define HOST_ID_MCU_0_R5_3 (6U)
+/** A72_0(Secure): Cortex A72 context 0 on Main island */
+#define HOST_ID_A72_0 (10U)
+/** A72_1(Secure): Cortex A72 context 1 on Main island */
+#define HOST_ID_A72_1 (11U)
+/** A72_2(Non Secure): Cortex A72 context 2 on Main island */
+#define HOST_ID_A72_2 (12U)
+/** A72_3(Non Secure): Cortex A72 context 3 on Main island */
+#define HOST_ID_A72_3 (13U)
+/** A72_4(Non Secure): Cortex A72 context 4 on Main island */
+#define HOST_ID_A72_4 (14U)
+/** MAIN_0_R5_0(Non Secure): Cortex R5_0 context 0 on Main island */
+#define HOST_ID_MAIN_0_R5_0 (35U)
+/** MAIN_0_R5_1(Secure): Cortex R5_0 context 1 on Main island */
+#define HOST_ID_MAIN_0_R5_1 (36U)
+/** MAIN_0_R5_2(Non Secure): Cortex R5_0 context 2 on Main island */
+#define HOST_ID_MAIN_0_R5_2 (37U)
+/** MAIN_0_R5_3(Secure): Cortex R5_0 context 3 on MCU island */
+#define HOST_ID_MAIN_0_R5_3 (38U)
+
+/**
+ * Host catch all. Used in board configuration resource assignments to define
+ * resource ranges useable by all hosts. Cannot be used
+ */
+#define HOST_ID_ALL (128U)
+
+/** Number of unique hosts on the SoC */
+#define HOST_ID_CNT (14U)
+
+#endif /* J7200_HOSTS_H */
diff --git a/include/soc/j7200/resasg_types.h b/include/soc/j7200/resasg_types.h
new file mode 100644
index 0000000..418f5fc
--- /dev/null
+++ b/include/soc/j7200/resasg_types.h
@@ -0,0 +1,124 @@
+/*
+ * K3 System Firmware Board Configuration Data Definitions
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef RESASG_TYPES_H
+#define RESASG_TYPES_H
+
+/**
+ * Resource assignment type shift
+ */
+#define RESASG_TYPE_SHIFT (0x0006U)
+/**
+ * Resource assignment type mask
+ */
+#define RESASG_TYPE_MASK (0xFFC0U)
+/**
+ * Resource assignment subtype shift
+ */
+#define RESASG_SUBTYPE_SHIFT (0x0000U)
+/**
+ * Resource assignment subtype mask
+ */
+#define RESASG_SUBTYPE_MASK (0x003FU)
+/**
+ * Macro to create unique resource assignment types using type and subtype
+ */
+
+#define RESASG_UTYPE(type, subtype) \
+        (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) |\
+         ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
+
+/**
+ * IA subtypes definitions
+ */
+#define RESASG_SUBTYPE_IA_VINT (0x000AU)
+#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
+#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
+#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
+#define RESASG_SUBTYPES_IA_CNT (0x0004U)
+
+/**
+ * IR subtypes definitions
+ */
+#define RESASG_SUBTYPE_IR_OUTPUT (0x0000U)
+#define RESASG_SUBTYPES_IR_CNT (0x0001U)
+
+/**
+ * Proxy subtypes definitions
+ */
+#define RESASG_SUBTYPE_PROXY_PROXIES (0x0000U)
+#define RESASG_SUBTYPES_PROXY_CNT (0x0001U)
+
+/**
+ * RA subtypes definitions
+ */
+#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
+#define RESASG_SUBTYPE_RA_GP (0x0001U)
+#define RESASG_SUBTYPE_RA_UDMAP_RX (0x0002U)
+#define RESASG_SUBTYPE_RA_UDMAP_TX (0x0003U)
+#define RESASG_SUBTYPE_RA_UDMAP_RX_H (0x0005U)
+#define RESASG_SUBTYPE_RA_UDMAP_RX_UH (0x0006U)
+#define RESASG_SUBTYPE_RA_UDMAP_TX_H (0x0007U)
+#define RESASG_SUBTYPE_RA_UDMAP_TX_UH (0x0008U)
+#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
+#define RESASG_SUBTYPE_RA_MONITORS (0x000BU)
+#define RESASG_SUBTYPES_RA_CNT (0x000AU)
+
+/**
+ * UDMAP subtypes definitions
+ */
+#define RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON (0x0000U)
+#define RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES (0x0001U)
+#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
+#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
+#define RESASG_SUBTYPE_UDMAP_RX_CHAN (0x000AU)
+#define RESASG_SUBTYPE_UDMAP_RX_HCHAN (0x000BU)
+#define RESASG_SUBTYPE_UDMAP_RX_UHCHAN (0x000CU)
+#define RESASG_SUBTYPE_UDMAP_TX_CHAN (0x000DU)
+#define RESASG_SUBTYPE_UDMAP_TX_HCHAN (0x000FU)
+#define RESASG_SUBTYPE_UDMAP_TX_UHCHAN (0x0010U)
+#define RESASG_SUBTYPES_UDMAP_CNT (0x000AU)
+
+
+/**
+ * Total number of unique resource types for SoC
+ */
+#define RESASG_UTYPE_CNT 54U
+
+/**
+ * Total number of resource entries allowed for SoC
+ */
+#define RESASG_ENTRIES_MAX (RESASG_UTYPE_CNT * 5U)
+
+#endif /* RESASG_TYPES_H */