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authorNikhil Devshatwar2020-08-18 11:01:09 -0500
committerDave Gerlach2020-08-19 09:33:43 -0500
commit75d3fce7d9b780f24664cb3da76ab0031a19ff81 (patch)
tree89aab398dc6a791a8e1145e8826dfb3180f8c131
parent060498a9bf287260431139f69767f54eff3d159c (diff)
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include: j721e: j7200: Update headers from SYSFW 2020.07-RC2
Update header files from System firmware 2020.07. This includes many renames for the device macros. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rw-r--r--include/soc/j7200/devices.h6
-rw-r--r--include/soc/j721e/devices.h54
-rw-r--r--include/soc/j721e/hosts.h21
3 files changed, 51 insertions, 30 deletions
diff --git a/include/soc/j7200/devices.h b/include/soc/j7200/devices.h
index bf8e60e..11cc026 100644
--- a/include/soc/j7200/devices.h
+++ b/include/soc/j7200/devices.h
@@ -39,7 +39,7 @@
39#define J7200_DEV_MCU_ADC1 1 39#define J7200_DEV_MCU_ADC1 1
40#define J7200_DEV_ATL0 2 40#define J7200_DEV_ATL0 2
41#define J7200_DEV_COMPUTE_CLUSTER0 3 41#define J7200_DEV_COMPUTE_CLUSTER0 3
42#define J7200_DEV_A72SS0 4 42#define J7200_DEV_A72SS0_CORE0 4
43#define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5 43#define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
44#define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6 44#define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6
45#define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7 45#define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7
@@ -195,8 +195,8 @@
195#define J7200_DEV_WKUP_I2C0 197 195#define J7200_DEV_WKUP_I2C0 197
196#define J7200_DEV_NAVSS0 199 196#define J7200_DEV_NAVSS0 199
197#define J7200_DEV_NAVSS0_CPTS_0 201 197#define J7200_DEV_NAVSS0_CPTS_0 201
198#define J7200_DEV_A72SS0_CORE0 202 198#define J7200_DEV_A72SS0_CORE0_0 202
199#define J7200_DEV_A72SS0_CORE1 203 199#define J7200_DEV_A72SS0_CORE0_1 203
200#define J7200_DEV_NAVSS0_DTI_0 206 200#define J7200_DEV_NAVSS0_DTI_0 206
201#define J7200_DEV_NAVSS0_MODSS_INTA_0 207 201#define J7200_DEV_NAVSS0_MODSS_INTA_0 207
202#define J7200_DEV_NAVSS0_MODSS_INTA_1 208 202#define J7200_DEV_NAVSS0_MODSS_INTA_1 208
diff --git a/include/soc/j721e/devices.h b/include/soc/j721e/devices.h
index 2d0458a..1c2ab11 100644
--- a/include/soc/j721e/devices.h
+++ b/include/soc/j721e/devices.h
@@ -35,10 +35,10 @@
35#ifndef SOC_J721E_DEVICES_H 35#ifndef SOC_J721E_DEVICES_H
36#define SOC_J721E_DEVICES_H 36#define SOC_J721E_DEVICES_H
37 37
38#define J721E_DEV_MCU_ADC0 0 38#define J721E_DEV_MCU_ADC12_16FFC0 0
39#define J721E_DEV_MCU_ADC1 1 39#define J721E_DEV_MCU_ADC12_16FFC1 1
40#define J721E_DEV_ATL0 2 40#define J721E_DEV_ATL0 2
41#define J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 3 41#define J721E_DEV_COMPUTE_CLUSTER0 3
42#define J721E_DEV_A72SS0 4 42#define J721E_DEV_A72SS0 4
43#define J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5 43#define J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
44#define J721E_DEV_COMPUTE_CLUSTER0_CLEC 6 44#define J721E_DEV_COMPUTE_CLUSTER0_CLEC 6
@@ -57,7 +57,7 @@
57#define J721E_DEV_CPSW0 19 57#define J721E_DEV_CPSW0 19
58#define J721E_DEV_CPT2_AGGR0 20 58#define J721E_DEV_CPT2_AGGR0 20
59#define J721E_DEV_CPT2_AGGR1 21 59#define J721E_DEV_CPT2_AGGR1 21
60#define J721E_DEV_DMSC_WKUP_0 22 60#define J721E_DEV_WKUP_DMSC0 22
61#define J721E_DEV_CPT2_AGGR2 23 61#define J721E_DEV_CPT2_AGGR2 23
62#define J721E_DEV_MCU_CPT2_AGGR0 24 62#define J721E_DEV_MCU_CPT2_AGGR0 24
63#define J721E_DEV_CSI_PSILSS0 25 63#define J721E_DEV_CSI_PSILSS0 25
@@ -83,7 +83,7 @@
83#define J721E_DEV_MCU_DCC1 45 83#define J721E_DEV_MCU_DCC1 45
84#define J721E_DEV_MCU_DCC2 46 84#define J721E_DEV_MCU_DCC2 46
85#define J721E_DEV_DDR0 47 85#define J721E_DEV_DDR0 47
86#define J721E_DEV_DMPAC_TOP_MAIN_0 48 86#define J721E_DEV_DMPAC0 48
87#define J721E_DEV_TIMER0 49 87#define J721E_DEV_TIMER0 49
88#define J721E_DEV_TIMER1 50 88#define J721E_DEV_TIMER1 50
89#define J721E_DEV_TIMER2 51 89#define J721E_DEV_TIMER2 51
@@ -134,7 +134,7 @@
134#define J721E_DEV_ESM0 97 134#define J721E_DEV_ESM0 97
135#define J721E_DEV_MCU_ESM0 98 135#define J721E_DEV_MCU_ESM0 98
136#define J721E_DEV_WKUP_ESM0 99 136#define J721E_DEV_WKUP_ESM0 99
137#define J721E_DEV_FSS_MCU_0 100 137#define J721E_DEV_MCU_FSS0 100
138#define J721E_DEV_MCU_FSS0_FSAS_0 101 138#define J721E_DEV_MCU_FSS0_FSAS_0 101
139#define J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 102 139#define J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 102
140#define J721E_DEV_MCU_FSS0_OSPI_0 103 140#define J721E_DEV_MCU_FSS0_OSPI_0 103
@@ -158,7 +158,7 @@
158#define J721E_DEV_C66SS0_INTROUTER0 121 158#define J721E_DEV_C66SS0_INTROUTER0 121
159#define J721E_DEV_C66SS1_INTROUTER0 122 159#define J721E_DEV_C66SS1_INTROUTER0 122
160#define J721E_DEV_CMPEVENT_INTRTR0 123 160#define J721E_DEV_CMPEVENT_INTRTR0 123
161#define J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0 124 161#define J721E_DEV_GPU0 124
162#define J721E_DEV_GPU0_GPU_0 125 162#define J721E_DEV_GPU0_GPU_0 125
163#define J721E_DEV_GPU0_GPUCORE_0 126 163#define J721E_DEV_GPU0_GPUCORE_0 126
164#define J721E_DEV_LED0 127 164#define J721E_DEV_LED0 127
@@ -173,8 +173,8 @@
173#define J721E_DEV_WKUP_GPIOMUX_INTRTR0 137 173#define J721E_DEV_WKUP_GPIOMUX_INTRTR0 137
174#define J721E_DEV_WKUP_PSC0 138 174#define J721E_DEV_WKUP_PSC0 138
175#define J721E_DEV_AASRC0 139 175#define J721E_DEV_AASRC0 139
176#define J721E_DEV_K3_C66_COREPAC_MAIN_0 140 176#define J721E_DEV_C66SS0 140
177#define J721E_DEV_K3_C66_COREPAC_MAIN_1 141 177#define J721E_DEV_C66SS1 141
178#define J721E_DEV_C66SS0_CORE0 142 178#define J721E_DEV_C66SS0_CORE0 142
179#define J721E_DEV_C66SS1_CORE0 143 179#define J721E_DEV_C66SS1_CORE0 143
180#define J721E_DEV_DECODER0 144 180#define J721E_DEV_DECODER0 144
@@ -229,7 +229,7 @@
229#define J721E_DEV_MCU_I2C0 194 229#define J721E_DEV_MCU_I2C0 194
230#define J721E_DEV_MCU_I2C1 195 230#define J721E_DEV_MCU_I2C1 195
231#define J721E_DEV_WKUP_I2C0 197 231#define J721E_DEV_WKUP_I2C0 197
232#define J721E_DEV_NAVSS512L_MAIN_0 199 232#define J721E_DEV_NAVSS0 199
233#define J721E_DEV_NAVSS0_CPTS_0 201 233#define J721E_DEV_NAVSS0_CPTS_0 201
234#define J721E_DEV_A72SS0_CORE0 202 234#define J721E_DEV_A72SS0_CORE0 202
235#define J721E_DEV_A72SS0_CORE1 203 235#define J721E_DEV_A72SS0_CORE1 203
@@ -259,24 +259,24 @@
259#define J721E_DEV_NAVSS0_TCU_0 229 259#define J721E_DEV_NAVSS0_TCU_0 229
260#define J721E_DEV_NAVSS0_TIMERMGR_0 230 260#define J721E_DEV_NAVSS0_TIMERMGR_0 230
261#define J721E_DEV_NAVSS0_TIMERMGR_1 231 261#define J721E_DEV_NAVSS0_TIMERMGR_1 231
262#define J721E_DEV_NAVSS_MCU_J7_MCU_0 232 262#define J721E_DEV_MCU_NAVSS0 232
263#define J721E_DEV_MCU_NAVSS0_INTAGGR_0 233 263#define J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 233
264#define J721E_DEV_MCU_NAVSS0_PROXY_0 234 264#define J721E_DEV_MCU_NAVSS0_PROXY0 234
265#define J721E_DEV_MCU_NAVSS0_RINGACC_0 235 265#define J721E_DEV_MCU_NAVSS0_RINGACC0 235
266#define J721E_DEV_MCU_NAVSS0_UDMAP_0 236 266#define J721E_DEV_MCU_NAVSS0_UDMAP_0 236
267#define J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0 237 267#define J721E_DEV_MCU_NAVSS0_INTR_0 237
268#define J721E_DEV_MCU_NAVSS0_MCRC_0 238 268#define J721E_DEV_MCU_NAVSS0_MCRC_0 238
269#define J721E_DEV_PCIE0 239 269#define J721E_DEV_PCIE0 239
270#define J721E_DEV_PCIE1 240 270#define J721E_DEV_PCIE1 240
271#define J721E_DEV_PCIE2 241 271#define J721E_DEV_PCIE2 241
272#define J721E_DEV_PCIE3 242 272#define J721E_DEV_PCIE3 242
273#define J721E_DEV_PULSAR_SL_MAIN_0 243 273#define J721E_DEV_R5FSS0 243
274#define J721E_DEV_PULSAR_SL_MAIN_1 244 274#define J721E_DEV_R5FSS1 244
275#define J721E_DEV_R5FSS0_CORE0 245 275#define J721E_DEV_R5FSS0_CORE0 245
276#define J721E_DEV_R5FSS0_CORE1 246 276#define J721E_DEV_R5FSS0_CORE1 246
277#define J721E_DEV_R5FSS1_CORE0 247 277#define J721E_DEV_R5FSS1_CORE0 247
278#define J721E_DEV_R5FSS1_CORE1 248 278#define J721E_DEV_R5FSS1_CORE1 248
279#define J721E_DEV_PULSAR_SL_MCU_0 249 279#define J721E_DEV_MCU_R5FSS0 249
280#define J721E_DEV_MCU_R5FSS0_CORE0 250 280#define J721E_DEV_MCU_R5FSS0_CORE0 250
281#define J721E_DEV_MCU_R5FSS0_CORE1 251 281#define J721E_DEV_MCU_R5FSS0_CORE1 251
282#define J721E_DEV_RTI0 252 282#define J721E_DEV_RTI0 252
@@ -317,7 +317,7 @@
317#define J721E_DEV_WKUP_UART0 287 317#define J721E_DEV_WKUP_UART0 287
318#define J721E_DEV_USB0 288 318#define J721E_DEV_USB0 288
319#define J721E_DEV_USB1 289 319#define J721E_DEV_USB1 289
320#define J721E_DEV_VPAC_TOP_MAIN_0 290 320#define J721E_DEV_VPAC0 290
321#define J721E_DEV_VPFE0 291 321#define J721E_DEV_VPFE0 291
322#define J721E_DEV_SERDES_16G0 292 322#define J721E_DEV_SERDES_16G0 292
323#define J721E_DEV_SERDES_16G1 293 323#define J721E_DEV_SERDES_16G1 293
@@ -333,5 +333,21 @@
333#define J721E_DEV_MCU_NAVSS0_UDMASS 303 333#define J721E_DEV_MCU_NAVSS0_UDMASS 303
334#define J721E_DEV_DEBUGSS_WRAP0 304 334#define J721E_DEV_DEBUGSS_WRAP0 304
335#define J721E_DEV_DMPAC0_SDE_0 305 335#define J721E_DEV_DMPAC0_SDE_0 305
336#define J721E_DEV_GPU0_DFT_PBIST_0 306
337#define J721E_DEV_C66SS0_PBIST0 307
338#define J721E_DEV_C66SS1_PBIST0 308
339#define J721E_DEV_PBIST0 309
340#define J721E_DEV_PBIST1 310
341#define J721E_DEV_PBIST2 311
342#define J721E_DEV_PBIST3 312
343#define J721E_DEV_PBIST4 313
344#define J721E_DEV_PBIST5 314
345#define J721E_DEV_PBIST6 315
346#define J721E_DEV_PBIST7 316
347#define J721E_DEV_PBIST9 317
348#define J721E_DEV_PBIST10 318
349#define J721E_DEV_MCU_PBIST0 319
350#define J721E_DEV_MCU_PBIST1 320
351#define J721E_DEV_C71X_0_PBIST_VD 321
336 352
337#endif /* SOC_J721E_DEVICES_H */ 353#endif /* SOC_J721E_DEVICES_H */
diff --git a/include/soc/j721e/hosts.h b/include/soc/j721e/hosts.h
index 7a55f60..a6595ee 100644
--- a/include/soc/j721e/hosts.h
+++ b/include/soc/j721e/hosts.h
@@ -35,10 +35,10 @@
35#ifndef J721E_HOSTS_H 35#ifndef J721E_HOSTS_H
36#define J721E_HOSTS_H 36#define J721E_HOSTS_H
37 37
38/* Host IDs for J721E Device */ 38/** DMSC(Secure): Security Controller */
39
40/** DMSC(Secure): Device Management and Security Control */
41#define HOST_ID_DMSC (0U) 39#define HOST_ID_DMSC (0U)
40/** DM(Non Secure): Device Management */
41#define HOST_ID_DM (254U)
42/** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */ 42/** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */
43#define HOST_ID_MCU_0_R5_0 (3U) 43#define HOST_ID_MCU_0_R5_0 (3U)
44/** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */ 44/** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */
@@ -89,13 +89,18 @@
89#define HOST_ID_MAIN_1_R5_3 (43U) 89#define HOST_ID_MAIN_1_R5_3 (43U)
90/** ICSSG_0(Non Secure): ICSSG context 0 on Main island */ 90/** ICSSG_0(Non Secure): ICSSG context 0 on Main island */
91#define HOST_ID_ICSSG_0 (50U) 91#define HOST_ID_ICSSG_0 (50U)
92/** DM2DMSC(Secure): DM to DMSC communication */
93#define HOST_ID_DM2DMSC (250U)
94/** DMSC2DM(Non Secure): DMSC to DM communication */
95#define HOST_ID_DMSC2DM (251U)
92 96
93/** Host catch all. Used in board configuration resource assignments to 97/**
94 * define resource ranges useable by all hosts. Cannot be used as a host 98 * Host catch all. Used in board configuration resource assignments to define
95 * in TISCI message headers */ 99 * resource ranges useable by all hosts. Cannot be used
100 */
96#define HOST_ID_ALL (128U) 101#define HOST_ID_ALL (128U)
97 102
98/** Number of unique hosts on the J721E SoC */ 103/** Number of unique hosts on the SoC */
99#define HOST_ID_CNT (26U) 104#define HOST_ID_CNT (29U)
100 105
101#endif /* J721E_HOSTS_H */ 106#endif /* J721E_HOSTS_H */