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authorVignesh Raghavendra2021-04-14 11:53:42 -0500
committerDave Gerlach2021-04-19 09:38:28 -0500
commita6b09643aa1acbcfa59bd2c1c080e3ad6c9e8074 (patch)
tree7ce4cb96a74b718c65c70132361f80f18a0bbbb1
parentc376cd495b9821b6e3cb296b1bbae10d0f010817 (diff)
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j721e/j7200: rm-cfg: Drop resource allocation of MCU R50 secure context2021.00.001
Drop resource allocation for MCU_R5_0_1 as post HSM Rearch, R5 SPL needs to non secure host IDs for all RM requests. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--soc/j7200/evm/rm-cfg.c261
-rw-r--r--soc/j7200/evm/sysfw_img_cfg.h4
-rw-r--r--soc/j721e/evm/rm-cfg.c262
-rw-r--r--soc/j721e/evm/sysfw_img_cfg.h4
4 files changed, 10 insertions, 521 deletions
diff --git a/soc/j7200/evm/rm-cfg.c b/soc/j7200/evm/rm-cfg.c
index fd0ff41..390163a 100644
--- a/soc/j7200/evm/rm-cfg.c
+++ b/soc/j7200/evm/rm-cfg.c
@@ -2,7 +2,7 @@
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -129,13 +129,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
129 .host_id = HOST_ID_MCU_0_R5_0, 129 .host_id = HOST_ID_MCU_0_R5_0,
130 }, 130 },
131 { 131 {
132 .start_resource = 0,
133 .num_resource = 32,
134 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0,
135 RESASG_SUBTYPE_IR_OUTPUT),
136 .host_id = HOST_ID_MCU_0_R5_1,
137 },
138 {
139 .start_resource = 32, 132 .start_resource = 32,
140 .num_resource = 32, 133 .num_resource = 32,
141 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0, 134 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0,
@@ -151,13 +144,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
151 .host_id = HOST_ID_MCU_0_R5_0, 144 .host_id = HOST_ID_MCU_0_R5_0,
152 }, 145 },
153 { 146 {
154 .start_resource = 0,
155 .num_resource = 24,
156 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0,
157 RESASG_SUBTYPE_IR_OUTPUT),
158 .host_id = HOST_ID_MCU_0_R5_1,
159 },
160 {
161 .start_resource = 24, 147 .start_resource = 24,
162 .num_resource = 24, 148 .num_resource = 24,
163 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0, 149 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0,
@@ -173,13 +159,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
173 .host_id = HOST_ID_MCU_0_R5_0, 159 .host_id = HOST_ID_MCU_0_R5_0,
174 }, 160 },
175 { 161 {
176 .start_resource = 0,
177 .num_resource = 8,
178 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
179 RESASG_SUBTYPE_IR_OUTPUT),
180 .host_id = HOST_ID_MCU_0_R5_1,
181 },
182 {
183 .start_resource = 8, 162 .start_resource = 8,
184 .num_resource = 8, 163 .num_resource = 8,
185 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0, 164 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
@@ -231,13 +210,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
231 .host_id = HOST_ID_MCU_0_R5_0, 210 .host_id = HOST_ID_MCU_0_R5_0,
232 }, 211 },
233 { 212 {
234 .start_resource = 0,
235 .num_resource = 8,
236 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
237 RESASG_SUBTYPE_IR_OUTPUT),
238 .host_id = HOST_ID_MCU_0_R5_1,
239 },
240 {
241 .start_resource = 8, 213 .start_resource = 8,
242 .num_resource = 8, 214 .num_resource = 8,
243 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0, 215 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
@@ -313,13 +285,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
313 .host_id = HOST_ID_MCU_0_R5_0, 285 .host_id = HOST_ID_MCU_0_R5_0,
314 }, 286 },
315 { 287 {
316 .start_resource = 136,
317 .num_resource = 16,
318 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
319 RESASG_SUBTYPE_IA_VINT),
320 .host_id = HOST_ID_MCU_0_R5_1,
321 },
322 {
323 .start_resource = 152, 288 .start_resource = 152,
324 .num_resource = 16, 289 .num_resource = 16,
325 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 290 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
@@ -370,13 +335,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
370 .host_id = HOST_ID_MCU_0_R5_0, 335 .host_id = HOST_ID_MCU_0_R5_0,
371 }, 336 },
372 { 337 {
373 .start_resource = 1554,
374 .num_resource = 128,
375 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
376 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
377 .host_id = HOST_ID_MCU_0_R5_1,
378 },
379 {
380 .start_resource = 1682, 338 .start_resource = 1682,
381 .num_resource = 128, 339 .num_resource = 128,
382 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0, 340 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
@@ -427,13 +385,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
427 .host_id = HOST_ID_MCU_0_R5_0, 385 .host_id = HOST_ID_MCU_0_R5_0,
428 }, 386 },
429 { 387 {
430 .start_resource = 8,
431 .num_resource = 4,
432 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
433 RESASG_SUBTYPE_PROXY_PROXIES),
434 .host_id = HOST_ID_MCU_0_R5_1,
435 },
436 {
437 .start_resource = 12, 388 .start_resource = 12,
438 .num_resource = 4, 389 .num_resource = 4,
439 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0, 390 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
@@ -492,13 +443,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
492 .host_id = HOST_ID_MCU_0_R5_0, 443 .host_id = HOST_ID_MCU_0_R5_0,
493 }, 444 },
494 { 445 {
495 .start_resource = 360,
496 .num_resource = 32,
497 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
498 RESASG_SUBTYPE_RA_GP),
499 .host_id = HOST_ID_MCU_0_R5_1,
500 },
501 {
502 .start_resource = 392, 446 .start_resource = 392,
503 .num_resource = 32, 447 .num_resource = 32,
504 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 448 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -549,13 +493,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
549 .host_id = HOST_ID_MCU_0_R5_0, 493 .host_id = HOST_ID_MCU_0_R5_0,
550 }, 494 },
551 { 495 {
552 .start_resource = 70,
553 .num_resource = 2,
554 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
555 RESASG_SUBTYPE_RA_UDMAP_RX),
556 .host_id = HOST_ID_MCU_0_R5_1,
557 },
558 {
559 .start_resource = 72, 496 .start_resource = 72,
560 .num_resource = 2, 497 .num_resource = 2,
561 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 498 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -634,13 +571,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
634 .host_id = HOST_ID_MCU_0_R5_0, 571 .host_id = HOST_ID_MCU_0_R5_0,
635 }, 572 },
636 { 573 {
637 .start_resource = 10,
638 .num_resource = 2,
639 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
640 RESASG_SUBTYPE_RA_UDMAP_TX),
641 .host_id = HOST_ID_MCU_0_R5_1,
642 },
643 {
644 .start_resource = 12, 574 .start_resource = 12,
645 .num_resource = 2, 575 .num_resource = 2,
646 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 576 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -822,13 +752,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
822 .host_id = HOST_ID_MCU_0_R5_0, 752 .host_id = HOST_ID_MCU_0_R5_0,
823 }, 753 },
824 { 754 {
825 .start_resource = 5,
826 .num_resource = 1,
827 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
828 RESASG_SUBTYPE_RA_MONITORS),
829 .host_id = HOST_ID_MCU_0_R5_1,
830 },
831 {
832 .start_resource = 6, 755 .start_resource = 6,
833 .num_resource = 1, 756 .num_resource = 1,
834 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 757 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
@@ -932,13 +855,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
932 .host_id = HOST_ID_MCU_0_R5_0, 855 .host_id = HOST_ID_MCU_0_R5_0,
933 }, 856 },
934 { 857 {
935 .start_resource = 10,
936 .num_resource = 2,
937 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
938 RESASG_SUBTYPE_UDMAP_RX_CHAN),
939 .host_id = HOST_ID_MCU_0_R5_1,
940 },
941 {
942 .start_resource = 12, 858 .start_resource = 12,
943 .num_resource = 2, 859 .num_resource = 2,
944 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 860 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
@@ -1061,13 +977,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1061 .host_id = HOST_ID_MCU_0_R5_0, 977 .host_id = HOST_ID_MCU_0_R5_0,
1062 }, 978 },
1063 { 979 {
1064 .start_resource = 10,
1065 .num_resource = 2,
1066 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1067 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1068 .host_id = HOST_ID_MCU_0_R5_1,
1069 },
1070 {
1071 .start_resource = 12, 980 .start_resource = 12,
1072 .num_resource = 2, 981 .num_resource = 2,
1073 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 982 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
@@ -1204,13 +1113,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1204 .host_id = HOST_ID_MCU_0_R5_0, 1113 .host_id = HOST_ID_MCU_0_R5_0,
1205 }, 1114 },
1206 { 1115 {
1207 .start_resource = 400,
1208 .num_resource = 4,
1209 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
1210 RESASG_SUBTYPE_IR_OUTPUT),
1211 .host_id = HOST_ID_MCU_0_R5_1,
1212 },
1213 {
1214 .start_resource = 404, 1116 .start_resource = 404,
1215 .num_resource = 4, 1117 .num_resource = 4,
1216 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0, 1118 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
@@ -1240,13 +1142,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1240 .host_id = HOST_ID_MCU_0_R5_0, 1142 .host_id = HOST_ID_MCU_0_R5_0,
1241 }, 1143 },
1242 { 1144 {
1243 .start_resource = 63,
1244 .num_resource = 64,
1245 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1246 RESASG_SUBTYPE_IA_VINT),
1247 .host_id = HOST_ID_MCU_0_R5_1,
1248 },
1249 {
1250 .start_resource = 127, 1145 .start_resource = 127,
1251 .num_resource = 32, 1146 .num_resource = 32,
1252 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1147 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
@@ -1297,13 +1192,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1297 .host_id = HOST_ID_MCU_0_R5_0, 1192 .host_id = HOST_ID_MCU_0_R5_0,
1298 }, 1193 },
1299 { 1194 {
1300 .start_resource = 16655,
1301 .num_resource = 256,
1302 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1303 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1304 .host_id = HOST_ID_MCU_0_R5_1,
1305 },
1306 {
1307 .start_resource = 16911, 1195 .start_resource = 16911,
1308 .num_resource = 128, 1196 .num_resource = 128,
1309 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1197 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
@@ -1354,13 +1242,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1354 .host_id = HOST_ID_MCU_0_R5_0, 1242 .host_id = HOST_ID_MCU_0_R5_0,
1355 }, 1243 },
1356 { 1244 {
1357 .start_resource = 13,
1358 .num_resource = 16,
1359 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1360 RESASG_SUBTYPE_PROXY_PROXIES),
1361 .host_id = HOST_ID_MCU_0_R5_1,
1362 },
1363 {
1364 .start_resource = 29, 1245 .start_resource = 29,
1365 .num_resource = 16, 1246 .num_resource = 16,
1366 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0, 1247 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
@@ -1419,13 +1300,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1419 .host_id = HOST_ID_MCU_0_R5_0, 1300 .host_id = HOST_ID_MCU_0_R5_0,
1420 }, 1301 },
1421 { 1302 {
1422 .start_resource = 144,
1423 .num_resource = 32,
1424 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1425 RESASG_SUBTYPE_RA_GP),
1426 .host_id = HOST_ID_MCU_0_R5_1,
1427 },
1428 {
1429 .start_resource = 176, 1303 .start_resource = 176,
1430 .num_resource = 32, 1304 .num_resource = 32,
1431 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1305 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1476,13 +1350,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1476 .host_id = HOST_ID_MCU_0_R5_0, 1350 .host_id = HOST_ID_MCU_0_R5_0,
1477 }, 1351 },
1478 { 1352 {
1479 .start_resource = 55,
1480 .num_resource = 2,
1481 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1482 RESASG_SUBTYPE_RA_UDMAP_RX),
1483 .host_id = HOST_ID_MCU_0_R5_1,
1484 },
1485 {
1486 .start_resource = 57, 1353 .start_resource = 57,
1487 .num_resource = 2, 1354 .num_resource = 2,
1488 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1355 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1525,13 +1392,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1525 .host_id = HOST_ID_MCU_0_R5_0, 1392 .host_id = HOST_ID_MCU_0_R5_0,
1526 }, 1393 },
1527 { 1394 {
1528 .start_resource = 76,
1529 .num_resource = 4,
1530 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1531 RESASG_SUBTYPE_RA_UDMAP_RX),
1532 .host_id = HOST_ID_MCU_0_R5_1,
1533 },
1534 {
1535 .start_resource = 80, 1395 .start_resource = 80,
1536 .num_resource = 4, 1396 .num_resource = 4,
1537 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1397 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1582,13 +1442,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1582 .host_id = HOST_ID_MCU_0_R5_0, 1442 .host_id = HOST_ID_MCU_0_R5_0,
1583 }, 1443 },
1584 { 1444 {
1585 .start_resource = 7,
1586 .num_resource = 2,
1587 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1588 RESASG_SUBTYPE_RA_UDMAP_TX),
1589 .host_id = HOST_ID_MCU_0_R5_1,
1590 },
1591 {
1592 .start_resource = 9, 1445 .start_resource = 9,
1593 .num_resource = 2, 1446 .num_resource = 2,
1594 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1447 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1631,13 +1484,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1631 .host_id = HOST_ID_MCU_0_R5_0, 1484 .host_id = HOST_ID_MCU_0_R5_0,
1632 }, 1485 },
1633 { 1486 {
1634 .start_resource = 28,
1635 .num_resource = 4,
1636 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1637 RESASG_SUBTYPE_RA_UDMAP_TX),
1638 .host_id = HOST_ID_MCU_0_R5_1,
1639 },
1640 {
1641 .start_resource = 32, 1487 .start_resource = 32,
1642 .num_resource = 4, 1488 .num_resource = 4,
1643 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1489 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1678,13 +1524,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1678 .num_resource = 0, 1524 .num_resource = 0,
1679 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1525 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1680 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1526 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1681 .host_id = HOST_ID_MCU_0_R5_1,
1682 },
1683 {
1684 .start_resource = 48,
1685 .num_resource = 0,
1686 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1687 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1688 .host_id = HOST_ID_A72_2, 1527 .host_id = HOST_ID_A72_2,
1689 }, 1528 },
1690 { 1529 {
@@ -1701,13 +1540,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1701 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1540 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1702 .host_id = HOST_ID_MCU_0_R5_0, 1541 .host_id = HOST_ID_MCU_0_R5_0,
1703 }, 1542 },
1704 {
1705 .start_resource = 49,
1706 .num_resource = 1,
1707 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1708 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1709 .host_id = HOST_ID_MCU_0_R5_1,
1710 },
1711 /* MCU NAVSS Rings for High capacity Tx channels */ 1543 /* MCU NAVSS Rings for High capacity Tx channels */
1712 { 1544 {
1713 .start_resource = 0, 1545 .start_resource = 0,
@@ -1721,13 +1553,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1721 .num_resource = 0, 1553 .num_resource = 0,
1722 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1554 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1723 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1555 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1724 .host_id = HOST_ID_MCU_0_R5_1,
1725 },
1726 {
1727 .start_resource = 0,
1728 .num_resource = 0,
1729 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1730 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1731 .host_id = HOST_ID_A72_2, 1556 .host_id = HOST_ID_A72_2,
1732 }, 1557 },
1733 { 1558 {
@@ -1744,13 +1569,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1744 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1569 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1745 .host_id = HOST_ID_MCU_0_R5_0, 1570 .host_id = HOST_ID_MCU_0_R5_0,
1746 }, 1571 },
1747 {
1748 .start_resource = 1,
1749 .num_resource = 1,
1750 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1751 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1752 .host_id = HOST_ID_MCU_0_R5_1,
1753 },
1754 /* MCU NAVSS Ring accelerator virt_id range */ 1572 /* MCU NAVSS Ring accelerator virt_id range */
1755 { 1573 {
1756 .start_resource = 2, 1574 .start_resource = 2,
@@ -1789,13 +1607,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1789 .host_id = HOST_ID_MCU_0_R5_0, 1607 .host_id = HOST_ID_MCU_0_R5_0,
1790 }, 1608 },
1791 { 1609 {
1792 .start_resource = 5,
1793 .num_resource = 6,
1794 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1795 RESASG_SUBTYPE_RA_MONITORS),
1796 .host_id = HOST_ID_MCU_0_R5_1,
1797 },
1798 {
1799 .start_resource = 11, 1610 .start_resource = 11,
1800 .num_resource = 6, 1611 .num_resource = 6,
1801 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1612 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
@@ -1846,13 +1657,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1846 .host_id = HOST_ID_MCU_0_R5_0, 1657 .host_id = HOST_ID_MCU_0_R5_0,
1847 }, 1658 },
1848 { 1659 {
1849 .start_resource = 60,
1850 .num_resource = 8,
1851 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1852 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1853 .host_id = HOST_ID_MCU_0_R5_1,
1854 },
1855 {
1856 .start_resource = 68, 1660 .start_resource = 68,
1857 .num_resource = 4, 1661 .num_resource = 4,
1858 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1662 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
@@ -1927,13 +1731,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1927 .host_id = HOST_ID_MCU_0_R5_0, 1731 .host_id = HOST_ID_MCU_0_R5_0,
1928 }, 1732 },
1929 { 1733 {
1930 .start_resource = 7,
1931 .num_resource = 2,
1932 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1933 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1934 .host_id = HOST_ID_MCU_0_R5_1,
1935 },
1936 {
1937 .start_resource = 9, 1734 .start_resource = 9,
1938 .num_resource = 2, 1735 .num_resource = 2,
1939 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1736 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
@@ -1976,13 +1773,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1976 .host_id = HOST_ID_MCU_0_R5_0, 1773 .host_id = HOST_ID_MCU_0_R5_0,
1977 }, 1774 },
1978 { 1775 {
1979 .start_resource = 28,
1980 .num_resource = 4,
1981 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1982 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1983 .host_id = HOST_ID_MCU_0_R5_1,
1984 },
1985 {
1986 .start_resource = 32, 1776 .start_resource = 32,
1987 .num_resource = 4, 1777 .num_resource = 4,
1988 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1778 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
@@ -2023,13 +1813,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2023 .num_resource = 0, 1813 .num_resource = 0,
2024 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1814 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2025 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1815 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2026 .host_id = HOST_ID_MCU_0_R5_1,
2027 },
2028 {
2029 .start_resource = 0,
2030 .num_resource = 0,
2031 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2032 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2033 .host_id = HOST_ID_A72_2, 1816 .host_id = HOST_ID_A72_2,
2034 }, 1817 },
2035 { 1818 {
@@ -2046,13 +1829,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2046 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1829 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2047 .host_id = HOST_ID_MCU_0_R5_0, 1830 .host_id = HOST_ID_MCU_0_R5_0,
2048 }, 1831 },
2049 {
2050 .start_resource = 1,
2051 .num_resource = 1,
2052 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2053 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2054 .host_id = HOST_ID_MCU_0_R5_1,
2055 },
2056 /* MCU NAVSS UDMA Normal capacity Tx channels */ 1832 /* MCU NAVSS UDMA Normal capacity Tx channels */
2057 { 1833 {
2058 .start_resource = 2, 1834 .start_resource = 2,
@@ -2076,13 +1852,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2076 .host_id = HOST_ID_MCU_0_R5_0, 1852 .host_id = HOST_ID_MCU_0_R5_0,
2077 }, 1853 },
2078 { 1854 {
2079 .start_resource = 7,
2080 .num_resource = 2,
2081 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2082 RESASG_SUBTYPE_UDMAP_TX_CHAN),
2083 .host_id = HOST_ID_MCU_0_R5_1,
2084 },
2085 {
2086 .start_resource = 9, 1855 .start_resource = 9,
2087 .num_resource = 2, 1856 .num_resource = 2,
2088 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1857 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
@@ -2125,13 +1894,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2125 .host_id = HOST_ID_MCU_0_R5_0, 1894 .host_id = HOST_ID_MCU_0_R5_0,
2126 }, 1895 },
2127 { 1896 {
2128 .start_resource = 28,
2129 .num_resource = 4,
2130 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2131 RESASG_SUBTYPE_UDMAP_TX_CHAN),
2132 .host_id = HOST_ID_MCU_0_R5_1,
2133 },
2134 {
2135 .start_resource = 32, 1897 .start_resource = 32,
2136 .num_resource = 4, 1898 .num_resource = 4,
2137 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1899 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
@@ -2172,13 +1934,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2172 .num_resource = 0, 1934 .num_resource = 0,
2173 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1935 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2174 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 1936 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2175 .host_id = HOST_ID_MCU_0_R5_1,
2176 },
2177 {
2178 .start_resource = 0,
2179 .num_resource = 0,
2180 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2181 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2182 .host_id = HOST_ID_A72_2, 1937 .host_id = HOST_ID_A72_2,
2183 }, 1938 },
2184 { 1939 {
@@ -2195,13 +1950,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2195 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 1950 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2196 .host_id = HOST_ID_MCU_0_R5_0, 1951 .host_id = HOST_ID_MCU_0_R5_0,
2197 }, 1952 },
2198 {
2199 .start_resource = 1,
2200 .num_resource = 1,
2201 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2202 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2203 .host_id = HOST_ID_MCU_0_R5_1,
2204 },
2205 /* MCU NAVSS Interrupt router */ 1953 /* MCU NAVSS Interrupt router */
2206 { 1954 {
2207 .start_resource = 11, 1955 .start_resource = 11,
@@ -2211,13 +1959,6 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
2211 .host_id = HOST_ID_MCU_0_R5_0, 1959 .host_id = HOST_ID_MCU_0_R5_0,
2212 }, 1960 },
2213 { 1961 {
2214 .start_resource = 11,
2215 .num_resource = 20,
2216 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
2217 RESASG_SUBTYPE_IR_OUTPUT),
2218 .host_id = HOST_ID_MCU_0_R5_1,
2219 },
2220 {
2221 .start_resource = 36, 1962 .start_resource = 36,
2222 .num_resource = 28, 1963 .num_resource = 28,
2223 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0, 1964 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
diff --git a/soc/j7200/evm/sysfw_img_cfg.h b/soc/j7200/evm/sysfw_img_cfg.h
index 87a6d8b..79843e7 100644
--- a/soc/j7200/evm/sysfw_img_cfg.h
+++ b/soc/j7200/evm/sysfw_img_cfg.h
@@ -3,7 +3,7 @@
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * 5 *
6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 293 40#define BOARDCFG_RM_RESASG_ENTRIES 256
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */
diff --git a/soc/j721e/evm/rm-cfg.c b/soc/j721e/evm/rm-cfg.c
index fef44aa..71537ed 100644
--- a/soc/j721e/evm/rm-cfg.c
+++ b/soc/j721e/evm/rm-cfg.c
@@ -2,7 +2,7 @@
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -193,13 +193,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
193 .host_id = HOST_ID_MCU_0_R5_0, 193 .host_id = HOST_ID_MCU_0_R5_0,
194 }, 194 },
195 { 195 {
196 .start_resource = 0,
197 .num_resource = 32,
198 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_LVL_INTRTR0,
199 RESASG_SUBTYPE_IR_OUTPUT),
200 .host_id = HOST_ID_MCU_0_R5_1,
201 },
202 {
203 .start_resource = 32, 196 .start_resource = 32,
204 .num_resource = 32, 197 .num_resource = 32,
205 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_LVL_INTRTR0, 198 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_LVL_INTRTR0,
@@ -215,13 +208,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
215 .host_id = HOST_ID_MCU_0_R5_0, 208 .host_id = HOST_ID_MCU_0_R5_0,
216 }, 209 },
217 { 210 {
218 .start_resource = 0,
219 .num_resource = 24,
220 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_PLS_INTRTR0,
221 RESASG_SUBTYPE_IR_OUTPUT),
222 .host_id = HOST_ID_MCU_0_R5_1,
223 },
224 {
225 .start_resource = 24, 211 .start_resource = 24,
226 .num_resource = 24, 212 .num_resource = 24,
227 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_PLS_INTRTR0, 213 .type = RESASG_UTYPE (J721E_DEV_MAIN2MCU_PLS_INTRTR0,
@@ -237,13 +223,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
237 .host_id = HOST_ID_MCU_0_R5_0, 223 .host_id = HOST_ID_MCU_0_R5_0,
238 }, 224 },
239 { 225 {
240 .start_resource = 0,
241 .num_resource = 8,
242 .type = RESASG_UTYPE (J721E_DEV_GPIOMUX_INTRTR0,
243 RESASG_SUBTYPE_IR_OUTPUT),
244 .host_id = HOST_ID_MCU_0_R5_1,
245 },
246 {
247 .start_resource = 8, 226 .start_resource = 8,
248 .num_resource = 8, 227 .num_resource = 8,
249 .type = RESASG_UTYPE (J721E_DEV_GPIOMUX_INTRTR0, 228 .type = RESASG_UTYPE (J721E_DEV_GPIOMUX_INTRTR0,
@@ -353,13 +332,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
353 .host_id = HOST_ID_MCU_0_R5_0, 332 .host_id = HOST_ID_MCU_0_R5_0,
354 }, 333 },
355 { 334 {
356 .start_resource = 0,
357 .num_resource = 8,
358 .type = RESASG_UTYPE (J721E_DEV_WKUP_GPIOMUX_INTRTR0,
359 RESASG_SUBTYPE_IR_OUTPUT),
360 .host_id = HOST_ID_MCU_0_R5_1,
361 },
362 {
363 .start_resource = 8, 335 .start_resource = 8,
364 .num_resource = 8, 336 .num_resource = 8,
365 .type = RESASG_UTYPE (J721E_DEV_WKUP_GPIOMUX_INTRTR0, 337 .type = RESASG_UTYPE (J721E_DEV_WKUP_GPIOMUX_INTRTR0,
@@ -520,13 +492,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
520 .host_id = HOST_ID_MCU_0_R5_0, 492 .host_id = HOST_ID_MCU_0_R5_0,
521 }, 493 },
522 { 494 {
523 .start_resource = 1574,
524 .num_resource = 32,
525 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
526 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
527 .host_id = HOST_ID_MCU_0_R5_1,
528 },
529 {
530 .start_resource = 1606, 495 .start_resource = 1606,
531 .num_resource = 32, 496 .num_resource = 32,
532 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0, 497 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
@@ -612,13 +577,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
612 .host_id = HOST_ID_MCU_0_R5_0, 577 .host_id = HOST_ID_MCU_0_R5_0,
613 }, 578 },
614 { 579 {
615 .start_resource = 8,
616 .num_resource = 4,
617 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_PROXY_0,
618 RESASG_SUBTYPE_PROXY_PROXIES),
619 .host_id = HOST_ID_MCU_0_R5_1,
620 },
621 {
622 .start_resource = 12, 580 .start_resource = 12,
623 .num_resource = 4, 581 .num_resource = 4,
624 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_PROXY_0, 582 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_PROXY_0,
@@ -712,13 +670,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
712 .host_id = HOST_ID_MCU_0_R5_0, 670 .host_id = HOST_ID_MCU_0_R5_0,
713 }, 671 },
714 { 672 {
715 .start_resource = 630,
716 .num_resource = 6,
717 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
718 RESASG_SUBTYPE_RA_GP),
719 .host_id = HOST_ID_MCU_0_R5_1,
720 },
721 {
722 .start_resource = 636, 673 .start_resource = 636,
723 .num_resource = 6, 674 .num_resource = 6,
724 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 675 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
@@ -798,13 +749,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
798 }, 749 },
799 { 750 {
800 .start_resource = 324, 751 .start_resource = 324,
801 .num_resource = 2,
802 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
803 RESASG_SUBTYPE_RA_UDMAP_RX),
804 .host_id = HOST_ID_MCU_0_R5_1,
805 },
806 {
807 .start_resource = 324,
808 .num_resource = 0, 752 .num_resource = 0,
809 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 753 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
810 RESASG_SUBTYPE_RA_UDMAP_RX), 754 RESASG_SUBTYPE_RA_UDMAP_RX),
@@ -946,13 +890,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
946 }, 890 },
947 { 891 {
948 .start_resource = 24, 892 .start_resource = 24,
949 .num_resource = 2,
950 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
951 RESASG_SUBTYPE_RA_UDMAP_TX),
952 .host_id = HOST_ID_MCU_0_R5_1,
953 },
954 {
955 .start_resource = 24,
956 .num_resource = 0, 893 .num_resource = 0,
957 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 894 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
958 RESASG_SUBTYPE_RA_UDMAP_TX), 895 RESASG_SUBTYPE_RA_UDMAP_TX),
@@ -1268,13 +1205,13 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1268 /* Main NAVSS Ring accelerator virt_id range */ 1205 /* Main NAVSS Ring accelerator virt_id range */
1269 { 1206 {
1270 .start_resource = 2, 1207 .start_resource = 2,
1271 .num_resource = 1, 1208 .num_resource = 5,
1272 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 1209 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1273 RESASG_SUBTYPE_RA_VIRTID), 1210 RESASG_SUBTYPE_RA_VIRTID),
1274 .host_id = HOST_ID_A72_2, 1211 .host_id = HOST_ID_A72_2,
1275 }, 1212 },
1276 { 1213 {
1277 .start_resource = 3, 1214 .start_resource = 7,
1278 .num_resource = 1, 1215 .num_resource = 1,
1279 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 1216 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1280 RESASG_SUBTYPE_RA_VIRTID), 1217 RESASG_SUBTYPE_RA_VIRTID),
@@ -1303,13 +1240,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1303 .host_id = HOST_ID_MCU_0_R5_0, 1240 .host_id = HOST_ID_MCU_0_R5_0,
1304 }, 1241 },
1305 { 1242 {
1306 .start_resource = 5,
1307 .num_resource = 1,
1308 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1309 RESASG_SUBTYPE_RA_MONITORS),
1310 .host_id = HOST_ID_MCU_0_R5_1,
1311 },
1312 {
1313 .start_resource = 6, 1243 .start_resource = 6,
1314 .num_resource = 1, 1244 .num_resource = 1,
1315 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 1245 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
@@ -1435,13 +1365,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1435 }, 1365 },
1436 { 1366 {
1437 .start_resource = 24, 1367 .start_resource = 24,
1438 .num_resource = 2,
1439 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1440 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1441 .host_id = HOST_ID_MCU_0_R5_1,
1442 },
1443 {
1444 .start_resource = 24,
1445 .num_resource = 0, 1368 .num_resource = 0,
1446 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0, 1369 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1447 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1370 RESASG_SUBTYPE_UDMAP_RX_CHAN),
@@ -1648,13 +1571,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1648 }, 1571 },
1649 { 1572 {
1650 .start_resource = 24, 1573 .start_resource = 24,
1651 .num_resource = 2,
1652 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1653 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1654 .host_id = HOST_ID_MCU_0_R5_1,
1655 },
1656 {
1657 .start_resource = 24,
1658 .num_resource = 0, 1574 .num_resource = 0,
1659 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0, 1575 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1660 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1576 RESASG_SUBTYPE_UDMAP_TX_CHAN),
@@ -1974,13 +1890,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1974 .host_id = HOST_ID_MCU_0_R5_0, 1890 .host_id = HOST_ID_MCU_0_R5_0,
1975 }, 1891 },
1976 { 1892 {
1977 .start_resource = 400,
1978 .num_resource = 4,
1979 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
1980 RESASG_SUBTYPE_IR_OUTPUT),
1981 .host_id = HOST_ID_MCU_0_R5_1,
1982 },
1983 {
1984 .start_resource = 404, 1893 .start_resource = 404,
1985 .num_resource = 4, 1894 .num_resource = 4,
1986 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0, 1895 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
@@ -2010,13 +1919,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2010 .host_id = HOST_ID_MCU_0_R5_0, 1919 .host_id = HOST_ID_MCU_0_R5_0,
2011 }, 1920 },
2012 { 1921 {
2013 .start_resource = 64,
2014 .num_resource = 64,
2015 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0,
2016 RESASG_SUBTYPE_IA_VINT),
2017 .host_id = HOST_ID_MCU_0_R5_1,
2018 },
2019 {
2020 .start_resource = 128, 1922 .start_resource = 128,
2021 .num_resource = 4, 1923 .num_resource = 4,
2022 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0, 1924 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0,
@@ -2102,13 +2004,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2102 .host_id = HOST_ID_MCU_0_R5_0, 2004 .host_id = HOST_ID_MCU_0_R5_0,
2103 }, 2005 },
2104 { 2006 {
2105 .start_resource = 16656,
2106 .num_resource = 256,
2107 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0,
2108 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
2109 .host_id = HOST_ID_MCU_0_R5_1,
2110 },
2111 {
2112 .start_resource = 16912, 2007 .start_resource = 16912,
2113 .num_resource = 64, 2008 .num_resource = 64,
2114 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0, 2009 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0,
@@ -2194,13 +2089,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2194 .host_id = HOST_ID_MCU_0_R5_0, 2089 .host_id = HOST_ID_MCU_0_R5_0,
2195 }, 2090 },
2196 { 2091 {
2197 .start_resource = 9,
2198 .num_resource = 4,
2199 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_PROXY0,
2200 RESASG_SUBTYPE_PROXY_PROXIES),
2201 .host_id = HOST_ID_MCU_0_R5_1,
2202 },
2203 {
2204 .start_resource = 13, 2092 .start_resource = 13,
2205 .num_resource = 4, 2093 .num_resource = 4,
2206 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_PROXY0, 2094 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_PROXY0,
@@ -2294,13 +2182,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2294 .host_id = HOST_ID_MCU_0_R5_0, 2182 .host_id = HOST_ID_MCU_0_R5_0,
2295 }, 2183 },
2296 { 2184 {
2297 .start_resource = 124,
2298 .num_resource = 32,
2299 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2300 RESASG_SUBTYPE_RA_GP),
2301 .host_id = HOST_ID_MCU_0_R5_1,
2302 },
2303 {
2304 .start_resource = 156, 2185 .start_resource = 156,
2305 .num_resource = 12, 2186 .num_resource = 12,
2306 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2187 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
@@ -2380,13 +2261,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2380 }, 2261 },
2381 { 2262 {
2382 .start_resource = 54, 2263 .start_resource = 54,
2383 .num_resource = 2,
2384 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2385 RESASG_SUBTYPE_RA_UDMAP_RX),
2386 .host_id = HOST_ID_MCU_0_R5_1,
2387 },
2388 {
2389 .start_resource = 54,
2390 .num_resource = 0, 2264 .num_resource = 0,
2391 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2265 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2392 RESASG_SUBTYPE_RA_UDMAP_RX), 2266 RESASG_SUBTYPE_RA_UDMAP_RX),
@@ -2470,13 +2344,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2470 .host_id = HOST_ID_MCU_0_R5_0, 2344 .host_id = HOST_ID_MCU_0_R5_0,
2471 }, 2345 },
2472 { 2346 {
2473 .start_resource = 78,
2474 .num_resource = 3,
2475 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2476 RESASG_SUBTYPE_RA_UDMAP_RX),
2477 .host_id = HOST_ID_MCU_0_R5_1,
2478 },
2479 {
2480 .start_resource = 81, 2347 .start_resource = 81,
2481 .num_resource = 2, 2348 .num_resource = 2,
2482 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2349 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
@@ -2556,13 +2423,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2556 }, 2423 },
2557 { 2424 {
2558 .start_resource = 6, 2425 .start_resource = 6,
2559 .num_resource = 2,
2560 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2561 RESASG_SUBTYPE_RA_UDMAP_TX),
2562 .host_id = HOST_ID_MCU_0_R5_1,
2563 },
2564 {
2565 .start_resource = 6,
2566 .num_resource = 0, 2426 .num_resource = 0,
2567 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2427 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2568 RESASG_SUBTYPE_RA_UDMAP_TX), 2428 RESASG_SUBTYPE_RA_UDMAP_TX),
@@ -2646,13 +2506,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2646 .host_id = HOST_ID_MCU_0_R5_0, 2506 .host_id = HOST_ID_MCU_0_R5_0,
2647 }, 2507 },
2648 { 2508 {
2649 .start_resource = 30,
2650 .num_resource = 3,
2651 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2652 RESASG_SUBTYPE_RA_UDMAP_TX),
2653 .host_id = HOST_ID_MCU_0_R5_1,
2654 },
2655 {
2656 .start_resource = 33, 2509 .start_resource = 33,
2657 .num_resource = 2, 2510 .num_resource = 2,
2658 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2511 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
@@ -2730,20 +2583,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2730 RESASG_SUBTYPE_RA_UDMAP_RX_H), 2583 RESASG_SUBTYPE_RA_UDMAP_RX_H),
2731 .host_id = HOST_ID_MCU_0_R5_0, 2584 .host_id = HOST_ID_MCU_0_R5_0,
2732 }, 2585 },
2733 {
2734 .start_resource = 48,
2735 .num_resource = 0,
2736 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2737 RESASG_SUBTYPE_RA_UDMAP_RX_H),
2738 .host_id = HOST_ID_MCU_0_R5_1,
2739 },
2740 {
2741 .start_resource = 48,
2742 .num_resource = 2,
2743 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2744 RESASG_SUBTYPE_RA_UDMAP_RX_H),
2745 .host_id = HOST_ID_MCU_0_R5_1,
2746 },
2747 /* MCU NAVSS Rings for High capacity Tx channels */ 2586 /* MCU NAVSS Rings for High capacity Tx channels */
2748 { 2587 {
2749 .start_resource = 0, 2588 .start_resource = 0,
@@ -2759,30 +2598,16 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2759 RESASG_SUBTYPE_RA_UDMAP_TX_H), 2598 RESASG_SUBTYPE_RA_UDMAP_TX_H),
2760 .host_id = HOST_ID_MCU_0_R5_0, 2599 .host_id = HOST_ID_MCU_0_R5_0,
2761 }, 2600 },
2762 {
2763 .start_resource = 0,
2764 .num_resource = 0,
2765 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2766 RESASG_SUBTYPE_RA_UDMAP_TX_H),
2767 .host_id = HOST_ID_MCU_0_R5_1,
2768 },
2769 {
2770 .start_resource = 0,
2771 .num_resource = 2,
2772 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2773 RESASG_SUBTYPE_RA_UDMAP_TX_H),
2774 .host_id = HOST_ID_MCU_0_R5_1,
2775 },
2776 /* MCU NAVSS Ring accelerator virt_id range */ 2601 /* MCU NAVSS Ring accelerator virt_id range */
2777 { 2602 {
2778 .start_resource = 2, 2603 .start_resource = 2,
2779 .num_resource = 1, 2604 .num_resource = 5,
2780 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2605 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2781 RESASG_SUBTYPE_RA_VIRTID), 2606 RESASG_SUBTYPE_RA_VIRTID),
2782 .host_id = HOST_ID_A72_2, 2607 .host_id = HOST_ID_A72_2,
2783 }, 2608 },
2784 { 2609 {
2785 .start_resource = 3, 2610 .start_resource = 7,
2786 .num_resource = 1, 2611 .num_resource = 1,
2787 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2612 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2788 RESASG_SUBTYPE_RA_VIRTID), 2613 RESASG_SUBTYPE_RA_VIRTID),
@@ -2811,13 +2636,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2811 .host_id = HOST_ID_MCU_0_R5_0, 2636 .host_id = HOST_ID_MCU_0_R5_0,
2812 }, 2637 },
2813 { 2638 {
2814 .start_resource = 5,
2815 .num_resource = 3,
2816 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
2817 RESASG_SUBTYPE_RA_MONITORS),
2818 .host_id = HOST_ID_MCU_0_R5_1,
2819 },
2820 {
2821 .start_resource = 8, 2639 .start_resource = 8,
2822 .num_resource = 3, 2640 .num_resource = 3,
2823 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0, 2641 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC0,
@@ -2896,13 +2714,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2896 .host_id = HOST_ID_MCU_0_R5_0, 2714 .host_id = HOST_ID_MCU_0_R5_0,
2897 }, 2715 },
2898 { 2716 {
2899 .start_resource = 60,
2900 .num_resource = 8,
2901 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
2902 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
2903 .host_id = HOST_ID_MCU_0_R5_1,
2904 },
2905 {
2906 .start_resource = 68, 2717 .start_resource = 68,
2907 .num_resource = 4, 2718 .num_resource = 4,
2908 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0, 2719 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
@@ -2985,13 +2796,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2985 }, 2796 },
2986 { 2797 {
2987 .start_resource = 6, 2798 .start_resource = 6,
2988 .num_resource = 2,
2989 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
2990 RESASG_SUBTYPE_UDMAP_RX_CHAN),
2991 .host_id = HOST_ID_MCU_0_R5_1,
2992 },
2993 {
2994 .start_resource = 6,
2995 .num_resource = 0, 2799 .num_resource = 0,
2996 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0, 2800 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
2997 RESASG_SUBTYPE_UDMAP_RX_CHAN), 2801 RESASG_SUBTYPE_UDMAP_RX_CHAN),
@@ -3075,13 +2879,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3075 .host_id = HOST_ID_MCU_0_R5_0, 2879 .host_id = HOST_ID_MCU_0_R5_0,
3076 }, 2880 },
3077 { 2881 {
3078 .start_resource = 30,
3079 .num_resource = 3,
3080 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3081 RESASG_SUBTYPE_UDMAP_RX_CHAN),
3082 .host_id = HOST_ID_MCU_0_R5_1,
3083 },
3084 {
3085 .start_resource = 33, 2882 .start_resource = 33,
3086 .num_resource = 2, 2883 .num_resource = 2,
3087 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0, 2884 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
@@ -3159,20 +2956,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3159 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 2956 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
3160 .host_id = HOST_ID_MCU_0_R5_0, 2957 .host_id = HOST_ID_MCU_0_R5_0,
3161 }, 2958 },
3162 {
3163 .start_resource = 0,
3164 .num_resource = 0,
3165 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3166 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
3167 .host_id = HOST_ID_MCU_0_R5_1,
3168 },
3169 {
3170 .start_resource = 0,
3171 .num_resource = 2,
3172 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3173 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
3174 .host_id = HOST_ID_MCU_0_R5_1,
3175 },
3176 /* MCU NAVSS UDMA Normal capacity Tx channels */ 2959 /* MCU NAVSS UDMA Normal capacity Tx channels */
3177 { 2960 {
3178 .start_resource = 2, 2961 .start_resource = 2,
@@ -3190,13 +2973,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3190 }, 2973 },
3191 { 2974 {
3192 .start_resource = 6, 2975 .start_resource = 6,
3193 .num_resource = 2,
3194 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3195 RESASG_SUBTYPE_UDMAP_TX_CHAN),
3196 .host_id = HOST_ID_MCU_0_R5_1,
3197 },
3198 {
3199 .start_resource = 6,
3200 .num_resource = 0, 2976 .num_resource = 0,
3201 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0, 2977 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3202 RESASG_SUBTYPE_UDMAP_TX_CHAN), 2978 RESASG_SUBTYPE_UDMAP_TX_CHAN),
@@ -3280,13 +3056,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3280 .host_id = HOST_ID_MCU_0_R5_0, 3056 .host_id = HOST_ID_MCU_0_R5_0,
3281 }, 3057 },
3282 { 3058 {
3283 .start_resource = 30,
3284 .num_resource = 3,
3285 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3286 RESASG_SUBTYPE_UDMAP_TX_CHAN),
3287 .host_id = HOST_ID_MCU_0_R5_1,
3288 },
3289 {
3290 .start_resource = 33, 3059 .start_resource = 33,
3291 .num_resource = 2, 3060 .num_resource = 2,
3292 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0, 3061 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
@@ -3364,20 +3133,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3364 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 3133 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
3365 .host_id = HOST_ID_MCU_0_R5_0, 3134 .host_id = HOST_ID_MCU_0_R5_0,
3366 }, 3135 },
3367 {
3368 .start_resource = 0,
3369 .num_resource = 0,
3370 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3371 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
3372 .host_id = HOST_ID_MCU_0_R5_1,
3373 },
3374 {
3375 .start_resource = 0,
3376 .num_resource = 2,
3377 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
3378 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
3379 .host_id = HOST_ID_MCU_0_R5_1,
3380 },
3381 /* MCU NAVSS Interrupt router */ 3136 /* MCU NAVSS Interrupt router */
3382 { 3137 {
3383 .start_resource = 12, 3138 .start_resource = 12,
@@ -3387,13 +3142,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
3387 .host_id = HOST_ID_MCU_0_R5_0, 3142 .host_id = HOST_ID_MCU_0_R5_0,
3388 }, 3143 },
3389 { 3144 {
3390 .start_resource = 12,
3391 .num_resource = 20,
3392 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTR_0,
3393 RESASG_SUBTYPE_IR_OUTPUT),
3394 .host_id = HOST_ID_MCU_0_R5_1,
3395 },
3396 {
3397 .start_resource = 36, 3145 .start_resource = 36,
3398 .num_resource = 28, 3146 .num_resource = 28,
3399 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTR_0, 3147 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTR_0,
diff --git a/soc/j721e/evm/sysfw_img_cfg.h b/soc/j721e/evm/sysfw_img_cfg.h
index b0f6528..5bd33a4 100644
--- a/soc/j721e/evm/sysfw_img_cfg.h
+++ b/soc/j721e/evm/sysfw_img_cfg.h
@@ -3,7 +3,7 @@
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * 5 *
6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 454 40#define BOARDCFG_RM_RESASG_ENTRIES 418
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */