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authorNikhil Devshatwar2020-08-11 16:33:04 -0500
committerDave Gerlach2020-08-14 12:11:07 -0500
commitc0768f96f248ec6a001d2e5fbac574e6de60e7f5 (patch)
tree3358e3925df45f857ef8226f6348e6f69627ba40
parentce61f3b2f893d4cc08bc64332f2027d62133bbcb (diff)
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soc: j7200: rm-cfg: Auto generate from host-tools
Auto generated from the host-tools with: Commit ID: 1f48ea8844cff145d6b12fee3d8a0b19e0602a66 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
-rw-r--r--soc/j7200/evm/rm-cfg.c1610
-rw-r--r--soc/j7200/evm/sysfw_img_cfg.h6
2 files changed, 1613 insertions, 3 deletions
diff --git a/soc/j7200/evm/rm-cfg.c b/soc/j7200/evm/rm-cfg.c
index 96d2270..24db2c9 100644
--- a/soc/j7200/evm/rm-cfg.c
+++ b/soc/j7200/evm/rm-cfg.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
3 * 4 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 * 6 *
@@ -51,7 +52,56 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
51 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM, 52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
52 .size = sizeof (struct boardcfg_rm_host_cfg), 53 .size = sizeof (struct boardcfg_rm_host_cfg),
53 }, 54 },
54 .host_cfg_entries = {{0}}, 55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_MCU_0_R5_0,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_MCU_0_R5_2,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_A72_2,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 {
81 .host_id = HOST_ID_A72_3,
82 .allowed_atype = 0b101010,
83 .allowed_qos = 0xAAAA,
84 .allowed_orderid = 0xAAAAAAAA,
85 .allowed_priority = 0xAAAA,
86 .allowed_sched_priority = 0xAA,
87 },
88 {
89 .host_id = HOST_ID_MAIN_0_R5_0,
90 .allowed_atype = 0b101010,
91 .allowed_qos = 0xAAAA,
92 .allowed_orderid = 0xAAAAAAAA,
93 .allowed_priority = 0xAAAA,
94 .allowed_sched_priority = 0xAA,
95 },
96 {
97 .host_id = HOST_ID_MAIN_0_R5_2,
98 .allowed_atype = 0b101010,
99 .allowed_qos = 0xAAAA,
100 .allowed_orderid = 0xAAAAAAAA,
101 .allowed_priority = 0xAAAA,
102 .allowed_sched_priority = 0xAA,
103 },
104 }
55 }, 105 },
56 106
57 /* boardcfg_rm_resasg */ 107 /* boardcfg_rm_resasg */
@@ -70,5 +120,1563 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
70 120
71 /* This is actually part of .resasg */ 121 /* This is actually part of .resasg */
72 .resasg_entries = { 122 .resasg_entries = {
123 /* Main 2 MCU Level Interrupt router */
124 {
125 .start_resource = 0,
126 .num_resource = 32,
127 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0,
128 RESASG_SUBTYPE_IR_OUTPUT),
129 .host_id = HOST_ID_MCU_0_R5_0,
130 },
131 {
132 .start_resource = 0,
133 .num_resource = 32,
134 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0,
135 RESASG_SUBTYPE_IR_OUTPUT),
136 .host_id = HOST_ID_MCU_0_R5_1,
137 },
138 {
139 .start_resource = 32,
140 .num_resource = 32,
141 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_LVL_INTRTR0,
142 RESASG_SUBTYPE_IR_OUTPUT),
143 .host_id = HOST_ID_MCU_0_R5_2,
144 },
145 /* Main 2 MCU Pulse Interrupt router */
146 {
147 .start_resource = 0,
148 .num_resource = 24,
149 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0,
150 RESASG_SUBTYPE_IR_OUTPUT),
151 .host_id = HOST_ID_MCU_0_R5_0,
152 },
153 {
154 .start_resource = 0,
155 .num_resource = 24,
156 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0,
157 RESASG_SUBTYPE_IR_OUTPUT),
158 .host_id = HOST_ID_MCU_0_R5_1,
159 },
160 {
161 .start_resource = 24,
162 .num_resource = 24,
163 .type = RESASG_UTYPE (J7200_DEV_MAIN2MCU_PLS_INTRTR0,
164 RESASG_SUBTYPE_IR_OUTPUT),
165 .host_id = HOST_ID_MCU_0_R5_2,
166 },
167 /* Main GPIO Interrupt router */
168 {
169 .start_resource = 0,
170 .num_resource = 8,
171 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
172 RESASG_SUBTYPE_IR_OUTPUT),
173 .host_id = HOST_ID_MCU_0_R5_0,
174 },
175 {
176 .start_resource = 0,
177 .num_resource = 8,
178 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
179 RESASG_SUBTYPE_IR_OUTPUT),
180 .host_id = HOST_ID_MCU_0_R5_1,
181 },
182 {
183 .start_resource = 8,
184 .num_resource = 8,
185 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
186 RESASG_SUBTYPE_IR_OUTPUT),
187 .host_id = HOST_ID_MCU_0_R5_2,
188 },
189 {
190 .start_resource = 16,
191 .num_resource = 8,
192 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
193 RESASG_SUBTYPE_IR_OUTPUT),
194 .host_id = HOST_ID_MAIN_0_R5_0,
195 },
196 {
197 .start_resource = 24,
198 .num_resource = 8,
199 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
200 RESASG_SUBTYPE_IR_OUTPUT),
201 .host_id = HOST_ID_MAIN_0_R5_2,
202 },
203 {
204 .start_resource = 32,
205 .num_resource = 16,
206 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
207 RESASG_SUBTYPE_IR_OUTPUT),
208 .host_id = HOST_ID_A72_2,
209 },
210 {
211 .start_resource = 48,
212 .num_resource = 16,
213 .type = RESASG_UTYPE (J7200_DEV_GPIOMUX_INTRTR0,
214 RESASG_SUBTYPE_IR_OUTPUT),
215 .host_id = HOST_ID_A72_3,
216 },
217 /* Timesync Interrupt router */
218 {
219 .start_resource = 0,
220 .num_resource = 48,
221 .type = RESASG_UTYPE (J7200_DEV_TIMESYNC_INTRTR0,
222 RESASG_SUBTYPE_IR_OUTPUT),
223 .host_id = HOST_ID_ALL,
224 },
225 /* Wakeup GPIO Interrupt router */
226 {
227 .start_resource = 0,
228 .num_resource = 8,
229 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
230 RESASG_SUBTYPE_IR_OUTPUT),
231 .host_id = HOST_ID_MCU_0_R5_0,
232 },
233 {
234 .start_resource = 0,
235 .num_resource = 8,
236 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
237 RESASG_SUBTYPE_IR_OUTPUT),
238 .host_id = HOST_ID_MCU_0_R5_1,
239 },
240 {
241 .start_resource = 8,
242 .num_resource = 8,
243 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
244 RESASG_SUBTYPE_IR_OUTPUT),
245 .host_id = HOST_ID_MCU_0_R5_2,
246 },
247 {
248 .start_resource = 16,
249 .num_resource = 8,
250 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
251 RESASG_SUBTYPE_IR_OUTPUT),
252 .host_id = HOST_ID_A72_2,
253 },
254 {
255 .start_resource = 24,
256 .num_resource = 8,
257 .type = RESASG_UTYPE (J7200_DEV_WKUP_GPIOMUX_INTRTR0,
258 RESASG_SUBTYPE_IR_OUTPUT),
259 .host_id = HOST_ID_A72_3,
260 },
261 /* MODSS Interrupt aggregator0 Virtual intettupts */
262 {
263 .start_resource = 0,
264 .num_resource = 64,
265 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_MODSS_INTA_0,
266 RESASG_SUBTYPE_IA_VINT),
267 .host_id = HOST_ID_ALL,
268 },
269 /* MODSS Interrupt aggregator0 Global events */
270 {
271 .start_resource = 20480,
272 .num_resource = 1024,
273 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_MODSS_INTA_0,
274 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
275 .host_id = HOST_ID_ALL,
276 },
277 /* MODSS Interrupt aggregator1 Virtual intettupts */
278 {
279 .start_resource = 0,
280 .num_resource = 64,
281 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_MODSS_INTA_1,
282 RESASG_SUBTYPE_IA_VINT),
283 .host_id = HOST_ID_ALL,
284 },
285 /* MODSS Interrupt aggregator1 Global events */
286 {
287 .start_resource = 22528,
288 .num_resource = 1024,
289 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_MODSS_INTA_1,
290 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
291 .host_id = HOST_ID_ALL,
292 },
293 /* Main NAVSS UDMA Interrupt aggregator Virtual interrupts */
294 {
295 .start_resource = 18,
296 .num_resource = 86,
297 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
298 RESASG_SUBTYPE_IA_VINT),
299 .host_id = HOST_ID_A72_2,
300 },
301 {
302 .start_resource = 104,
303 .num_resource = 32,
304 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
305 RESASG_SUBTYPE_IA_VINT),
306 .host_id = HOST_ID_A72_3,
307 },
308 {
309 .start_resource = 136,
310 .num_resource = 8,
311 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
312 RESASG_SUBTYPE_IA_VINT),
313 .host_id = HOST_ID_MAIN_0_R5_0,
314 },
315 {
316 .start_resource = 144,
317 .num_resource = 24,
318 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
319 RESASG_SUBTYPE_IA_VINT),
320 .host_id = HOST_ID_MAIN_0_R5_2,
321 },
322 {
323 .start_resource = 168,
324 .num_resource = 88,
325 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
326 RESASG_SUBTYPE_IA_VINT),
327 .host_id = HOST_ID_ALL,
328 },
329 /* Main NAVSS UDMA Interrupt aggregator Global events */
330 {
331 .start_resource = 18,
332 .num_resource = 1024,
333 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
334 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
335 .host_id = HOST_ID_A72_2,
336 },
337 {
338 .start_resource = 1042,
339 .num_resource = 512,
340 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
341 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
342 .host_id = HOST_ID_A72_3,
343 },
344 {
345 .start_resource = 1554,
346 .num_resource = 32,
347 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
348 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
349 .host_id = HOST_ID_MCU_0_R5_0,
350 },
351 {
352 .start_resource = 1554,
353 .num_resource = 32,
354 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
355 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
356 .host_id = HOST_ID_MCU_0_R5_1,
357 },
358 {
359 .start_resource = 1586,
360 .num_resource = 32,
361 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
362 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
363 .host_id = HOST_ID_MCU_0_R5_2,
364 },
365 {
366 .start_resource = 1618,
367 .num_resource = 256,
368 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
369 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
370 .host_id = HOST_ID_MAIN_0_R5_0,
371 },
372 {
373 .start_resource = 1874,
374 .num_resource = 512,
375 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
376 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
377 .host_id = HOST_ID_MAIN_0_R5_2,
378 },
379 {
380 .start_resource = 2386,
381 .num_resource = 2222,
382 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMASS_INTA_0,
383 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
384 .host_id = HOST_ID_ALL,
385 },
386 /* Main NAVSS Non secure proxies */
387 {
388 .start_resource = 0,
389 .num_resource = 4,
390 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
391 RESASG_SUBTYPE_PROXY_PROXIES),
392 .host_id = HOST_ID_A72_2,
393 },
394 {
395 .start_resource = 4,
396 .num_resource = 4,
397 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
398 RESASG_SUBTYPE_PROXY_PROXIES),
399 .host_id = HOST_ID_A72_3,
400 },
401 {
402 .start_resource = 8,
403 .num_resource = 4,
404 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
405 RESASG_SUBTYPE_PROXY_PROXIES),
406 .host_id = HOST_ID_MCU_0_R5_0,
407 },
408 {
409 .start_resource = 8,
410 .num_resource = 4,
411 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
412 RESASG_SUBTYPE_PROXY_PROXIES),
413 .host_id = HOST_ID_MCU_0_R5_1,
414 },
415 {
416 .start_resource = 12,
417 .num_resource = 4,
418 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
419 RESASG_SUBTYPE_PROXY_PROXIES),
420 .host_id = HOST_ID_MCU_0_R5_2,
421 },
422 {
423 .start_resource = 16,
424 .num_resource = 8,
425 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
426 RESASG_SUBTYPE_PROXY_PROXIES),
427 .host_id = HOST_ID_MAIN_0_R5_0,
428 },
429 {
430 .start_resource = 24,
431 .num_resource = 8,
432 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
433 RESASG_SUBTYPE_PROXY_PROXIES),
434 .host_id = HOST_ID_MAIN_0_R5_2,
435 },
436 {
437 .start_resource = 32,
438 .num_resource = 32,
439 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_PROXY_0,
440 RESASG_SUBTYPE_PROXY_PROXIES),
441 .host_id = HOST_ID_ALL,
442 },
443 /* Main NAVSS Ringacc error event config */
444 {
445 .start_resource = 0,
446 .num_resource = 1,
447 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
448 RESASG_SUBTYPE_RA_ERROR_OES),
449 .host_id = HOST_ID_ALL,
450 },
451 /* Main NAVSS Ringacc Free rings */
452 {
453 .start_resource = 120,
454 .num_resource = 150,
455 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
456 RESASG_SUBTYPE_RA_GP),
457 .host_id = HOST_ID_A72_2,
458 },
459 {
460 .start_resource = 270,
461 .num_resource = 40,
462 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
463 RESASG_SUBTYPE_RA_GP),
464 .host_id = HOST_ID_A72_3,
465 },
466 {
467 .start_resource = 310,
468 .num_resource = 6,
469 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
470 RESASG_SUBTYPE_RA_GP),
471 .host_id = HOST_ID_MCU_0_R5_0,
472 },
473 {
474 .start_resource = 310,
475 .num_resource = 6,
476 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
477 RESASG_SUBTYPE_RA_GP),
478 .host_id = HOST_ID_MCU_0_R5_1,
479 },
480 {
481 .start_resource = 316,
482 .num_resource = 6,
483 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
484 RESASG_SUBTYPE_RA_GP),
485 .host_id = HOST_ID_MCU_0_R5_2,
486 },
487 {
488 .start_resource = 322,
489 .num_resource = 40,
490 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
491 RESASG_SUBTYPE_RA_GP),
492 .host_id = HOST_ID_MAIN_0_R5_0,
493 },
494 {
495 .start_resource = 362,
496 .num_resource = 182,
497 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
498 RESASG_SUBTYPE_RA_GP),
499 .host_id = HOST_ID_MAIN_0_R5_2,
500 },
501 {
502 .start_resource = 544,
503 .num_resource = 430,
504 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
505 RESASG_SUBTYPE_RA_GP),
506 .host_id = HOST_ID_ALL,
507 },
508 /* Main NAVSS Ringacc rings for Normal capacity Rx channels */
509 {
510 .start_resource = 64,
511 .num_resource = 24,
512 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
513 RESASG_SUBTYPE_RA_UDMAP_RX),
514 .host_id = HOST_ID_A72_2,
515 },
516 {
517 .start_resource = 88,
518 .num_resource = 10,
519 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
520 RESASG_SUBTYPE_RA_UDMAP_RX),
521 .host_id = HOST_ID_A72_3,
522 },
523 {
524 .start_resource = 98,
525 .num_resource = 2,
526 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
527 RESASG_SUBTYPE_RA_UDMAP_RX),
528 .host_id = HOST_ID_MCU_0_R5_0,
529 },
530 {
531 .start_resource = 98,
532 .num_resource = 2,
533 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
534 RESASG_SUBTYPE_RA_UDMAP_RX),
535 .host_id = HOST_ID_MCU_0_R5_1,
536 },
537 {
538 .start_resource = 100,
539 .num_resource = 2,
540 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
541 RESASG_SUBTYPE_RA_UDMAP_RX),
542 .host_id = HOST_ID_MCU_0_R5_2,
543 },
544 {
545 .start_resource = 102,
546 .num_resource = 7,
547 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
548 RESASG_SUBTYPE_RA_UDMAP_RX),
549 .host_id = HOST_ID_MAIN_0_R5_0,
550 },
551 {
552 .start_resource = 109,
553 .num_resource = 8,
554 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
555 RESASG_SUBTYPE_RA_UDMAP_RX),
556 .host_id = HOST_ID_MAIN_0_R5_2,
557 },
558 {
559 .start_resource = 117,
560 .num_resource = 3,
561 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
562 RESASG_SUBTYPE_RA_UDMAP_RX),
563 .host_id = HOST_ID_ALL,
564 },
565 /* Main NAVSS Ringacc rings for Normal capacity Tx channels */
566 {
567 .start_resource = 4,
568 .num_resource = 24,
569 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
570 RESASG_SUBTYPE_RA_UDMAP_TX),
571 .host_id = HOST_ID_A72_2,
572 },
573 {
574 .start_resource = 28,
575 .num_resource = 10,
576 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
577 RESASG_SUBTYPE_RA_UDMAP_TX),
578 .host_id = HOST_ID_A72_3,
579 },
580 {
581 .start_resource = 38,
582 .num_resource = 2,
583 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
584 RESASG_SUBTYPE_RA_UDMAP_TX),
585 .host_id = HOST_ID_MCU_0_R5_0,
586 },
587 {
588 .start_resource = 38,
589 .num_resource = 2,
590 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
591 RESASG_SUBTYPE_RA_UDMAP_TX),
592 .host_id = HOST_ID_MCU_0_R5_1,
593 },
594 {
595 .start_resource = 40,
596 .num_resource = 2,
597 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
598 RESASG_SUBTYPE_RA_UDMAP_TX),
599 .host_id = HOST_ID_MCU_0_R5_2,
600 },
601 {
602 .start_resource = 42,
603 .num_resource = 7,
604 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
605 RESASG_SUBTYPE_RA_UDMAP_TX),
606 .host_id = HOST_ID_MAIN_0_R5_0,
607 },
608 {
609 .start_resource = 49,
610 .num_resource = 8,
611 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
612 RESASG_SUBTYPE_RA_UDMAP_TX),
613 .host_id = HOST_ID_MAIN_0_R5_2,
614 },
615 {
616 .start_resource = 57,
617 .num_resource = 3,
618 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
619 RESASG_SUBTYPE_RA_UDMAP_TX),
620 .host_id = HOST_ID_ALL,
621 },
622 /* Main NAVSS Ringacc rings for High capacity Rx channels */
623 {
624 .start_resource = 62,
625 .num_resource = 2,
626 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
627 RESASG_SUBTYPE_RA_UDMAP_RX_H),
628 .host_id = HOST_ID_MAIN_0_R5_0,
629 },
630 /* Main NAVSS Ringacc rings for Ultra high capacity Rx channels */
631 {
632 .start_resource = 60,
633 .num_resource = 2,
634 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
635 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
636 .host_id = HOST_ID_MAIN_0_R5_2,
637 },
638 /* Main NAVSS Ringacc rings for High capacity Tx channels */
639 {
640 .start_resource = 2,
641 .num_resource = 2,
642 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
643 RESASG_SUBTYPE_RA_UDMAP_TX_H),
644 .host_id = HOST_ID_MAIN_0_R5_0,
645 },
646 /* Main NAVSS Ringacc rings for Ultra high capacity Tx channels */
647 {
648 .start_resource = 0,
649 .num_resource = 2,
650 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
651 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
652 .host_id = HOST_ID_MAIN_0_R5_2,
653 },
654 /* Main NAVSS Ringacc virt_id range */
655 {
656 .start_resource = 2,
657 .num_resource = 1,
658 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
659 RESASG_SUBTYPE_RA_VIRTID),
660 .host_id = HOST_ID_A72_2,
661 },
662 {
663 .start_resource = 3,
664 .num_resource = 1,
665 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
666 RESASG_SUBTYPE_RA_VIRTID),
667 .host_id = HOST_ID_A72_3,
668 },
669 /* Main NAVSS Ringacc ring monitors */
670 {
671 .start_resource = 0,
672 .num_resource = 3,
673 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
674 RESASG_SUBTYPE_RA_MONITORS),
675 .host_id = HOST_ID_A72_2,
676 },
677 {
678 .start_resource = 3,
679 .num_resource = 2,
680 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
681 RESASG_SUBTYPE_RA_MONITORS),
682 .host_id = HOST_ID_A72_3,
683 },
684 {
685 .start_resource = 5,
686 .num_resource = 1,
687 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
688 RESASG_SUBTYPE_RA_MONITORS),
689 .host_id = HOST_ID_MCU_0_R5_0,
690 },
691 {
692 .start_resource = 5,
693 .num_resource = 1,
694 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
695 RESASG_SUBTYPE_RA_MONITORS),
696 .host_id = HOST_ID_MCU_0_R5_1,
697 },
698 {
699 .start_resource = 6,
700 .num_resource = 1,
701 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
702 RESASG_SUBTYPE_RA_MONITORS),
703 .host_id = HOST_ID_MCU_0_R5_2,
704 },
705 {
706 .start_resource = 7,
707 .num_resource = 6,
708 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
709 RESASG_SUBTYPE_RA_MONITORS),
710 .host_id = HOST_ID_MAIN_0_R5_0,
711 },
712 {
713 .start_resource = 13,
714 .num_resource = 3,
715 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
716 RESASG_SUBTYPE_RA_MONITORS),
717 .host_id = HOST_ID_MAIN_0_R5_2,
718 },
719 {
720 .start_resource = 16,
721 .num_resource = 16,
722 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
723 RESASG_SUBTYPE_RA_MONITORS),
724 .host_id = HOST_ID_ALL,
725 },
726 /* Main NAVSS UDMA Rx free flows */
727 {
728 .start_resource = 60,
729 .num_resource = 8,
730 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
731 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
732 .host_id = HOST_ID_A72_2,
733 },
734 {
735 .start_resource = 68,
736 .num_resource = 8,
737 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
738 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
739 .host_id = HOST_ID_A72_3,
740 },
741 {
742 .start_resource = 76,
743 .num_resource = 64,
744 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
745 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
746 .host_id = HOST_ID_MAIN_0_R5_0,
747 },
748 {
749 .start_resource = 140,
750 .num_resource = 8,
751 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
752 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
753 .host_id = HOST_ID_MAIN_0_R5_2,
754 },
755 {
756 .start_resource = 148,
757 .num_resource = 2,
758 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
759 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
760 .host_id = HOST_ID_ALL,
761 },
762 /* Main NAVSS invalid flow event config */
763 {
764 .start_resource = 0,
765 .num_resource = 1,
766 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
767 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
768 .host_id = HOST_ID_ALL,
769 },
770 /* Main NAVSS UDMA global event trigger */
771 {
772 .start_resource = 49152,
773 .num_resource = 1024,
774 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
775 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
776 .host_id = HOST_ID_ALL,
777 },
778 /* Main NAVSS UDMA global config */
779 {
780 .start_resource = 0,
781 .num_resource = 1,
782 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
783 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
784 .host_id = HOST_ID_ALL,
785 },
786 /* Main NAVSS UDMA Normal capacity Rx channels */
787 {
788 .start_resource = 4,
789 .num_resource = 24,
790 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
791 RESASG_SUBTYPE_UDMAP_RX_CHAN),
792 .host_id = HOST_ID_A72_2,
793 },
794 {
795 .start_resource = 28,
796 .num_resource = 10,
797 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
798 RESASG_SUBTYPE_UDMAP_RX_CHAN),
799 .host_id = HOST_ID_A72_3,
800 },
801 {
802 .start_resource = 38,
803 .num_resource = 2,
804 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
805 RESASG_SUBTYPE_UDMAP_RX_CHAN),
806 .host_id = HOST_ID_MCU_0_R5_0,
807 },
808 {
809 .start_resource = 38,
810 .num_resource = 2,
811 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
812 RESASG_SUBTYPE_UDMAP_RX_CHAN),
813 .host_id = HOST_ID_MCU_0_R5_1,
814 },
815 {
816 .start_resource = 40,
817 .num_resource = 2,
818 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
819 RESASG_SUBTYPE_UDMAP_RX_CHAN),
820 .host_id = HOST_ID_MCU_0_R5_2,
821 },
822 {
823 .start_resource = 42,
824 .num_resource = 7,
825 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
826 RESASG_SUBTYPE_UDMAP_RX_CHAN),
827 .host_id = HOST_ID_MAIN_0_R5_0,
828 },
829 {
830 .start_resource = 49,
831 .num_resource = 8,
832 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
833 RESASG_SUBTYPE_UDMAP_RX_CHAN),
834 .host_id = HOST_ID_MAIN_0_R5_2,
835 },
836 {
837 .start_resource = 57,
838 .num_resource = 3,
839 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
840 RESASG_SUBTYPE_UDMAP_RX_CHAN),
841 .host_id = HOST_ID_ALL,
842 },
843 /* Main NAVSS UDMA High capacity Rx channels */
844 {
845 .start_resource = 2,
846 .num_resource = 2,
847 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
848 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
849 .host_id = HOST_ID_MAIN_0_R5_0,
850 },
851 /* Main NAVSS UDMA Ultra high capacity Rx channels */
852 {
853 .start_resource = 0,
854 .num_resource = 2,
855 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
856 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
857 .host_id = HOST_ID_MAIN_0_R5_2,
858 },
859 /* Main NAVSS UDMA Normal capacity Tx channels */
860 {
861 .start_resource = 4,
862 .num_resource = 24,
863 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
864 RESASG_SUBTYPE_UDMAP_TX_CHAN),
865 .host_id = HOST_ID_A72_2,
866 },
867 {
868 .start_resource = 28,
869 .num_resource = 10,
870 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
871 RESASG_SUBTYPE_UDMAP_TX_CHAN),
872 .host_id = HOST_ID_A72_3,
873 },
874 {
875 .start_resource = 38,
876 .num_resource = 2,
877 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
878 RESASG_SUBTYPE_UDMAP_TX_CHAN),
879 .host_id = HOST_ID_MCU_0_R5_0,
880 },
881 {
882 .start_resource = 38,
883 .num_resource = 2,
884 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
885 RESASG_SUBTYPE_UDMAP_TX_CHAN),
886 .host_id = HOST_ID_MCU_0_R5_1,
887 },
888 {
889 .start_resource = 40,
890 .num_resource = 2,
891 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
892 RESASG_SUBTYPE_UDMAP_TX_CHAN),
893 .host_id = HOST_ID_MCU_0_R5_2,
894 },
895 {
896 .start_resource = 42,
897 .num_resource = 7,
898 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
899 RESASG_SUBTYPE_UDMAP_TX_CHAN),
900 .host_id = HOST_ID_MAIN_0_R5_0,
901 },
902 {
903 .start_resource = 49,
904 .num_resource = 8,
905 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
906 RESASG_SUBTYPE_UDMAP_TX_CHAN),
907 .host_id = HOST_ID_MAIN_0_R5_2,
908 },
909 {
910 .start_resource = 57,
911 .num_resource = 3,
912 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
913 RESASG_SUBTYPE_UDMAP_TX_CHAN),
914 .host_id = HOST_ID_ALL,
915 },
916 /* Main NAVSS UDMA High capacity Tx channels */
917 {
918 .start_resource = 2,
919 .num_resource = 2,
920 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
921 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
922 .host_id = HOST_ID_MAIN_0_R5_0,
923 },
924 /* Main NAVSS UDMA Ultra high capacity Tx channels */
925 {
926 .start_resource = 0,
927 .num_resource = 2,
928 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
929 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
930 .host_id = HOST_ID_MAIN_0_R5_2,
931 },
932 /* Main NAVSS Interrupt router */
933 {
934 .start_resource = 10,
935 .num_resource = 128,
936 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
937 RESASG_SUBTYPE_IR_OUTPUT),
938 .host_id = HOST_ID_A72_2,
939 },
940 {
941 .start_resource = 138,
942 .num_resource = 54,
943 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
944 RESASG_SUBTYPE_IR_OUTPUT),
945 .host_id = HOST_ID_A72_3,
946 },
947 {
948 .start_resource = 196,
949 .num_resource = 28,
950 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
951 RESASG_SUBTYPE_IR_OUTPUT),
952 .host_id = HOST_ID_MAIN_0_R5_0,
953 },
954 {
955 .start_resource = 228,
956 .num_resource = 28,
957 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
958 RESASG_SUBTYPE_IR_OUTPUT),
959 .host_id = HOST_ID_MAIN_0_R5_2,
960 },
961 {
962 .start_resource = 400,
963 .num_resource = 4,
964 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
965 RESASG_SUBTYPE_IR_OUTPUT),
966 .host_id = HOST_ID_MCU_0_R5_0,
967 },
968 {
969 .start_resource = 400,
970 .num_resource = 4,
971 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
972 RESASG_SUBTYPE_IR_OUTPUT),
973 .host_id = HOST_ID_MCU_0_R5_1,
974 },
975 {
976 .start_resource = 404,
977 .num_resource = 4,
978 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_INTR_ROUTER_0,
979 RESASG_SUBTYPE_IR_OUTPUT),
980 .host_id = HOST_ID_MCU_0_R5_2,
981 },
982 /* MCU NAVSS Interrupt aggregator Virtual interrupts */
983 {
984 .start_resource = 8,
985 .num_resource = 32,
986 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
987 RESASG_SUBTYPE_IA_VINT),
988 .host_id = HOST_ID_A72_2,
989 },
990 {
991 .start_resource = 40,
992 .num_resource = 16,
993 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
994 RESASG_SUBTYPE_IA_VINT),
995 .host_id = HOST_ID_A72_3,
996 },
997 {
998 .start_resource = 56,
999 .num_resource = 64,
1000 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1001 RESASG_SUBTYPE_IA_VINT),
1002 .host_id = HOST_ID_MCU_0_R5_0,
1003 },
1004 {
1005 .start_resource = 56,
1006 .num_resource = 64,
1007 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1008 RESASG_SUBTYPE_IA_VINT),
1009 .host_id = HOST_ID_MCU_0_R5_1,
1010 },
1011 {
1012 .start_resource = 120,
1013 .num_resource = 4,
1014 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1015 RESASG_SUBTYPE_IA_VINT),
1016 .host_id = HOST_ID_MCU_0_R5_2,
1017 },
1018 {
1019 .start_resource = 124,
1020 .num_resource = 16,
1021 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1022 RESASG_SUBTYPE_IA_VINT),
1023 .host_id = HOST_ID_MAIN_0_R5_0,
1024 },
1025 {
1026 .start_resource = 140,
1027 .num_resource = 16,
1028 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1029 RESASG_SUBTYPE_IA_VINT),
1030 .host_id = HOST_ID_MAIN_0_R5_2,
1031 },
1032 {
1033 .start_resource = 156,
1034 .num_resource = 100,
1035 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1036 RESASG_SUBTYPE_IA_VINT),
1037 .host_id = HOST_ID_ALL,
1038 },
1039 /* MCU NAVSS Interrupt aggregator Global events */
1040 {
1041 .start_resource = 16392,
1042 .num_resource = 128,
1043 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1044 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1045 .host_id = HOST_ID_A72_2,
1046 },
1047 {
1048 .start_resource = 16520,
1049 .num_resource = 128,
1050 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1051 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1052 .host_id = HOST_ID_A72_3,
1053 },
1054 {
1055 .start_resource = 16648,
1056 .num_resource = 256,
1057 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1058 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1059 .host_id = HOST_ID_MCU_0_R5_0,
1060 },
1061 {
1062 .start_resource = 16648,
1063 .num_resource = 256,
1064 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1065 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1066 .host_id = HOST_ID_MCU_0_R5_1,
1067 },
1068 {
1069 .start_resource = 16904,
1070 .num_resource = 64,
1071 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1072 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1073 .host_id = HOST_ID_MCU_0_R5_2,
1074 },
1075 {
1076 .start_resource = 16968,
1077 .num_resource = 128,
1078 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1079 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1080 .host_id = HOST_ID_MAIN_0_R5_0,
1081 },
1082 {
1083 .start_resource = 17096,
1084 .num_resource = 128,
1085 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1086 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1087 .host_id = HOST_ID_MAIN_0_R5_2,
1088 },
1089 {
1090 .start_resource = 17224,
1091 .num_resource = 696,
1092 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0,
1093 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1094 .host_id = HOST_ID_ALL,
1095 },
1096 /* MCU NAVSS Non secure proxies */
1097 {
1098 .start_resource = 1,
1099 .num_resource = 8,
1100 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1101 RESASG_SUBTYPE_PROXY_PROXIES),
1102 .host_id = HOST_ID_A72_2,
1103 },
1104 {
1105 .start_resource = 9,
1106 .num_resource = 4,
1107 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1108 RESASG_SUBTYPE_PROXY_PROXIES),
1109 .host_id = HOST_ID_A72_3,
1110 },
1111 {
1112 .start_resource = 13,
1113 .num_resource = 8,
1114 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1115 RESASG_SUBTYPE_PROXY_PROXIES),
1116 .host_id = HOST_ID_MCU_0_R5_0,
1117 },
1118 {
1119 .start_resource = 13,
1120 .num_resource = 8,
1121 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1122 RESASG_SUBTYPE_PROXY_PROXIES),
1123 .host_id = HOST_ID_MCU_0_R5_1,
1124 },
1125 {
1126 .start_resource = 21,
1127 .num_resource = 8,
1128 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1129 RESASG_SUBTYPE_PROXY_PROXIES),
1130 .host_id = HOST_ID_MCU_0_R5_2,
1131 },
1132 {
1133 .start_resource = 29,
1134 .num_resource = 16,
1135 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1136 RESASG_SUBTYPE_PROXY_PROXIES),
1137 .host_id = HOST_ID_MAIN_0_R5_0,
1138 },
1139 {
1140 .start_resource = 45,
1141 .num_resource = 12,
1142 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1143 RESASG_SUBTYPE_PROXY_PROXIES),
1144 .host_id = HOST_ID_MAIN_0_R5_2,
1145 },
1146 {
1147 .start_resource = 57,
1148 .num_resource = 7,
1149 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_PROXY0,
1150 RESASG_SUBTYPE_PROXY_PROXIES),
1151 .host_id = HOST_ID_ALL,
1152 },
1153 /* MCU NAVSS Ringacc error event config */
1154 {
1155 .start_resource = 0,
1156 .num_resource = 1,
1157 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1158 RESASG_SUBTYPE_RA_ERROR_OES),
1159 .host_id = HOST_ID_ALL,
1160 },
1161 /* MCU NAVSS Ringacc free rings */
1162 {
1163 .start_resource = 96,
1164 .num_resource = 20,
1165 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1166 RESASG_SUBTYPE_RA_GP),
1167 .host_id = HOST_ID_A72_2,
1168 },
1169 {
1170 .start_resource = 116,
1171 .num_resource = 8,
1172 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1173 RESASG_SUBTYPE_RA_GP),
1174 .host_id = HOST_ID_A72_3,
1175 },
1176 {
1177 .start_resource = 124,
1178 .num_resource = 32,
1179 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1180 RESASG_SUBTYPE_RA_GP),
1181 .host_id = HOST_ID_MCU_0_R5_0,
1182 },
1183 {
1184 .start_resource = 124,
1185 .num_resource = 32,
1186 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1187 RESASG_SUBTYPE_RA_GP),
1188 .host_id = HOST_ID_MCU_0_R5_1,
1189 },
1190 {
1191 .start_resource = 156,
1192 .num_resource = 12,
1193 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1194 RESASG_SUBTYPE_RA_GP),
1195 .host_id = HOST_ID_MCU_0_R5_2,
1196 },
1197 {
1198 .start_resource = 168,
1199 .num_resource = 16,
1200 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1201 RESASG_SUBTYPE_RA_GP),
1202 .host_id = HOST_ID_MAIN_0_R5_0,
1203 },
1204 {
1205 .start_resource = 184,
1206 .num_resource = 8,
1207 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1208 RESASG_SUBTYPE_RA_GP),
1209 .host_id = HOST_ID_MAIN_0_R5_2,
1210 },
1211 {
1212 .start_resource = 192,
1213 .num_resource = 60,
1214 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1215 RESASG_SUBTYPE_RA_GP),
1216 .host_id = HOST_ID_ALL,
1217 },
1218 /* MCU NAVSS Ringacc rings for Normal capacity Rx channels */
1219 {
1220 .start_resource = 50,
1221 .num_resource = 12,
1222 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1223 RESASG_SUBTYPE_RA_UDMAP_RX),
1224 .host_id = HOST_ID_A72_2,
1225 },
1226 {
1227 .start_resource = 62,
1228 .num_resource = 6,
1229 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1230 RESASG_SUBTYPE_RA_UDMAP_RX),
1231 .host_id = HOST_ID_A72_3,
1232 },
1233 {
1234 .start_resource = 68,
1235 .num_resource = 5,
1236 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1237 RESASG_SUBTYPE_RA_UDMAP_RX),
1238 .host_id = HOST_ID_MCU_0_R5_0,
1239 },
1240 {
1241 .start_resource = 68,
1242 .num_resource = 5,
1243 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1244 RESASG_SUBTYPE_RA_UDMAP_RX),
1245 .host_id = HOST_ID_MCU_0_R5_1,
1246 },
1247 {
1248 .start_resource = 73,
1249 .num_resource = 2,
1250 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1251 RESASG_SUBTYPE_RA_UDMAP_RX),
1252 .host_id = HOST_ID_MCU_0_R5_2,
1253 },
1254 {
1255 .start_resource = 75,
1256 .num_resource = 3,
1257 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1258 RESASG_SUBTYPE_RA_UDMAP_RX),
1259 .host_id = HOST_ID_MAIN_0_R5_0,
1260 },
1261 {
1262 .start_resource = 78,
1263 .num_resource = 2,
1264 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1265 RESASG_SUBTYPE_RA_UDMAP_RX),
1266 .host_id = HOST_ID_MAIN_0_R5_2,
1267 },
1268 {
1269 .start_resource = 80,
1270 .num_resource = 13,
1271 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1272 RESASG_SUBTYPE_RA_UDMAP_RX),
1273 .host_id = HOST_ID_ALL,
1274 },
1275 /* MCU NAVSS Ringacc rings for Normal capacity Tx channels */
1276 {
1277 .start_resource = 2,
1278 .num_resource = 12,
1279 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1280 RESASG_SUBTYPE_RA_UDMAP_TX),
1281 .host_id = HOST_ID_A72_2,
1282 },
1283 {
1284 .start_resource = 14,
1285 .num_resource = 6,
1286 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1287 RESASG_SUBTYPE_RA_UDMAP_TX),
1288 .host_id = HOST_ID_A72_3,
1289 },
1290 {
1291 .start_resource = 20,
1292 .num_resource = 5,
1293 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1294 RESASG_SUBTYPE_RA_UDMAP_TX),
1295 .host_id = HOST_ID_MCU_0_R5_0,
1296 },
1297 {
1298 .start_resource = 20,
1299 .num_resource = 5,
1300 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1301 RESASG_SUBTYPE_RA_UDMAP_TX),
1302 .host_id = HOST_ID_MCU_0_R5_1,
1303 },
1304 {
1305 .start_resource = 25,
1306 .num_resource = 2,
1307 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1308 RESASG_SUBTYPE_RA_UDMAP_TX),
1309 .host_id = HOST_ID_MCU_0_R5_2,
1310 },
1311 {
1312 .start_resource = 27,
1313 .num_resource = 3,
1314 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1315 RESASG_SUBTYPE_RA_UDMAP_TX),
1316 .host_id = HOST_ID_MAIN_0_R5_0,
1317 },
1318 {
1319 .start_resource = 30,
1320 .num_resource = 2,
1321 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1322 RESASG_SUBTYPE_RA_UDMAP_TX),
1323 .host_id = HOST_ID_MAIN_0_R5_2,
1324 },
1325 {
1326 .start_resource = 32,
1327 .num_resource = 14,
1328 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1329 RESASG_SUBTYPE_RA_UDMAP_TX),
1330 .host_id = HOST_ID_ALL,
1331 },
1332 /* MCU NAVSS Ringacc rings for High capacity Rx channels */
1333 {
1334 .start_resource = 48,
1335 .num_resource = 2,
1336 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1337 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1338 .host_id = HOST_ID_MCU_0_R5_0,
1339 },
1340 {
1341 .start_resource = 48,
1342 .num_resource = 2,
1343 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1344 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1345 .host_id = HOST_ID_MCU_0_R5_1,
1346 },
1347 /* MCU NAVSS Ringacc rings for High capacity Tx channels */
1348 {
1349 .start_resource = 0,
1350 .num_resource = 2,
1351 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1352 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1353 .host_id = HOST_ID_MCU_0_R5_0,
1354 },
1355 {
1356 .start_resource = 0,
1357 .num_resource = 2,
1358 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1359 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1360 .host_id = HOST_ID_MCU_0_R5_1,
1361 },
1362 /* MCU NAVSS Ringacc virt_id range */
1363 {
1364 .start_resource = 2,
1365 .num_resource = 1,
1366 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1367 RESASG_SUBTYPE_RA_VIRTID),
1368 .host_id = HOST_ID_A72_2,
1369 },
1370 {
1371 .start_resource = 3,
1372 .num_resource = 1,
1373 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1374 RESASG_SUBTYPE_RA_VIRTID),
1375 .host_id = HOST_ID_A72_3,
1376 },
1377 /* MCU NAVSS Ringacc ring monitors */
1378 {
1379 .start_resource = 0,
1380 .num_resource = 3,
1381 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1382 RESASG_SUBTYPE_RA_MONITORS),
1383 .host_id = HOST_ID_A72_2,
1384 },
1385 {
1386 .start_resource = 3,
1387 .num_resource = 2,
1388 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1389 RESASG_SUBTYPE_RA_MONITORS),
1390 .host_id = HOST_ID_A72_3,
1391 },
1392 {
1393 .start_resource = 5,
1394 .num_resource = 3,
1395 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1396 RESASG_SUBTYPE_RA_MONITORS),
1397 .host_id = HOST_ID_MCU_0_R5_0,
1398 },
1399 {
1400 .start_resource = 5,
1401 .num_resource = 3,
1402 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1403 RESASG_SUBTYPE_RA_MONITORS),
1404 .host_id = HOST_ID_MCU_0_R5_1,
1405 },
1406 {
1407 .start_resource = 8,
1408 .num_resource = 3,
1409 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1410 RESASG_SUBTYPE_RA_MONITORS),
1411 .host_id = HOST_ID_MCU_0_R5_2,
1412 },
1413 {
1414 .start_resource = 11,
1415 .num_resource = 3,
1416 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1417 RESASG_SUBTYPE_RA_MONITORS),
1418 .host_id = HOST_ID_MAIN_0_R5_0,
1419 },
1420 {
1421 .start_resource = 14,
1422 .num_resource = 3,
1423 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1424 RESASG_SUBTYPE_RA_MONITORS),
1425 .host_id = HOST_ID_MAIN_0_R5_2,
1426 },
1427 {
1428 .start_resource = 17,
1429 .num_resource = 15,
1430 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1431 RESASG_SUBTYPE_RA_MONITORS),
1432 .host_id = HOST_ID_ALL,
1433 },
1434 /* MCU NAVSS UDMA Rx free flows */
1435 {
1436 .start_resource = 48,
1437 .num_resource = 8,
1438 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1439 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1440 .host_id = HOST_ID_A72_2,
1441 },
1442 {
1443 .start_resource = 56,
1444 .num_resource = 4,
1445 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1446 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1447 .host_id = HOST_ID_A72_3,
1448 },
1449 {
1450 .start_resource = 60,
1451 .num_resource = 8,
1452 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1453 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1454 .host_id = HOST_ID_MCU_0_R5_0,
1455 },
1456 {
1457 .start_resource = 60,
1458 .num_resource = 8,
1459 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1460 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1461 .host_id = HOST_ID_MCU_0_R5_1,
1462 },
1463 {
1464 .start_resource = 68,
1465 .num_resource = 4,
1466 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1467 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1468 .host_id = HOST_ID_MCU_0_R5_2,
1469 },
1470 {
1471 .start_resource = 72,
1472 .num_resource = 8,
1473 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1474 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1475 .host_id = HOST_ID_MAIN_0_R5_0,
1476 },
1477 {
1478 .start_resource = 80,
1479 .num_resource = 4,
1480 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1481 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1482 .host_id = HOST_ID_MAIN_0_R5_2,
1483 },
1484 {
1485 .start_resource = 84,
1486 .num_resource = 12,
1487 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1488 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1489 .host_id = HOST_ID_ALL,
1490 },
1491 /* MCU NAVSS invalid flow event config */
1492 {
1493 .start_resource = 0,
1494 .num_resource = 1,
1495 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1496 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
1497 .host_id = HOST_ID_ALL,
1498 },
1499 /* MCU NAVSS UDMA global event trigger */
1500 {
1501 .start_resource = 56320,
1502 .num_resource = 256,
1503 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1504 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
1505 .host_id = HOST_ID_ALL,
1506 },
1507 /* MCU NAVSS UDMA global config */
1508 {
1509 .start_resource = 0,
1510 .num_resource = 1,
1511 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1512 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
1513 .host_id = HOST_ID_ALL,
1514 },
1515 /* MCU NAVSS UDMA Normal capacity Rx channels */
1516 {
1517 .start_resource = 2,
1518 .num_resource = 12,
1519 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1520 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1521 .host_id = HOST_ID_A72_2,
1522 },
1523 {
1524 .start_resource = 14,
1525 .num_resource = 6,
1526 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1527 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1528 .host_id = HOST_ID_A72_3,
1529 },
1530 {
1531 .start_resource = 20,
1532 .num_resource = 5,
1533 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1534 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1535 .host_id = HOST_ID_MCU_0_R5_0,
1536 },
1537 {
1538 .start_resource = 20,
1539 .num_resource = 5,
1540 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1541 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1542 .host_id = HOST_ID_MCU_0_R5_1,
1543 },
1544 {
1545 .start_resource = 25,
1546 .num_resource = 2,
1547 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1548 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1549 .host_id = HOST_ID_MCU_0_R5_2,
1550 },
1551 {
1552 .start_resource = 27,
1553 .num_resource = 3,
1554 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1555 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1556 .host_id = HOST_ID_MAIN_0_R5_0,
1557 },
1558 {
1559 .start_resource = 30,
1560 .num_resource = 2,
1561 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1562 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1563 .host_id = HOST_ID_MAIN_0_R5_2,
1564 },
1565 {
1566 .start_resource = 32,
1567 .num_resource = 13,
1568 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1569 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1570 .host_id = HOST_ID_ALL,
1571 },
1572 /* MCU NAVSS UDMA High capacity Rx channels */
1573 {
1574 .start_resource = 0,
1575 .num_resource = 2,
1576 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1577 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1578 .host_id = HOST_ID_MCU_0_R5_0,
1579 },
1580 {
1581 .start_resource = 0,
1582 .num_resource = 2,
1583 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1584 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1585 .host_id = HOST_ID_MCU_0_R5_1,
1586 },
1587 /* MCU NAVSS UDMA Normal capacity Tx channels */
1588 {
1589 .start_resource = 2,
1590 .num_resource = 12,
1591 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1592 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1593 .host_id = HOST_ID_A72_2,
1594 },
1595 {
1596 .start_resource = 14,
1597 .num_resource = 6,
1598 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1599 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1600 .host_id = HOST_ID_A72_3,
1601 },
1602 {
1603 .start_resource = 20,
1604 .num_resource = 5,
1605 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1606 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1607 .host_id = HOST_ID_MCU_0_R5_0,
1608 },
1609 {
1610 .start_resource = 20,
1611 .num_resource = 5,
1612 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1613 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1614 .host_id = HOST_ID_MCU_0_R5_1,
1615 },
1616 {
1617 .start_resource = 25,
1618 .num_resource = 2,
1619 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1620 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1621 .host_id = HOST_ID_MCU_0_R5_2,
1622 },
1623 {
1624 .start_resource = 27,
1625 .num_resource = 3,
1626 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1627 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1628 .host_id = HOST_ID_MAIN_0_R5_0,
1629 },
1630 {
1631 .start_resource = 30,
1632 .num_resource = 2,
1633 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1634 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1635 .host_id = HOST_ID_MAIN_0_R5_2,
1636 },
1637 {
1638 .start_resource = 32,
1639 .num_resource = 14,
1640 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1641 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1642 .host_id = HOST_ID_ALL,
1643 },
1644 /* MCU NAVSS UDMA High capacity Tx channels */
1645 {
1646 .start_resource = 0,
1647 .num_resource = 2,
1648 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1649 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1650 .host_id = HOST_ID_MCU_0_R5_0,
1651 },
1652 {
1653 .start_resource = 0,
1654 .num_resource = 2,
1655 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1656 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1657 .host_id = HOST_ID_MCU_0_R5_1,
1658 },
1659 /* MCU NAVSS Interrupt router */
1660 {
1661 .start_resource = 4,
1662 .num_resource = 28,
1663 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
1664 RESASG_SUBTYPE_IR_OUTPUT),
1665 .host_id = HOST_ID_MCU_0_R5_0,
1666 },
1667 {
1668 .start_resource = 4,
1669 .num_resource = 28,
1670 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
1671 RESASG_SUBTYPE_IR_OUTPUT),
1672 .host_id = HOST_ID_MCU_0_R5_1,
1673 },
1674 {
1675 .start_resource = 36,
1676 .num_resource = 28,
1677 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_INTR_0,
1678 RESASG_SUBTYPE_IR_OUTPUT),
1679 .host_id = HOST_ID_MCU_0_R5_2,
1680 },
73 }, 1681 },
74}; 1682};
diff --git a/soc/j7200/evm/sysfw_img_cfg.h b/soc/j7200/evm/sysfw_img_cfg.h
index 93c90ec..82c3ad5 100644
--- a/soc/j7200/evm/sysfw_img_cfg.h
+++ b/soc/j7200/evm/sysfw_img_cfg.h
@@ -1,5 +1,7 @@
1/* 1/*
2 * K3 System Firmware Configuration Data 2 * K3 System Firmware Resource Management Board Config Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
3 * 5 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 * 7 *
@@ -35,6 +37,6 @@
35#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
37 39
38#define BOARDCFG_RM_RESASG_ENTRIES 0 40#define BOARDCFG_RM_RESASG_ENTRIES 215
39 41
40#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */