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author | Nikhil Devshatwar | 2020-08-18 11:01:09 -0500 |
---|---|---|
committer | Dave Gerlach | 2020-08-19 09:33:43 -0500 |
commit | 75d3fce7d9b780f24664cb3da76ab0031a19ff81 (patch) | |
tree | 89aab398dc6a791a8e1145e8826dfb3180f8c131 /include/soc/j7200/devices.h | |
parent | 060498a9bf287260431139f69767f54eff3d159c (diff) | |
download | k3-image-gen-75d3fce7d9b780f24664cb3da76ab0031a19ff81.tar.gz k3-image-gen-75d3fce7d9b780f24664cb3da76ab0031a19ff81.tar.xz k3-image-gen-75d3fce7d9b780f24664cb3da76ab0031a19ff81.zip |
include: j721e: j7200: Update headers from SYSFW 2020.07-RC2
Update header files from System firmware 2020.07.
This includes many renames for the device macros.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Diffstat (limited to 'include/soc/j7200/devices.h')
-rw-r--r-- | include/soc/j7200/devices.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/soc/j7200/devices.h b/include/soc/j7200/devices.h index bf8e60ea4..11cc026aa 100644 --- a/include/soc/j7200/devices.h +++ b/include/soc/j7200/devices.h | |||
@@ -39,7 +39,7 @@ | |||
39 | #define J7200_DEV_MCU_ADC1 1 | 39 | #define J7200_DEV_MCU_ADC1 1 |
40 | #define J7200_DEV_ATL0 2 | 40 | #define J7200_DEV_ATL0 2 |
41 | #define J7200_DEV_COMPUTE_CLUSTER0 3 | 41 | #define J7200_DEV_COMPUTE_CLUSTER0 3 |
42 | #define J7200_DEV_A72SS0 4 | 42 | #define J7200_DEV_A72SS0_CORE0 4 |
43 | #define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5 | 43 | #define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5 |
44 | #define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6 | 44 | #define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6 |
45 | #define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7 | 45 | #define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7 |
@@ -195,8 +195,8 @@ | |||
195 | #define J7200_DEV_WKUP_I2C0 197 | 195 | #define J7200_DEV_WKUP_I2C0 197 |
196 | #define J7200_DEV_NAVSS0 199 | 196 | #define J7200_DEV_NAVSS0 199 |
197 | #define J7200_DEV_NAVSS0_CPTS_0 201 | 197 | #define J7200_DEV_NAVSS0_CPTS_0 201 |
198 | #define J7200_DEV_A72SS0_CORE0 202 | 198 | #define J7200_DEV_A72SS0_CORE0_0 202 |
199 | #define J7200_DEV_A72SS0_CORE1 203 | 199 | #define J7200_DEV_A72SS0_CORE0_1 203 |
200 | #define J7200_DEV_NAVSS0_DTI_0 206 | 200 | #define J7200_DEV_NAVSS0_DTI_0 206 |
201 | #define J7200_DEV_NAVSS0_MODSS_INTA_0 207 | 201 | #define J7200_DEV_NAVSS0_MODSS_INTA_0 207 |
202 | #define J7200_DEV_NAVSS0_MODSS_INTA_1 208 | 202 | #define J7200_DEV_NAVSS0_MODSS_INTA_1 208 |