diff options
author | Nishanth Menon | 2019-05-18 07:19:26 -0500 |
---|---|---|
committer | Andreas Dannenberg | 2019-06-10 11:41:49 -0500 |
commit | 6c918cf454b3e5a82df3d697bee624eaa41b3881 (patch) | |
tree | e6c70735b01e7e71c719e7ab11c34857487793bf /include/soc | |
parent | 429501819077e61a5d32b4507b2e0b9e3fa7b653 (diff) | |
download | k3-image-gen-6c918cf454b3e5a82df3d697bee624eaa41b3881.tar.gz k3-image-gen-6c918cf454b3e5a82df3d697bee624eaa41b3881.tar.xz k3-image-gen-6c918cf454b3e5a82df3d697bee624eaa41b3881.zip |
include: Add AM65X specific headers corresponding to SYSFW
Introduce initial AM65X specific headers
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'include/soc')
-rw-r--r-- | include/soc/am65x/devices.h | 282 | ||||
-rw-r--r-- | include/soc/am65x/hosts.h | 85 | ||||
-rw-r--r-- | include/soc/am65x/resasg_types.h | 298 |
3 files changed, 665 insertions, 0 deletions
diff --git a/include/soc/am65x/devices.h b/include/soc/am65x/devices.h new file mode 100644 index 000000000..a1bc9211f --- /dev/null +++ b/include/soc/am65x/devices.h | |||
@@ -0,0 +1,282 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Board Configuration Data Definitions | ||
3 | * | ||
4 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef SOC_AM6_DEVICES_H | ||
36 | #define SOC_AM6_DEVICES_H | ||
37 | |||
38 | #define AM6_DEV_DCC4 13 | ||
39 | #define AM6_DEV_DCC6 15 | ||
40 | #define AM6_DEV_DCC0 9 | ||
41 | #define AM6_DEV_MCU_DCC2 19 | ||
42 | #define AM6_DEV_DCC5 14 | ||
43 | #define AM6_DEV_MCU_DCC0 17 | ||
44 | #define AM6_DEV_MCU_DCC1 18 | ||
45 | #define AM6_DEV_DCC1 10 | ||
46 | #define AM6_DEV_DCC3 12 | ||
47 | #define AM6_DEV_DCC7 16 | ||
48 | #define AM6_DEV_DCC2 11 | ||
49 | #define AM6_DEV_MCU_I2C0 114 | ||
50 | #define AM6_DEV_I2C3 113 | ||
51 | #define AM6_DEV_I2C2 112 | ||
52 | #define AM6_DEV_WKUP_I2C0 115 | ||
53 | #define AM6_DEV_I2C0 110 | ||
54 | #define AM6_DEV_I2C1 111 | ||
55 | #define AM6_DEV_TIMER5 30 | ||
56 | #define AM6_DEV_TIMER6 31 | ||
57 | #define AM6_DEV_TIMER7 32 | ||
58 | #define AM6_DEV_MCU_TIMER0 35 | ||
59 | #define AM6_DEV_TIMER8 33 | ||
60 | #define AM6_DEV_TIMER2 27 | ||
61 | #define AM6_DEV_MCU_TIMER1 36 | ||
62 | #define AM6_DEV_MCU_TIMER2 37 | ||
63 | #define AM6_DEV_TIMER4 29 | ||
64 | #define AM6_DEV_TIMER3 28 | ||
65 | #define AM6_DEV_TIMER9 34 | ||
66 | #define AM6_DEV_TIMER11 26 | ||
67 | #define AM6_DEV_TIMER10 25 | ||
68 | #define AM6_DEV_TIMER0 23 | ||
69 | #define AM6_DEV_MCU_TIMER3 38 | ||
70 | #define AM6_DEV_TIMER1 24 | ||
71 | #define AM6_DEV_WKUP_PSC0 79 | ||
72 | #define AM6_DEV_CBASS0 82 | ||
73 | #define AM6_DEV_PLL_MMR0 101 | ||
74 | #define AM6_DEV_MCU_CPT2_AGGR0 7 | ||
75 | #define AM6_DEV_CPT2_AGGR0 6 | ||
76 | #define AM6_DEV_DEBUGSS0 68 | ||
77 | #define AM6_DEV_EHRPWM4 44 | ||
78 | #define AM6_DEV_EHRPWM1 41 | ||
79 | #define AM6_DEV_EHRPWM0 40 | ||
80 | #define AM6_DEV_EHRPWM3 43 | ||
81 | #define AM6_DEV_EHRPWM5 45 | ||
82 | #define AM6_DEV_EHRPWM2 42 | ||
83 | #define AM6_DEV_ELM0 46 | ||
84 | #define AM6_DEV_MCU_UART0 149 | ||
85 | #define AM6_DEV_WKUP_UART0 150 | ||
86 | #define AM6_DEV_UART1 147 | ||
87 | #define AM6_DEV_UART0 146 | ||
88 | #define AM6_DEV_UART2 148 | ||
89 | #define AM6_DEV_SA2_UL0 136 | ||
90 | #define AM6_DEV_CAL0 2 | ||
91 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206 | ||
92 | #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207 | ||
93 | #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208 | ||
94 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209 | ||
95 | #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210 | ||
96 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211 | ||
97 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212 | ||
98 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213 | ||
99 | #define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214 | ||
100 | #define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215 | ||
101 | #define AM6_DEV_PBIST0 73 | ||
102 | #define AM6_DEV_PBIST1 74 | ||
103 | #define AM6_DEV_MCU_PBIST0 75 | ||
104 | #define AM6_DEV_NAVSS0 118 | ||
105 | #define AM6_DEV_DSS0 67 | ||
106 | #define AM6_DEV_GPMC0 60 | ||
107 | #define AM6_DEV_MMCSD1 48 | ||
108 | #define AM6_DEV_WKUP_PLLCTRL0 77 | ||
109 | #define AM6_DEV_PLLCTRL0 76 | ||
110 | #define AM6_DEV_USB3SS1 152 | ||
111 | #define AM6_DEV_USB3SS0 151 | ||
112 | #define AM6_DEV_MCU_MCSPI0 142 | ||
113 | #define AM6_DEV_MCSPI2 139 | ||
114 | #define AM6_DEV_MCU_MCSPI2 144 | ||
115 | #define AM6_DEV_MCSPI0 137 | ||
116 | #define AM6_DEV_MCSPI1 138 | ||
117 | #define AM6_DEV_MCSPI4 141 | ||
118 | #define AM6_DEV_MCSPI3 140 | ||
119 | #define AM6_DEV_MCU_MCSPI1 143 | ||
120 | #define AM6_DEV_DEBUGSS_WRAP0 21 | ||
121 | #define AM6_DEV_CBASS_INFRA0 85 | ||
122 | #define AM6_DEV_STM0 8 | ||
123 | #define AM6_DEV_MCU_RTI1 135 | ||
124 | #define AM6_DEV_RTI0 130 | ||
125 | #define AM6_DEV_RTI3 133 | ||
126 | #define AM6_DEV_RTI1 131 | ||
127 | #define AM6_DEV_MCU_RTI0 134 | ||
128 | #define AM6_DEV_RTI2 132 | ||
129 | #define AM6_DEV_PSRAMECC0 128 | ||
130 | #define AM6_DEV_EFUSE0 69 | ||
131 | #define AM6_DEV_MCASP0 104 | ||
132 | #define AM6_DEV_MCASP1 105 | ||
133 | #define AM6_DEV_MCASP2 106 | ||
134 | #define AM6_DEV_MCU_ARMSS0 129 | ||
135 | #define AM6_DEV_MCU_ARMSS0_CPU0 159 | ||
136 | #define AM6_DEV_MCU_ARMSS0_CPU1 245 | ||
137 | #define AM6_DEV_CCDEBUGSS0 66 | ||
138 | #define AM6_DEV_WKUP_CTRL_MMR0 155 | ||
139 | #define AM6_DEV_MCU_CBASS_FW0 91 | ||
140 | #define AM6_DEV_MCU_CPSW0 5 | ||
141 | #define AM6_DEV_SERDES0 153 | ||
142 | #define AM6_DEV_SERDES1 154 | ||
143 | #define AM6_DEV_OLDI_TX_CORE_MAIN_0 216 | ||
144 | #define AM6_DEV_MCU_ADC1 1 | ||
145 | #define AM6_DEV_MCU_ADC0 0 | ||
146 | #define AM6_DEV_WKUP_DMSC0 22 | ||
147 | #define AM6_DEV_MCU_PLL_MMR0 108 | ||
148 | #define AM6_DEV_MCU_SEC_MMR0 109 | ||
149 | #define AM6_DEV_GIC0 56 | ||
150 | #define AM6_DEV_MCU_DEBUGSS0 71 | ||
151 | #define AM6_DEV_EQEP0 49 | ||
152 | #define AM6_DEV_EQEP2 51 | ||
153 | #define AM6_DEV_EQEP1 50 | ||
154 | #define AM6_DEV_WKUP_GPIO0 59 | ||
155 | #define AM6_DEV_GPIO0 57 | ||
156 | #define AM6_DEV_GPIO1 58 | ||
157 | #define AM6_DEV_COMPUTE_CLUSTER_MSMC0 196 | ||
158 | #define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197 | ||
159 | #define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198 | ||
160 | #define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199 | ||
161 | #define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200 | ||
162 | #define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201 | ||
163 | #define AM6_DEV_COMPUTE_CLUSTER_A53_0 202 | ||
164 | #define AM6_DEV_COMPUTE_CLUSTER_A53_1 203 | ||
165 | #define AM6_DEV_COMPUTE_CLUSTER_A53_2 204 | ||
166 | #define AM6_DEV_COMPUTE_CLUSTER_A53_3 205 | ||
167 | #define AM6_DEV_WKUP_CBASS0 94 | ||
168 | #define AM6_DEV_MCU_ROM0 78 | ||
169 | #define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217 | ||
170 | #define AM6_DEV_ESM0 52 | ||
171 | #define AM6_DEV_PRU_ICSSG2 64 | ||
172 | #define AM6_DEV_PRU_ICSSG0 62 | ||
173 | #define AM6_DEV_PRU_ICSSG1 63 | ||
174 | #define AM6_DEV_MCU_ESM0 53 | ||
175 | #define AM6_DEV_ECAP0 39 | ||
176 | #define AM6_DEV_WKUP_ESM0 54 | ||
177 | #define AM6_DEV_MCU_EFUSE0 72 | ||
178 | #define AM6_DEV_MCU_CTRL_MMR0 107 | ||
179 | #define AM6_DEV_PSC0 70 | ||
180 | #define AM6_DEV_CTRL_MMR0 99 | ||
181 | #define AM6_DEV_MCU_MCAN0 102 | ||
182 | #define AM6_DEV_MCU_MCAN1 103 | ||
183 | #define AM6_DEV_DDRSS0 20 | ||
184 | #define AM6_DEV_MCU_NAVSS0 119 | ||
185 | #define AM6_DEV_MCU_FSS0 55 | ||
186 | #define AM6_DEV_DFTSS0 117 | ||
187 | #define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156 | ||
188 | #define AM6_DEV_GPIOMUX_INTRTR0 100 | ||
189 | #define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97 | ||
190 | #define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98 | ||
191 | #define AM6_DEV_ICEMELTER_WKUP_0 218 | ||
192 | #define AM6_DEV_GPU0 65 | ||
193 | #define AM6_DEV_PDMA_DEBUG0 122 | ||
194 | #define AM6_DEV_PDMA0 123 | ||
195 | #define AM6_DEV_PDMA1 124 | ||
196 | #define AM6_DEV_MCU_PDMA0 125 | ||
197 | #define AM6_DEV_MCU_PDMA1 126 | ||
198 | #define AM6_DEV_MCU_MSRAM0 116 | ||
199 | #define AM6_DEV_CMPEVENT_INTRTR0 3 | ||
200 | #define AM6_DEV_DEBUGSUSPENDRTR0 81 | ||
201 | #define AM6_DEV_TIMESYNC_INTRTR0 145 | ||
202 | #define AM6_DEV_CBASS_DEBUG0 83 | ||
203 | #define AM6_DEV_CBASS_FW0 84 | ||
204 | #define AM6_DEV_MCU_CBASS_DEBUG0 90 | ||
205 | #define AM6_DEV_WKUP_CBASS_FW0 96 | ||
206 | #define AM6_DEV_PCIE0 120 | ||
207 | #define AM6_DEV_PCIE1 121 | ||
208 | #define AM6_DEV_GTC0 61 | ||
209 | #define AM6_DEV_K3_LED_MAIN_0 219 | ||
210 | #define AM6_DEV_WKUP_VTM0 80 | ||
211 | #define AM6_DEV_MMCSD0 47 | ||
212 | #define AM6_DEV_MCU_ECC_AGGR0 92 | ||
213 | #define AM6_DEV_ECC_AGGR1 87 | ||
214 | #define AM6_DEV_ECC_AGGR2 88 | ||
215 | #define AM6_DEV_MCU_ECC_AGGR1 93 | ||
216 | #define AM6_DEV_WKUP_ECC_AGGR0 95 | ||
217 | #define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220 | ||
218 | #define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221 | ||
219 | #define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222 | ||
220 | #define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223 | ||
221 | #define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224 | ||
222 | #define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225 | ||
223 | #define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226 | ||
224 | #define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227 | ||
225 | #define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228 | ||
226 | #define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229 | ||
227 | #define AM6_DEV_ECC_AGGR0 86 | ||
228 | #define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230 | ||
229 | #define AM6_DEV_MCU_PSRAM0 127 | ||
230 | #define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231 | ||
231 | #define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232 | ||
232 | #define AM6_DEV_MCU_CBASS0 89 | ||
233 | #define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233 | ||
234 | #define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234 | ||
235 | #define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235 | ||
236 | #define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU 236 | ||
237 | #define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA 237 | ||
238 | #define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC 238 | ||
239 | #define AM6_DEV_DUMMY_IP_LPSC_DMSC 239 | ||
240 | #define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA 240 | ||
241 | #define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN 241 | ||
242 | #define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP 242 | ||
243 | #define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU 243 | ||
244 | #define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA 244 | ||
245 | #define AM6_DEV_BOARD0 157 | ||
246 | #define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161 | ||
247 | #define AM6_DEV_WKUP_DMSC0_INTR_AGGR_0 162 | ||
248 | #define AM6_DEV_NAVSS0_CPTS0 163 | ||
249 | #define AM6_DEV_NAVSS0_INTR_ROUTER_0 182 | ||
250 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164 | ||
251 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165 | ||
252 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166 | ||
253 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3 167 | ||
254 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4 168 | ||
255 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5 169 | ||
256 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6 170 | ||
257 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7 171 | ||
258 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8 172 | ||
259 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9 173 | ||
260 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174 | ||
261 | #define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175 | ||
262 | #define AM6_DEV_NAVSS0_MCRC0 176 | ||
263 | #define AM6_DEV_NAVSS0_MODSS_INTA0 180 | ||
264 | #define AM6_DEV_NAVSS0_MODSS_INTA1 181 | ||
265 | #define AM6_DEV_NAVSS0_PROXY0 185 | ||
266 | #define AM6_DEV_NAVSS0_PVU0 177 | ||
267 | #define AM6_DEV_NAVSS0_PVU1 178 | ||
268 | #define AM6_DEV_NAVSS0_RINGACC0 187 | ||
269 | #define AM6_DEV_NAVSS0_SEC_PROXY0 186 | ||
270 | #define AM6_DEV_NAVSS0_TIMER_MGR0 183 | ||
271 | #define AM6_DEV_NAVSS0_TIMER_MGR1 184 | ||
272 | #define AM6_DEV_NAVSS0_UDMAP0 188 | ||
273 | #define AM6_DEV_NAVSS0_UDMASS_INTA0 179 | ||
274 | #define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189 | ||
275 | #define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190 | ||
276 | #define AM6_DEV_MCU_NAVSS0_MCRC0 193 | ||
277 | #define AM6_DEV_MCU_NAVSS0_PROXY0 191 | ||
278 | #define AM6_DEV_MCU_NAVSS0_RINGACC0 195 | ||
279 | #define AM6_DEV_MCU_NAVSS0_SEC_PROXY0 192 | ||
280 | #define AM6_DEV_MCU_NAVSS0_UDMAP0 194 | ||
281 | |||
282 | #endif /* SOC_AM6_DEVICES_H */ | ||
diff --git a/include/soc/am65x/hosts.h b/include/soc/am65x/hosts.h new file mode 100644 index 000000000..0fe61be88 --- /dev/null +++ b/include/soc/am65x/hosts.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Board Configuration Data Definitions | ||
3 | * | ||
4 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef AM6_HOSTS_H | ||
36 | #define AM6_HOSTS_H | ||
37 | |||
38 | /* Host IDs for AM6 Device */ | ||
39 | |||
40 | /** DMSC(Secure): Device Management and Security Control */ | ||
41 | #define HOST_ID_DMSC (0U) | ||
42 | /** r5_0(Non Secure): Cortex R5 Context 0 on MCU island */ | ||
43 | #define HOST_ID_R5_0 (3U) | ||
44 | /** r5_1(Secure): Cortex R5 Context 1 on MCU island(Boot) */ | ||
45 | #define HOST_ID_R5_1 (4U) | ||
46 | /** r5_2(Non Secure): Cortex R5 Context 2 on MCU island */ | ||
47 | #define HOST_ID_R5_2 (5U) | ||
48 | /** r5_3(Secure): Cortex R5 Context 3 on MCU island */ | ||
49 | #define HOST_ID_R5_3 (6U) | ||
50 | /** a53_0(Secure): Cortex A53 context 0 on Main island */ | ||
51 | #define HOST_ID_A53_0 (10U) | ||
52 | /** a53_1(Secure): Cortex A53 context 1 on Main island */ | ||
53 | #define HOST_ID_A53_1 (11U) | ||
54 | /** a53_2(Non Secure): Cortex A53 context 2 on Main island */ | ||
55 | #define HOST_ID_A53_2 (12U) | ||
56 | /** a53_3(Non Secure): Cortex A53 context 3 on Main island */ | ||
57 | #define HOST_ID_A53_3 (13U) | ||
58 | /** a53_4(Non Secure): Cortex A53 context 4 on Main island */ | ||
59 | #define HOST_ID_A53_4 (14U) | ||
60 | /** a53_5(Non Secure): Cortex A53 context 5 on Main island */ | ||
61 | #define HOST_ID_A53_5 (15U) | ||
62 | /** a53_6(Non Secure): Cortex A53 context 6 on Main island */ | ||
63 | #define HOST_ID_A53_6 (16U) | ||
64 | /** a53_7(Non Secure): Cortex A53 context 7 on Main island */ | ||
65 | #define HOST_ID_A53_7 (17U) | ||
66 | /** gpu_0(Non Secure): SGX544 Context 0 on Main island */ | ||
67 | #define HOST_ID_GPU_0 (30U) | ||
68 | /** gpu_1(Non Secure): SGX544 Context 1 on Main island */ | ||
69 | #define HOST_ID_GPU_1 (31U) | ||
70 | /** icssg_0(Non Secure): ICSS Context 0 on Main island */ | ||
71 | #define HOST_ID_ICSSG_0 (50U) | ||
72 | /** icssg_1(Non Secure): ICSS Context 1 on Main island */ | ||
73 | #define HOST_ID_ICSSG_1 (51U) | ||
74 | /** icssg_2(Non Secure): ICSS Context 2 on Main island */ | ||
75 | #define HOST_ID_ICSSG_2 (52U) | ||
76 | |||
77 | /** Host catch all. Used in board configuration resource assignments to | ||
78 | * define resource ranges useable by all hosts. Cannot be used as a host | ||
79 | * in TISCI message headers */ | ||
80 | #define HOST_ID_ALL (128U) | ||
81 | |||
82 | /** Number of unique hosts on the AM6 SoC */ | ||
83 | #define HOST_ID_CNT (19U) | ||
84 | |||
85 | #endif /* AM6_HOSTS_H */ | ||
diff --git a/include/soc/am65x/resasg_types.h b/include/soc/am65x/resasg_types.h new file mode 100644 index 000000000..5e06ea361 --- /dev/null +++ b/include/soc/am65x/resasg_types.h | |||
@@ -0,0 +1,298 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Board Configuration Data Definitions | ||
3 | * | ||
4 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef RESASG_TYPES_H | ||
36 | #define RESASG_TYPES_H | ||
37 | |||
38 | /** | ||
39 | * Resource assignment type shift | ||
40 | */ | ||
41 | #define RESASG_TYPE_SHIFT (0x0006U) | ||
42 | /** | ||
43 | * Resource assignment type mask | ||
44 | */ | ||
45 | #define RESASG_TYPE_MASK (0xFFC0U) | ||
46 | |||
47 | /** | ||
48 | * Resource assignment subtype shift | ||
49 | */ | ||
50 | #define RESASG_SUBTYPE_SHIFT (0x0000U) | ||
51 | /** | ||
52 | * Resource assignment subtype mask | ||
53 | */ | ||
54 | #define RESASG_SUBTYPE_MASK (0x003FU) | ||
55 | |||
56 | /** | ||
57 | * Macro to create unique resource assignment types using type and subtype | ||
58 | */ | ||
59 | #define RESASG_UTYPE(type, subtype) \ | ||
60 | (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \ | ||
61 | ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK)) | ||
62 | |||
63 | /** Main domain Navigator Subsystem UDMASS IA0 */ | ||
64 | #define RESASG_TYPE_MAIN_NAV_UDMASS_IA0 (0x000U) | ||
65 | /** Main domain Navigator Subsystem MODSS IA0 */ | ||
66 | #define RESASG_TYPE_MAIN_NAV_MODSS_IA0 (0x001U) | ||
67 | /** Main domain Navigator Subsystem MODSS IA1 */ | ||
68 | #define RESASG_TYPE_MAIN_NAV_MODSS_IA1 (0x002U) | ||
69 | /** MCU domain Navigator Subsystem UDMASS IA0 */ | ||
70 | #define RESASG_TYPE_MCU_NAV_UDMASS_IA0 (0x003U) | ||
71 | /** Main domain Navigator Subsystem MCRC */ | ||
72 | #define RESASG_TYPE_MAIN_NAV_MCRC (0x004U) | ||
73 | /** MCU domain Navigator Subsystem MCRC */ | ||
74 | #define RESASG_TYPE_MCU_NAV_MCRC (0x005U) | ||
75 | /** Main domain Navigator Subsystem UDMAP */ | ||
76 | #define RESASG_TYPE_MAIN_NAV_UDMAP (0x006U) | ||
77 | /** MCU domain Navigator Subsystem UDMAP */ | ||
78 | #define RESASG_TYPE_MCU_NAV_UDMAP (0x007U) | ||
79 | /** MSMC */ | ||
80 | #define RESASG_TYPE_MSMC (0x008U) | ||
81 | /** Main domain Navigator Subsystem Ring Accelerator */ | ||
82 | #define RESASG_TYPE_MAIN_NAV_RA (0x009U) | ||
83 | /** MCU domain Navigator Subsystem Ring Accelerator */ | ||
84 | #define RESASG_TYPE_MCU_NAV_RA (0x00AU) | ||
85 | /** A53 GIC IRQ (input interrupts) */ | ||
86 | #define RESASG_TYPE_GIC_IRQ (0x00BU) | ||
87 | /** Pulsar core 0 IRQ (input interrupts) */ | ||
88 | #define RESASG_TYPE_PULSAR_C0_IRQ (0x00CU) | ||
89 | /** Pulsar core 1 IRQ (input interrupts) */ | ||
90 | #define RESASG_TYPE_PULSAR_C1_IRQ (0x00DU) | ||
91 | /** ICSSG 0 IRQ (input interrupts) */ | ||
92 | #define RESASG_TYPE_ICSSG0_IRQ (0x00EU) | ||
93 | /** ICSSG 1 IRQ (input interrupts) */ | ||
94 | #define RESASG_TYPE_ICSSG1_IRQ (0x00FU) | ||
95 | /** ICSSG 2 IRQ (input interrupts) */ | ||
96 | #define RESASG_TYPE_ICSSG2_IRQ (0x010U) | ||
97 | /** Maximum RESASG_TYPE value. DO NOT create types with a value | ||
98 | * greater than this */ | ||
99 | #define RESASG_TYPE_MAX (0x3FFU) | ||
100 | |||
101 | /** Main Nav UDMASS IA0 virtual interrupts */ | ||
102 | #define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT (0x00U) | ||
103 | /** Main Nav UDMASS IA0 source events (SEVI) */ | ||
104 | #define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI (0x01U) | ||
105 | /** Main Nav UDMASS IA0 multicast events (MEVI) */ | ||
106 | #define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI (0x02U) | ||
107 | /** Main Nav UDMASS IA0 global counter events (GEVI) */ | ||
108 | #define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI (0x03U) | ||
109 | /** Main Nav Total UDMASS IA0 subtypes. Update when subtypes added */ | ||
110 | #define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT (0x04U) | ||
111 | |||
112 | /** Main Nav MODSS IA0 virtual interrupts */ | ||
113 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT (0x00U) | ||
114 | /** Main Nav MODSS IA0 single events (SEVI) */ | ||
115 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI (0x01U) | ||
116 | /** Total Main Nav MODSS IA0 subtypes. Update when subtypes added */ | ||
117 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT (0x02U) | ||
118 | |||
119 | /** Main Nav MODSS IA1 virtual interrupts */ | ||
120 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT (0x00U) | ||
121 | /** Main Nav MODSS IA1 single events (SEVI) */ | ||
122 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI (0x01U) | ||
123 | /** Total Main Nav MODSS IA1 subtypes. Update when subtypes added */ | ||
124 | #define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT (0x02U) | ||
125 | |||
126 | /** MCU Nav UDMASS IA0 virtual interrupts */ | ||
127 | #define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT (0x00U) | ||
128 | /** MCU Nav UDMASS IA0 single events (SEVI) */ | ||
129 | #define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI (0x01U) | ||
130 | /** MCU Nav UDMASS IA0 multicast events (MEVI) */ | ||
131 | #define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI (0x02U) | ||
132 | /** MCU Nav UDMASS IA0 global counter events (GEVI) */ | ||
133 | #define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI (0x03U) | ||
134 | /** Total MCU Nav UDMASS IA0 subtypes. Update when subtypes added */ | ||
135 | #define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT (0x04U) | ||
136 | |||
137 | /** Main Nav MCRC local events (LEVI) */ | ||
138 | #define RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI (0x00U) | ||
139 | /** Total Main Nav MCRC subtypes. Update when subtypes added */ | ||
140 | #define RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT (0x01U) | ||
141 | |||
142 | /** MCU Nav MCRC local events (LEVI) */ | ||
143 | #define RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI (0x00U) | ||
144 | /** Total MCU Nav MCRC subtypes. Update when subtypes are added */ | ||
145 | #define RESASG_SUBTYPE_MCU_NAV_MCRC_CNT (0x01U) | ||
146 | |||
147 | /** Main Nav UDMAP trigger events */ | ||
148 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER (0x00U) | ||
149 | /** Nav UDMAP driver high capacity transmit channels */ | ||
150 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN (0x01U) | ||
151 | /** Main Nav UDMAP driver standard transmit channels */ | ||
152 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN (0x02U) | ||
153 | /** Main Nav UDMAP driver external transmit channels */ | ||
154 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN (0x03U) | ||
155 | /** Main Nav UDMAP driver high capacity receive channels */ | ||
156 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN (0x04U) | ||
157 | /** Main Nav UDMAP driver standard receive channels */ | ||
158 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN (0x05U) | ||
159 | /** Main Nav UDMAP driver common receive flows used by receive channel | ||
160 | * RCHAN_RFLOW_RNG parameters */ | ||
161 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON (0x06U) | ||
162 | /** Main Nav UDMAP driver global config invalid flow OES register */ | ||
163 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES (0x07U) | ||
164 | /** Main Nav UDMAP driver global config register region rd/wr access */ | ||
165 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG (0x08U) | ||
166 | /** Total Main Nav UDMAP subtypes. Update when subtypes added */ | ||
167 | #define RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT (0x09U) | ||
168 | |||
169 | /** MCU Nav UDMAP trigger events */ | ||
170 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER (0x00U) | ||
171 | /** MCU Nav UDMAP driver high capacity transmit channels */ | ||
172 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN (0x01U) | ||
173 | /** MCU Nav UDMAP driver standard transmit channels */ | ||
174 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN (0x02U) | ||
175 | /** MCU Nav UDMAP driver high capacity receive channels */ | ||
176 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN (0x03U) | ||
177 | /** MCU Nav UDMAP driver standard receive channels */ | ||
178 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN (0x04U) | ||
179 | /** MCU Nav UDMAP driver common receive flows used by receive channel | ||
180 | * RCHAN_RFLOW_RNG parameters */ | ||
181 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON (0x05U) | ||
182 | /** MCU Nav UDMAP driver global config invalid flow OES register */ | ||
183 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES (0x06U) | ||
184 | /** MCU Nav UDMAP driver global config register region rd/wr access */ | ||
185 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG (0x07U) | ||
186 | /** Total MCU Nav UDMAP subtypes. Update when subtypes added */ | ||
187 | #define RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT (0x08U) | ||
188 | |||
189 | /** MSMC DRU events */ | ||
190 | #define RESASG_SUBTYPE_MSMC_DRU (0x00U) | ||
191 | /** Total MSMC subtypes. Update when subtypes added */ | ||
192 | #define RESASG_SUBTYPE_MSMC_CNT (0x01U) | ||
193 | |||
194 | /** Main Nav RA driver UDMAP tx rings */ | ||
195 | #define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX (0x00U) | ||
196 | /** Main Nav RA driver UDMAP rx rings */ | ||
197 | #define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX (0x01U) | ||
198 | /** Main Nav RA driver general purpose rings */ | ||
199 | #define RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP (0x02U) | ||
200 | /** Main Nav RA driver global config error OES register */ | ||
201 | #define RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES (0x03U) | ||
202 | /** Main Nav RA driver ring virtids */ | ||
203 | #define RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID (0x04U) | ||
204 | /** Total Main Nav RA subtypes. Update when subtypes are added */ | ||
205 | #define RESASG_SUBTYPE_MAIN_NAV_RA_CNT (0x05U) | ||
206 | |||
207 | /** MCU Nav RA driver UDMAP tx rings */ | ||
208 | #define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX (0x00U) | ||
209 | /** MCU Nav RA driver UDMAP rx rings */ | ||
210 | #define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX (0x01U) | ||
211 | /** MCU Nav RA driver general purpose rings */ | ||
212 | #define RESASG_SUBTYPE_MCU_NAV_RA_RING_GP (0x02U) | ||
213 | /** MCU Nav RA driver global config error OES register */ | ||
214 | #define RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES (0x03U) | ||
215 | /** MCU Nav RA driver ring virtids */ | ||
216 | #define RESASG_SUBTYPE_MCU_NAV_RA_VIRTID (0x04U) | ||
217 | /** Total MCU Nav RA subtypes. Update when subtypes added */ | ||
218 | #define RESASG_SUBTYPE_MCU_NAV_RA_CNT (0x05U) | ||
219 | |||
220 | /** GIC IRQ inputs (64 - 127) from Main Nav */ | ||
221 | #define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 (0x00U) | ||
222 | /** GIC IRQ inputs (392 - 423) from Main GPIO IR */ | ||
223 | #define RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO (0x01U) | ||
224 | /** GIC IRQ inputs (448 - 503) from Main Nav */ | ||
225 | #define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 (0x02U) | ||
226 | /** GIC IRQ inputs (544 - 559) from Compare event IR */ | ||
227 | #define RESASG_SUBTYPE_GIC_IRQ_COMP_EVT (0x03U) | ||
228 | /** GIC IRQ inputs (712 - 727) from Wakeup GPIO IR */ | ||
229 | #define RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO (0x04U) | ||
230 | /** Total GIC IRQ subtypes. Update when subtypes added */ | ||
231 | #define RESASG_SUBTYPE_GIC_IRQ_CNT (0x05U) | ||
232 | |||
233 | /** Pulsar core 0 VIM IRQ inputs (64 - 95) from MCU Nav */ | ||
234 | #define RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV (0x00U) | ||
235 | /** Pulsar core 0 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */ | ||
236 | #define RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO (0x01U) | ||
237 | /** Pulsar core 0 VIM IRQ inputs (160 - 223) from Main2MCU level IR */ | ||
238 | #define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL (0x02U) | ||
239 | /** Pulsar core 0 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */ | ||
240 | #define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS (0x03U) | ||
241 | /** Total Pulsar core 0 IRQ subtypes. Update when subtypes added */ | ||
242 | #define RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT (0x04U) | ||
243 | |||
244 | /** Pulsar core 1 VIM IRQ inputs (64 - 95) from MCU Nav */ | ||
245 | #define RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV (0x00U) | ||
246 | /** Pulsar core 1 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */ | ||
247 | #define RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO (0x01U) | ||
248 | /** Pulsar core 1 VIM IRQ inputs (160 - 223) from Main2MCU level IR */ | ||
249 | #define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL (0x02U) | ||
250 | /** Pulsar core 1 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */ | ||
251 | #define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS (0x03U) | ||
252 | /** Total Pulsar core 1 IRQ subtypes. Update when subtypes added */ | ||
253 | #define RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT (0x04U) | ||
254 | |||
255 | /** ICSSG0 IRQ inputs (110 - 117) from Main Nav */ | ||
256 | #define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV (0x00U) | ||
257 | /** ICSSG0 IRQ inputs (152 - 159) from Main GPIO IR */ | ||
258 | #define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO (0x01U) | ||
259 | /** Total ICSSG 0 IRQ subtypes. Update when subtypes added */ | ||
260 | #define RESASG_SUBTYPE_ICSSG0_IRQ_CNT (0x02U) | ||
261 | |||
262 | /** ICSSG1 IRQ inputs (110 - 117) from Main Nav */ | ||
263 | #define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV (0x00U) | ||
264 | /** ICSSG1 IRQ inputs (152 - 159) from Main GPIO IR */ | ||
265 | #define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO (0x01U) | ||
266 | /** Total ICSSG1 IRQ subtypes. Update when subtypes added */ | ||
267 | #define RESASG_SUBTYPE_ICSSG1_IRQ_CNT (0x02U) | ||
268 | |||
269 | /** ICSSG2 IRQ inputs (110 - 117) from Main Nav */ | ||
270 | #define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV (0x00U) | ||
271 | /** ICSSG2 IRQ inputs (152 - 159) from Main GPIO IR */ | ||
272 | #define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO (0x01U) | ||
273 | /** Total ICSSG2 IRQ subtypes. Update when subtypes added */ | ||
274 | #define RESASG_SUBTYPE_ICSSG2_IRQ_CNT (0x02U) | ||
275 | |||
276 | /** | ||
277 | * Total number of unique resource types for AM6 | ||
278 | */ | ||
279 | #define RESASG_UTYPE_CNT \ | ||
280 | (RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT + \ | ||
281 | RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT + \ | ||
282 | RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT + \ | ||
283 | RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT + \ | ||
284 | RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT + \ | ||
285 | RESASG_SUBTYPE_MCU_NAV_MCRC_CNT + \ | ||
286 | RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT + \ | ||
287 | RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT + \ | ||
288 | RESASG_SUBTYPE_MSMC_CNT + \ | ||
289 | RESASG_SUBTYPE_MAIN_NAV_RA_CNT + \ | ||
290 | RESASG_SUBTYPE_MCU_NAV_RA_CNT + \ | ||
291 | RESASG_SUBTYPE_GIC_IRQ_CNT + \ | ||
292 | RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT + \ | ||
293 | RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT + \ | ||
294 | RESASG_SUBTYPE_ICSSG0_IRQ_CNT + \ | ||
295 | RESASG_SUBTYPE_ICSSG1_IRQ_CNT + \ | ||
296 | RESASG_SUBTYPE_ICSSG2_IRQ_CNT) | ||
297 | |||
298 | #endif /* RESASG_TYPES_H */ | ||