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authorDave Gerlach2020-03-24 22:44:30 -0500
committerDave Gerlach2020-03-26 19:54:51 -0500
commit721ebec2a3d1f93248ce5f1660f35b50dd31780c (patch)
tree0ccbf2eb7f78fa70cb7ce67411342197153ac3a2 /include
parentca0b17080a239e6eb69f7b36de6cfd36ddc67b4d (diff)
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soc: am65x_sr2: Introduce support for evm
Add support for AM65x SR2 SoCs which have slightly different board configuration requirements than AM65x and also require a specific firmware image. Also update the SYSFW_GIT_HASH to point to the latest ti-linux-firmware repo which contains v2019.12b SR2 binary. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/soc/am65x_sr2/devices.h282
-rw-r--r--include/soc/am65x_sr2/hosts.h86
-rw-r--r--include/soc/am65x_sr2/resasg_types.h174
3 files changed, 542 insertions, 0 deletions
diff --git a/include/soc/am65x_sr2/devices.h b/include/soc/am65x_sr2/devices.h
new file mode 100644
index 000000000..ccdbc22d8
--- /dev/null
+++ b/include/soc/am65x_sr2/devices.h
@@ -0,0 +1,282 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SOC_AM6_DEVICES_H
36#define SOC_AM6_DEVICES_H
37
38#define AM6_DEV_MCU_ADC0 0
39#define AM6_DEV_MCU_ADC1 1
40#define AM6_DEV_CAL0 2
41#define AM6_DEV_CMPEVENT_INTRTR0 3
42#define AM6_DEV_MCU_CPSW0 5
43#define AM6_DEV_CPT2_AGGR0 6
44#define AM6_DEV_MCU_CPT2_AGGR0 7
45#define AM6_DEV_STM0 8
46#define AM6_DEV_DCC0 9
47#define AM6_DEV_DCC1 10
48#define AM6_DEV_DCC2 11
49#define AM6_DEV_DCC3 12
50#define AM6_DEV_DCC4 13
51#define AM6_DEV_DCC5 14
52#define AM6_DEV_DCC6 15
53#define AM6_DEV_DCC7 16
54#define AM6_DEV_MCU_DCC0 17
55#define AM6_DEV_MCU_DCC1 18
56#define AM6_DEV_MCU_DCC2 19
57#define AM6_DEV_DDRSS0 20
58#define AM6_DEV_DEBUGSS_WRAP0 21
59#define AM6_DEV_WKUP_DMSC0 22
60#define AM6_DEV_TIMER0 23
61#define AM6_DEV_TIMER1 24
62#define AM6_DEV_TIMER10 25
63#define AM6_DEV_TIMER11 26
64#define AM6_DEV_TIMER2 27
65#define AM6_DEV_TIMER3 28
66#define AM6_DEV_TIMER4 29
67#define AM6_DEV_TIMER5 30
68#define AM6_DEV_TIMER6 31
69#define AM6_DEV_TIMER7 32
70#define AM6_DEV_TIMER8 33
71#define AM6_DEV_TIMER9 34
72#define AM6_DEV_MCU_TIMER0 35
73#define AM6_DEV_MCU_TIMER1 36
74#define AM6_DEV_MCU_TIMER2 37
75#define AM6_DEV_MCU_TIMER3 38
76#define AM6_DEV_ECAP0 39
77#define AM6_DEV_EHRPWM0 40
78#define AM6_DEV_EHRPWM1 41
79#define AM6_DEV_EHRPWM2 42
80#define AM6_DEV_EHRPWM3 43
81#define AM6_DEV_EHRPWM4 44
82#define AM6_DEV_EHRPWM5 45
83#define AM6_DEV_ELM0 46
84#define AM6_DEV_MMCSD0 47
85#define AM6_DEV_MMCSD1 48
86#define AM6_DEV_EQEP0 49
87#define AM6_DEV_EQEP1 50
88#define AM6_DEV_EQEP2 51
89#define AM6_DEV_ESM0 52
90#define AM6_DEV_MCU_ESM0 53
91#define AM6_DEV_WKUP_ESM0 54
92#define AM6_DEV_FSS_MCU_0 55
93#define AM6_DEV_GIC0 56
94#define AM6_DEV_GPIO0 57
95#define AM6_DEV_GPIO1 58
96#define AM6_DEV_WKUP_GPIO0 59
97#define AM6_DEV_GPMC0 60
98#define AM6_DEV_GTC0 61
99#define AM6_DEV_PRU_ICSSG0 62
100#define AM6_DEV_PRU_ICSSG1 63
101#define AM6_DEV_PRU_ICSSG2 64
102#define AM6_DEV_GPU0 65
103#define AM6_DEV_CCDEBUGSS0 66
104#define AM6_DEV_DSS0 67
105#define AM6_DEV_DEBUGSS0 68
106#define AM6_DEV_EFUSE0 69
107#define AM6_DEV_PSC0 70
108#define AM6_DEV_MCU_DEBUGSS0 71
109#define AM6_DEV_MCU_EFUSE0 72
110#define AM6_DEV_PBIST0 73
111#define AM6_DEV_PBIST1 74
112#define AM6_DEV_MCU_PBIST0 75
113#define AM6_DEV_PLLCTRL0 76
114#define AM6_DEV_WKUP_PLLCTRL0 77
115#define AM6_DEV_MCU_ROM0 78
116#define AM6_DEV_WKUP_PSC0 79
117#define AM6_DEV_WKUP_VTM0 80
118#define AM6_DEV_DEBUGSUSPENDRTR0 81
119#define AM6_DEV_CBASS0 82
120#define AM6_DEV_CBASS_DEBUG0 83
121#define AM6_DEV_CBASS_FW0 84
122#define AM6_DEV_CBASS_INFRA0 85
123#define AM6_DEV_ECC_AGGR0 86
124#define AM6_DEV_ECC_AGGR1 87
125#define AM6_DEV_ECC_AGGR2 88
126#define AM6_DEV_MCU_CBASS0 89
127#define AM6_DEV_MCU_CBASS_DEBUG0 90
128#define AM6_DEV_MCU_CBASS_FW0 91
129#define AM6_DEV_MCU_ECC_AGGR0 92
130#define AM6_DEV_MCU_ECC_AGGR1 93
131#define AM6_DEV_WKUP_CBASS0 94
132#define AM6_DEV_WKUP_ECC_AGGR0 95
133#define AM6_DEV_WKUP_CBASS_FW0 96
134#define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97
135#define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98
136#define AM6_DEV_CTRL_MMR0 99
137#define AM6_DEV_GPIOMUX_INTRTR0 100
138#define AM6_DEV_PLL_MMR0 101
139#define AM6_DEV_MCU_MCAN0 102
140#define AM6_DEV_MCU_MCAN1 103
141#define AM6_DEV_MCASP0 104
142#define AM6_DEV_MCASP1 105
143#define AM6_DEV_MCASP2 106
144#define AM6_DEV_MCU_CTRL_MMR0 107
145#define AM6_DEV_MCU_PLL_MMR0 108
146#define AM6_DEV_MCU_SEC_MMR0 109
147#define AM6_DEV_I2C0 110
148#define AM6_DEV_I2C1 111
149#define AM6_DEV_I2C2 112
150#define AM6_DEV_I2C3 113
151#define AM6_DEV_MCU_I2C0 114
152#define AM6_DEV_WKUP_I2C0 115
153#define AM6_DEV_MCU_MSRAM0 116
154#define AM6_DEV_DFTSS0 117
155#define AM6_DEV_NAVSS0 118
156#define AM6_DEV_MCU_NAVSS0 119
157#define AM6_DEV_PCIE0 120
158#define AM6_DEV_PCIE1 121
159#define AM6_DEV_PDMA_DEBUG0 122
160#define AM6_DEV_PDMA0 123
161#define AM6_DEV_PDMA1 124
162#define AM6_DEV_MCU_PDMA0 125
163#define AM6_DEV_MCU_PDMA1 126
164#define AM6_DEV_MCU_PSRAM0 127
165#define AM6_DEV_PSRAMECC0 128
166#define AM6_DEV_MCU_ARMSS0 129
167#define AM6_DEV_RTI0 130
168#define AM6_DEV_RTI1 131
169#define AM6_DEV_RTI2 132
170#define AM6_DEV_RTI3 133
171#define AM6_DEV_MCU_RTI0 134
172#define AM6_DEV_MCU_RTI1 135
173#define AM6_DEV_SA2_UL0 136
174#define AM6_DEV_MCSPI0 137
175#define AM6_DEV_MCSPI1 138
176#define AM6_DEV_MCSPI2 139
177#define AM6_DEV_MCSPI3 140
178#define AM6_DEV_MCSPI4 141
179#define AM6_DEV_MCU_MCSPI0 142
180#define AM6_DEV_MCU_MCSPI1 143
181#define AM6_DEV_MCU_MCSPI2 144
182#define AM6_DEV_TIMESYNC_INTRTR0 145
183#define AM6_DEV_UART0 146
184#define AM6_DEV_UART1 147
185#define AM6_DEV_UART2 148
186#define AM6_DEV_MCU_UART0 149
187#define AM6_DEV_WKUP_UART0 150
188#define AM6_DEV_USB3SS0 151
189#define AM6_DEV_USB3SS1 152
190#define AM6_DEV_SERDES0 153
191#define AM6_DEV_SERDES1 154
192#define AM6_DEV_WKUP_CTRL_MMR0 155
193#define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156
194#define AM6_DEV_BOARD0 157
195#define AM6_DEV_MCU_ARMSS0_CPU0 159
196#define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161
197#define AM6_DEV_NAVSS0_CPTS0 163
198#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164
199#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165
200#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166
201#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3 167
202#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4 168
203#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5 169
204#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6 170
205#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7 171
206#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8 172
207#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9 173
208#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174
209#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175
210#define AM6_DEV_NAVSS0_MCRC0 176
211#define AM6_DEV_NAVSS0_PVU0 177
212#define AM6_DEV_NAVSS0_PVU1 178
213#define AM6_DEV_NAVSS0_UDMASS_INTA0 179
214#define AM6_DEV_NAVSS0_MODSS_INTA0 180
215#define AM6_DEV_NAVSS0_MODSS_INTA1 181
216#define AM6_DEV_NAVSS0_INTR_ROUTER_0 182
217#define AM6_DEV_NAVSS0_TIMER_MGR0 183
218#define AM6_DEV_NAVSS0_TIMER_MGR1 184
219#define AM6_DEV_NAVSS0_PROXY0 185
220#define AM6_DEV_NAVSS0_RINGACC0 187
221#define AM6_DEV_NAVSS0_UDMAP0 188
222#define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189
223#define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190
224#define AM6_DEV_MCU_NAVSS0_PROXY0 191
225#define AM6_DEV_MCU_NAVSS0_MCRC0 193
226#define AM6_DEV_MCU_NAVSS0_UDMAP0 194
227#define AM6_DEV_MCU_NAVSS0_RINGACC0 195
228#define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197
229#define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198
230#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199
231#define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200
232#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201
233#define AM6_DEV_COMPUTE_CLUSTER_A53_0 202
234#define AM6_DEV_COMPUTE_CLUSTER_A53_1 203
235#define AM6_DEV_COMPUTE_CLUSTER_A53_2 204
236#define AM6_DEV_COMPUTE_CLUSTER_A53_3 205
237#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206
238#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207
239#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208
240#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209
241#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210
242#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211
243#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212
244#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213
245#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214
246#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215
247#define AM6_DEV_OLDI_TX_CORE_MAIN_0 216
248#define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217
249#define AM6_DEV_ICEMELTER_WKUP_0 218
250#define AM6_DEV_K3_LED_MAIN_0 219
251#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220
252#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221
253#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222
254#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223
255#define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224
256#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225
257#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226
258#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227
259#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228
260#define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229
261#define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230
262#define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231
263#define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232
264#define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233
265#define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234
266#define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235
267#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD 236
268#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD 237
269#define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD 238
270#define AM6_DEV_DUMMY_IP_LPSC_DMSC_VD 239
271#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD 240
272#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD 241
273#define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD 242
274#define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD 243
275#define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD 244
276#define AM6_DEV_MCU_ARMSS0_CPU1 245
277#define AM6_DEV_MCU_FSS0_FSAS_0 246
278#define AM6_DEV_MCU_FSS0_HYPERBUS0 247
279#define AM6_DEV_MCU_FSS0_OSPI_0 248
280#define AM6_DEV_MCU_FSS0_OSPI_1 249
281
282#endif /* SOC_AM6_DEVICES_H */
diff --git a/include/soc/am65x_sr2/hosts.h b/include/soc/am65x_sr2/hosts.h
new file mode 100644
index 000000000..b398a6418
--- /dev/null
+++ b/include/soc/am65x_sr2/hosts.h
@@ -0,0 +1,86 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36#ifndef AM6_HOSTS_H
37#define AM6_HOSTS_H
38
39/* Host IDs for AM6 Device */
40
41/** DMSC(Secure): Device Management and Security Control */
42#define HOST_ID_DMSC (0U)
43/** r5_0(Non Secure): Cortex R5 Context 0 on MCU island */
44#define HOST_ID_R5_0 (3U)
45/** r5_1(Secure): Cortex R5 Context 1 on MCU island(Boot) */
46#define HOST_ID_R5_1 (4U)
47/** r5_2(Non Secure): Cortex R5 Context 2 on MCU island */
48#define HOST_ID_R5_2 (5U)
49/** r5_3(Secure): Cortex R5 Context 3 on MCU island */
50#define HOST_ID_R5_3 (6U)
51/** a53_0(Secure): Cortex A53 context 0 on Main island */
52#define HOST_ID_A53_0 (10U)
53/** a53_1(Secure): Cortex A53 context 1 on Main island */
54#define HOST_ID_A53_1 (11U)
55/** a53_2(Non Secure): Cortex A53 context 2 on Main island */
56#define HOST_ID_A53_2 (12U)
57/** a53_3(Non Secure): Cortex A53 context 3 on Main island */
58#define HOST_ID_A53_3 (13U)
59/** a53_4(Non Secure): Cortex A53 context 4 on Main island */
60#define HOST_ID_A53_4 (14U)
61/** a53_5(Non Secure): Cortex A53 context 5 on Main island */
62#define HOST_ID_A53_5 (15U)
63/** a53_6(Non Secure): Cortex A53 context 6 on Main island */
64#define HOST_ID_A53_6 (16U)
65/** a53_7(Non Secure): Cortex A53 context 7 on Main island */
66#define HOST_ID_A53_7 (17U)
67/** gpu_0(Non Secure): SGX544 Context 0 on Main island */
68#define HOST_ID_GPU_0 (30U)
69/** gpu_1(Non Secure): SGX544 Context 1 on Main island */
70#define HOST_ID_GPU_1 (31U)
71/** icssg_0(Non Secure): ICSS Context 0 on Main island */
72#define HOST_ID_ICSSG_0 (50U)
73/** icssg_1(Non Secure): ICSS Context 1 on Main island */
74#define HOST_ID_ICSSG_1 (51U)
75/** icssg_2(Non Secure): ICSS Context 2 on Main island */
76#define HOST_ID_ICSSG_2 (52U)
77
78/** Host catch all. Used in board configuration resource assignments to
79 * define resource ranges useable by all hosts. Cannot be used as a host
80 * in TISCI message headers */
81#define HOST_ID_ALL (128U)
82
83/** Number of unique hosts on the AM6 SoC */
84#define HOST_ID_CNT (19U)
85
86#endif /* AM6_HOSTS_H */
diff --git a/include/soc/am65x_sr2/resasg_types.h b/include/soc/am65x_sr2/resasg_types.h
new file mode 100644
index 000000000..91646d614
--- /dev/null
+++ b/include/soc/am65x_sr2/resasg_types.h
@@ -0,0 +1,174 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef RESASG_TYPES_H
36#define RESASG_TYPES_H
37
38/**
39 * Resource assignment type shift
40 */
41#define RESASG_TYPE_SHIFT (0x0006U)
42/**
43 * Resource assignment type mask
44 */
45#define RESASG_TYPE_MASK (0xFFC0U)
46/**
47 * Resource assignment subtype shift
48 */
49#define RESASG_SUBTYPE_SHIFT (0x0000U)
50/**
51 * Resource assignment subtype mask
52 */
53#define RESASG_SUBTYPE_MASK (0x003FU)
54/**
55 * Macro to create unique resource assignment types using type and subtype
56 */
57
58#define RESASG_UTYPE(type, subtype) \
59 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) |\
60 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
61
62/**
63 * IA subtypes definitions
64 */
65#define RESASG_SUBTYPE_IA_VINT (0x000AU)
66#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
67#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
68#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
69#define RESASG_SUBTYPES_IA_CNT (0x0004U)
70
71/**
72 * IRQ subtypes definitions
73 */
74#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
75#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
76#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0002U)
77#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0003U)
78#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
79#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0000U)
80#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0004U)
81#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 (0x0002U)
82#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
83#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
84#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
85#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
86#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
87#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
88#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
89#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
90#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
91#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
92#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
93#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
94#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
95#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
96#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0004U)
97#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0005U)
98#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0006U)
99#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0007U)
100#define RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
101#define RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
102#define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0001U)
103#define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
104#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
105#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
106#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
107#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
108#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
109#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
110#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
111#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
112#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
113#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
114#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
115#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
116#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
117#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
118#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
119#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
120#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
121#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
122#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
123#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
124#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
125#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
126#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
127#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
128#define RESASG_SUBTYPE_WKUP_DMSC0_CORTEX_M3_0_NVIC_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
129#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
130#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
131#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0002U)
132#define RESASG_SUBTYPES_IRQ_CNT (0x003AU)
133
134/**
135 * Proxy subtypes definitions
136 */
137#define RESASG_SUBTYPE_PROXY_PROXIES (0x0000U)
138#define RESASG_SUBTYPES_PROXY_CNT (0x0001U)
139
140/**
141 * RA subtypes definitions
142 */
143#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
144#define RESASG_SUBTYPE_RA_GP (0x0001U)
145#define RESASG_SUBTYPE_RA_UDMAP_RX (0x0002U)
146#define RESASG_SUBTYPE_RA_UDMAP_TX (0x0003U)
147#define RESASG_SUBTYPE_RA_UDMAP_TX_EXT (0x0004U)
148#define RESASG_SUBTYPE_RA_UDMAP_RX_H (0x0005U)
149#define RESASG_SUBTYPE_RA_UDMAP_TX_H (0x0007U)
150#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
151#define RESASG_SUBTYPE_RA_MONITORS (0x000BU)
152#define RESASG_SUBTYPES_RA_CNT (0x0009U)
153
154/**
155 * UDMAP subtypes definitions
156 */
157#define RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON (0x0000U)
158#define RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES (0x0001U)
159#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
160#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
161#define RESASG_SUBTYPE_UDMAP_RX_CHAN (0x000AU)
162#define RESASG_SUBTYPE_UDMAP_RX_HCHAN (0x000BU)
163#define RESASG_SUBTYPE_UDMAP_TX_CHAN (0x000DU)
164#define RESASG_SUBTYPE_UDMAP_TX_ECHAN (0x000EU)
165#define RESASG_SUBTYPE_UDMAP_TX_HCHAN (0x000FU)
166#define RESASG_SUBTYPES_UDMAP_CNT (0x0009U)
167
168
169/**
170 * Total number of unique resource types for SoC
171 */
172#define RESASG_UTYPE_CNT 102U
173
174#endif /* RESASG_TYPES_H */