include: j721e: j7200: Update headers from SYSFW 2020.07-RC2

Update header files from System firmware 2020.07.
This includes many renames for the device macros.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

3 files changed, 51 insertions, 30 deletions

diff --git a/include/soc/j7200/devices.h b/include/soc/j7200/devices.h
index bf8e60ea4..11cc026aa 100644
--- a/include/soc/j7200/devices.h
+++ b/include/soc/j7200/devices.h
@@ -39,7 +39,7 @@
 #define J7200_DEV_MCU_ADC1 1
 #define J7200_DEV_ATL0 2
 #define J7200_DEV_COMPUTE_CLUSTER0 3
-#define J7200_DEV_A72SS0 4
+#define J7200_DEV_A72SS0_CORE0 4
 #define J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
 #define J7200_DEV_COMPUTE_CLUSTER0_CLEC 6
 #define J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE 7
@@ -195,8 +195,8 @@
 #define J7200_DEV_WKUP_I2C0 197
 #define J7200_DEV_NAVSS0 199
 #define J7200_DEV_NAVSS0_CPTS_0 201
-#define J7200_DEV_A72SS0_CORE0 202
-#define J7200_DEV_A72SS0_CORE1 203
+#define J7200_DEV_A72SS0_CORE0_0 202
+#define J7200_DEV_A72SS0_CORE0_1 203
 #define J7200_DEV_NAVSS0_DTI_0 206
 #define J7200_DEV_NAVSS0_MODSS_INTA_0 207
 #define J7200_DEV_NAVSS0_MODSS_INTA_1 208
diff --git a/include/soc/j721e/devices.h b/include/soc/j721e/devices.h
index 2d0458a79..1c2ab11ac 100644
--- a/include/soc/j721e/devices.h
+++ b/include/soc/j721e/devices.h
@@ -35,10 +35,10 @@
 #ifndef SOC_J721E_DEVICES_H
 #define SOC_J721E_DEVICES_H
 
-#define J721E_DEV_MCU_ADC0 0
-#define J721E_DEV_MCU_ADC1 1
+#define J721E_DEV_MCU_ADC12_16FFC0 0
+#define J721E_DEV_MCU_ADC12_16FFC1 1
 #define J721E_DEV_ATL0 2
-#define J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 3
+#define J721E_DEV_COMPUTE_CLUSTER0 3
 #define J721E_DEV_A72SS0 4
 #define J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
 #define J721E_DEV_COMPUTE_CLUSTER0_CLEC 6
@@ -57,7 +57,7 @@
 #define J721E_DEV_CPSW0 19
 #define J721E_DEV_CPT2_AGGR0 20
 #define J721E_DEV_CPT2_AGGR1 21
-#define J721E_DEV_DMSC_WKUP_0 22
+#define J721E_DEV_WKUP_DMSC0 22
 #define J721E_DEV_CPT2_AGGR2 23
 #define J721E_DEV_MCU_CPT2_AGGR0 24
 #define J721E_DEV_CSI_PSILSS0 25
@@ -83,7 +83,7 @@
 #define J721E_DEV_MCU_DCC1 45
 #define J721E_DEV_MCU_DCC2 46
 #define J721E_DEV_DDR0 47
-#define J721E_DEV_DMPAC_TOP_MAIN_0 48
+#define J721E_DEV_DMPAC0 48
 #define J721E_DEV_TIMER0 49
 #define J721E_DEV_TIMER1 50
 #define J721E_DEV_TIMER2 51
@@ -134,7 +134,7 @@
 #define J721E_DEV_ESM0 97
 #define J721E_DEV_MCU_ESM0 98
 #define J721E_DEV_WKUP_ESM0 99
-#define J721E_DEV_FSS_MCU_0 100
+#define J721E_DEV_MCU_FSS0 100
 #define J721E_DEV_MCU_FSS0_FSAS_0 101
 #define J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 102
 #define J721E_DEV_MCU_FSS0_OSPI_0 103
@@ -158,7 +158,7 @@
 #define J721E_DEV_C66SS0_INTROUTER0 121
 #define J721E_DEV_C66SS1_INTROUTER0 122
 #define J721E_DEV_CMPEVENT_INTRTR0 123
-#define J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0 124
+#define J721E_DEV_GPU0 124
 #define J721E_DEV_GPU0_GPU_0 125
 #define J721E_DEV_GPU0_GPUCORE_0 126
 #define J721E_DEV_LED0 127
@@ -173,8 +173,8 @@
 #define J721E_DEV_WKUP_GPIOMUX_INTRTR0 137
 #define J721E_DEV_WKUP_PSC0 138
 #define J721E_DEV_AASRC0 139
-#define J721E_DEV_K3_C66_COREPAC_MAIN_0 140
-#define J721E_DEV_K3_C66_COREPAC_MAIN_1 141
+#define J721E_DEV_C66SS0 140
+#define J721E_DEV_C66SS1 141
 #define J721E_DEV_C66SS0_CORE0 142
 #define J721E_DEV_C66SS1_CORE0 143
 #define J721E_DEV_DECODER0 144
@@ -229,7 +229,7 @@
 #define J721E_DEV_MCU_I2C0 194
 #define J721E_DEV_MCU_I2C1 195
 #define J721E_DEV_WKUP_I2C0 197
-#define J721E_DEV_NAVSS512L_MAIN_0 199
+#define J721E_DEV_NAVSS0 199
 #define J721E_DEV_NAVSS0_CPTS_0 201
 #define J721E_DEV_A72SS0_CORE0 202
 #define J721E_DEV_A72SS0_CORE1 203
@@ -259,24 +259,24 @@
 #define J721E_DEV_NAVSS0_TCU_0 229
 #define J721E_DEV_NAVSS0_TIMERMGR_0 230
 #define J721E_DEV_NAVSS0_TIMERMGR_1 231
-#define J721E_DEV_NAVSS_MCU_J7_MCU_0 232
-#define J721E_DEV_MCU_NAVSS0_INTAGGR_0 233
-#define J721E_DEV_MCU_NAVSS0_PROXY_0 234
-#define J721E_DEV_MCU_NAVSS0_RINGACC_0 235
+#define J721E_DEV_MCU_NAVSS0 232
+#define J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 233
+#define J721E_DEV_MCU_NAVSS0_PROXY0 234
+#define J721E_DEV_MCU_NAVSS0_RINGACC0 235
 #define J721E_DEV_MCU_NAVSS0_UDMAP_0 236
-#define J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0 237
+#define J721E_DEV_MCU_NAVSS0_INTR_0 237
 #define J721E_DEV_MCU_NAVSS0_MCRC_0 238
 #define J721E_DEV_PCIE0 239
 #define J721E_DEV_PCIE1 240
 #define J721E_DEV_PCIE2 241
 #define J721E_DEV_PCIE3 242
-#define J721E_DEV_PULSAR_SL_MAIN_0 243
-#define J721E_DEV_PULSAR_SL_MAIN_1 244
+#define J721E_DEV_R5FSS0 243
+#define J721E_DEV_R5FSS1 244
 #define J721E_DEV_R5FSS0_CORE0 245
 #define J721E_DEV_R5FSS0_CORE1 246
 #define J721E_DEV_R5FSS1_CORE0 247
 #define J721E_DEV_R5FSS1_CORE1 248
-#define J721E_DEV_PULSAR_SL_MCU_0 249
+#define J721E_DEV_MCU_R5FSS0 249
 #define J721E_DEV_MCU_R5FSS0_CORE0 250
 #define J721E_DEV_MCU_R5FSS0_CORE1 251
 #define J721E_DEV_RTI0 252
@@ -317,7 +317,7 @@
 #define J721E_DEV_WKUP_UART0 287
 #define J721E_DEV_USB0 288
 #define J721E_DEV_USB1 289
-#define J721E_DEV_VPAC_TOP_MAIN_0 290
+#define J721E_DEV_VPAC0 290
 #define J721E_DEV_VPFE0 291
 #define J721E_DEV_SERDES_16G0 292
 #define J721E_DEV_SERDES_16G1 293
@@ -333,5 +333,21 @@
 #define J721E_DEV_MCU_NAVSS0_UDMASS 303
 #define J721E_DEV_DEBUGSS_WRAP0 304
 #define J721E_DEV_DMPAC0_SDE_0 305
+#define J721E_DEV_GPU0_DFT_PBIST_0 306
+#define J721E_DEV_C66SS0_PBIST0 307
+#define J721E_DEV_C66SS1_PBIST0 308
+#define J721E_DEV_PBIST0 309
+#define J721E_DEV_PBIST1 310
+#define J721E_DEV_PBIST2 311
+#define J721E_DEV_PBIST3 312
+#define J721E_DEV_PBIST4 313
+#define J721E_DEV_PBIST5 314
+#define J721E_DEV_PBIST6 315
+#define J721E_DEV_PBIST7 316
+#define J721E_DEV_PBIST9 317
+#define J721E_DEV_PBIST10 318
+#define J721E_DEV_MCU_PBIST0 319
+#define J721E_DEV_MCU_PBIST1 320
+#define J721E_DEV_C71X_0_PBIST_VD 321
 
 #endif /* SOC_J721E_DEVICES_H */
diff --git a/include/soc/j721e/hosts.h b/include/soc/j721e/hosts.h
index 7a55f6084..a6595eecc 100644
--- a/include/soc/j721e/hosts.h
+++ b/include/soc/j721e/hosts.h
@@ -35,10 +35,10 @@
 #ifndef J721E_HOSTS_H
 #define J721E_HOSTS_H
 
-/* Host IDs for J721E Device */
-
-/** DMSC(Secure): Device Management and Security Control */
+/** DMSC(Secure): Security Controller */
 #define HOST_ID_DMSC (0U)
+/** DM(Non Secure): Device Management */
+#define HOST_ID_DM (254U)
 /** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */
 #define HOST_ID_MCU_0_R5_0 (3U)
 /** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */
@@ -89,13 +89,18 @@
 #define HOST_ID_MAIN_1_R5_3 (43U)
 /** ICSSG_0(Non Secure): ICSSG context 0 on Main island */
 #define HOST_ID_ICSSG_0 (50U)
+/** DM2DMSC(Secure): DM to DMSC communication */
+#define HOST_ID_DM2DMSC (250U)
+/** DMSC2DM(Non Secure): DMSC to DM communication */
+#define HOST_ID_DMSC2DM (251U)
 
-/** Host catch all.  Used in board configuration resource assignments to
- *  define resource ranges useable by all hosts.  Cannot be used as a host
- *  in TISCI message headers */
+/**
+ * Host catch all. Used in board configuration resource assignments to define
+ * resource ranges useable by all hosts. Cannot be used
+ */
 #define HOST_ID_ALL (128U)
 
-/** Number of unique hosts on the J721E SoC */
-#define HOST_ID_CNT (26U)
+/** Number of unique hosts on the SoC */
+#define HOST_ID_CNT (29U)
 
 #endif /* J721E_HOSTS_H */