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| author | Dave Gerlach | 2020-04-02 22:01:21 -0500 |
|---|---|---|
| committer | Dave Gerlach | 2020-04-22 09:24:38 -0500 |
| commit | c9e26b71b5349d885eb0866e0edffd983f5d505b (patch) | |
| tree | 446deea32d7689ecad219e314b8da32de894dfd3 /include | |
| parent | 93c0ee5566a075d1f82678b3ba607bfe3f0d1ce6 (diff) | |
| download | k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.tar.gz k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.tar.xz k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.zip | |
am65x_sr2: Update to ABI 3.0 resource types
Update the AM65x SR2 RM board configuration to use ABI 3.0 resource type
definitions.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/am65x_sr2/resasg_types.h | 65 |
1 files changed, 4 insertions, 61 deletions
diff --git a/include/soc/am65x_sr2/resasg_types.h b/include/soc/am65x_sr2/resasg_types.h index 91646d614..c76590a4f 100644 --- a/include/soc/am65x_sr2/resasg_types.h +++ b/include/soc/am65x_sr2/resasg_types.h | |||
| @@ -69,67 +69,10 @@ | |||
| 69 | #define RESASG_SUBTYPES_IA_CNT (0x0004U) | 69 | #define RESASG_SUBTYPES_IA_CNT (0x0004U) |
| 70 | 70 | ||
| 71 | /** | 71 | /** |
| 72 | * IRQ subtypes definitions | 72 | * IR subtypes definitions |
| 73 | */ | 73 | */ |
| 74 | #define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U) | 74 | #define RESASG_SUBTYPE_IR_OUTPUT (0x0000U) |
| 75 | #define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U) | 75 | #define RESASG_SUBTYPES_IR_CNT (0x0001U) |
| 76 | #define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0002U) | ||
| 77 | #define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0003U) | ||
| 78 | #define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U) | ||
| 79 | #define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0000U) | ||
| 80 | #define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0004U) | ||
| 81 | #define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 (0x0002U) | ||
| 82 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U) | ||
| 83 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U) | ||
| 84 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U) | ||
| 85 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U) | ||
| 86 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U) | ||
| 87 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U) | ||
| 88 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U) | ||
| 89 | #define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U) | ||
| 90 | #define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 91 | #define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U) | ||
| 92 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 93 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U) | ||
| 94 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U) | ||
| 95 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U) | ||
| 96 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0004U) | ||
| 97 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0005U) | ||
| 98 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0006U) | ||
| 99 | #define RESASG_SUBTYPE_NAVSS0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0007U) | ||
| 100 | #define RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 101 | #define RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 102 | #define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0001U) | ||
| 103 | #define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 104 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 105 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U) | ||
| 106 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U) | ||
| 107 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U) | ||
| 108 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U) | ||
| 109 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U) | ||
| 110 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U) | ||
| 111 | #define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U) | ||
| 112 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 113 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U) | ||
| 114 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U) | ||
| 115 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U) | ||
| 116 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U) | ||
| 117 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U) | ||
| 118 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U) | ||
| 119 | #define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U) | ||
| 120 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U) | ||
| 121 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U) | ||
| 122 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U) | ||
| 123 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U) | ||
| 124 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U) | ||
| 125 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U) | ||
| 126 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U) | ||
| 127 | #define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U) | ||
| 128 | #define RESASG_SUBTYPE_WKUP_DMSC0_CORTEX_M3_0_NVIC_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U) | ||
| 129 | #define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U) | ||
| 130 | #define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U) | ||
| 131 | #define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0002U) | ||
| 132 | #define RESASG_SUBTYPES_IRQ_CNT (0x003AU) | ||
| 133 | 76 | ||
| 134 | /** | 77 | /** |
| 135 | * Proxy subtypes definitions | 78 | * Proxy subtypes definitions |
| @@ -169,6 +112,6 @@ | |||
| 169 | /** | 112 | /** |
| 170 | * Total number of unique resource types for SoC | 113 | * Total number of unique resource types for SoC |
| 171 | */ | 114 | */ |
| 172 | #define RESASG_UTYPE_CNT 102U | 115 | #define RESASG_UTYPE_CNT 52U |
| 173 | 116 | ||
| 174 | #endif /* RESASG_TYPES_H */ | 117 | #endif /* RESASG_TYPES_H */ |