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authorLokesh Vutla2020-03-24 08:22:00 -0500
committerDave Gerlach2020-04-03 15:41:00 -0500
commitdb9b576019b674e822e8acf4252fb96ee4ed18e5 (patch)
treecde166e9469225f2848be9cffceb942ee266ff14 /include
parentd7e90ec350237720cf36c465bfa88178e81010c3 (diff)
downloadk3-image-gen-db9b576019b674e822e8acf4252fb96ee4ed18e5.tar.gz
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am65x: Update to ABI 3.0 resource types
Update the AM65x RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/soc/am65x/devices.h372
-rw-r--r--include/soc/am65x/resasg_types.h292
2 files changed, 232 insertions, 432 deletions
diff --git a/include/soc/am65x/devices.h b/include/soc/am65x/devices.h
index a1bc9211f..97479ff31 100644
--- a/include/soc/am65x/devices.h
+++ b/include/soc/am65x/devices.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * K3 System Firmware Board Configuration Data Definitions 2 * K3 System Firmware Board Configuration Data Definitions
3 * 3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
@@ -35,218 +35,165 @@
35#ifndef SOC_AM6_DEVICES_H 35#ifndef SOC_AM6_DEVICES_H
36#define SOC_AM6_DEVICES_H 36#define SOC_AM6_DEVICES_H
37 37
38#define AM6_DEV_DCC4 13 38#define AM6_DEV_MCU_ADC0 0
39#define AM6_DEV_DCC6 15 39#define AM6_DEV_MCU_ADC1 1
40#define AM6_DEV_CAL0 2
41#define AM6_DEV_CMPEVENT_INTRTR0 3
42#define AM6_DEV_MCU_CPSW0 5
43#define AM6_DEV_CPT2_AGGR0 6
44#define AM6_DEV_MCU_CPT2_AGGR0 7
45#define AM6_DEV_STM0 8
40#define AM6_DEV_DCC0 9 46#define AM6_DEV_DCC0 9
41#define AM6_DEV_MCU_DCC2 19
42#define AM6_DEV_DCC5 14
43#define AM6_DEV_MCU_DCC0 17
44#define AM6_DEV_MCU_DCC1 18
45#define AM6_DEV_DCC1 10 47#define AM6_DEV_DCC1 10
48#define AM6_DEV_DCC2 11
46#define AM6_DEV_DCC3 12 49#define AM6_DEV_DCC3 12
50#define AM6_DEV_DCC4 13
51#define AM6_DEV_DCC5 14
52#define AM6_DEV_DCC6 15
47#define AM6_DEV_DCC7 16 53#define AM6_DEV_DCC7 16
48#define AM6_DEV_DCC2 11 54#define AM6_DEV_MCU_DCC0 17
49#define AM6_DEV_MCU_I2C0 114 55#define AM6_DEV_MCU_DCC1 18
50#define AM6_DEV_I2C3 113 56#define AM6_DEV_MCU_DCC2 19
51#define AM6_DEV_I2C2 112 57#define AM6_DEV_DDRSS0 20
52#define AM6_DEV_WKUP_I2C0 115 58#define AM6_DEV_DEBUGSS_WRAP0 21
53#define AM6_DEV_I2C0 110 59#define AM6_DEV_WKUP_DMSC0 22
54#define AM6_DEV_I2C1 111 60#define AM6_DEV_TIMER0 23
61#define AM6_DEV_TIMER1 24
62#define AM6_DEV_TIMER10 25
63#define AM6_DEV_TIMER11 26
64#define AM6_DEV_TIMER2 27
65#define AM6_DEV_TIMER3 28
66#define AM6_DEV_TIMER4 29
55#define AM6_DEV_TIMER5 30 67#define AM6_DEV_TIMER5 30
56#define AM6_DEV_TIMER6 31 68#define AM6_DEV_TIMER6 31
57#define AM6_DEV_TIMER7 32 69#define AM6_DEV_TIMER7 32
58#define AM6_DEV_MCU_TIMER0 35
59#define AM6_DEV_TIMER8 33 70#define AM6_DEV_TIMER8 33
60#define AM6_DEV_TIMER2 27 71#define AM6_DEV_TIMER9 34
72#define AM6_DEV_MCU_TIMER0 35
61#define AM6_DEV_MCU_TIMER1 36 73#define AM6_DEV_MCU_TIMER1 36
62#define AM6_DEV_MCU_TIMER2 37 74#define AM6_DEV_MCU_TIMER2 37
63#define AM6_DEV_TIMER4 29
64#define AM6_DEV_TIMER3 28
65#define AM6_DEV_TIMER9 34
66#define AM6_DEV_TIMER11 26
67#define AM6_DEV_TIMER10 25
68#define AM6_DEV_TIMER0 23
69#define AM6_DEV_MCU_TIMER3 38 75#define AM6_DEV_MCU_TIMER3 38
70#define AM6_DEV_TIMER1 24 76#define AM6_DEV_ECAP0 39
71#define AM6_DEV_WKUP_PSC0 79
72#define AM6_DEV_CBASS0 82
73#define AM6_DEV_PLL_MMR0 101
74#define AM6_DEV_MCU_CPT2_AGGR0 7
75#define AM6_DEV_CPT2_AGGR0 6
76#define AM6_DEV_DEBUGSS0 68
77#define AM6_DEV_EHRPWM4 44
78#define AM6_DEV_EHRPWM1 41
79#define AM6_DEV_EHRPWM0 40 77#define AM6_DEV_EHRPWM0 40
78#define AM6_DEV_EHRPWM1 41
79#define AM6_DEV_EHRPWM2 42
80#define AM6_DEV_EHRPWM3 43 80#define AM6_DEV_EHRPWM3 43
81#define AM6_DEV_EHRPWM4 44
81#define AM6_DEV_EHRPWM5 45 82#define AM6_DEV_EHRPWM5 45
82#define AM6_DEV_EHRPWM2 42
83#define AM6_DEV_ELM0 46 83#define AM6_DEV_ELM0 46
84#define AM6_DEV_MCU_UART0 149 84#define AM6_DEV_MMCSD0 47
85#define AM6_DEV_WKUP_UART0 150
86#define AM6_DEV_UART1 147
87#define AM6_DEV_UART0 146
88#define AM6_DEV_UART2 148
89#define AM6_DEV_SA2_UL0 136
90#define AM6_DEV_CAL0 2
91#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206
92#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207
93#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208
94#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209
95#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210
96#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211
97#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212
98#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213
99#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214
100#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215
101#define AM6_DEV_PBIST0 73
102#define AM6_DEV_PBIST1 74
103#define AM6_DEV_MCU_PBIST0 75
104#define AM6_DEV_NAVSS0 118
105#define AM6_DEV_DSS0 67
106#define AM6_DEV_GPMC0 60
107#define AM6_DEV_MMCSD1 48 85#define AM6_DEV_MMCSD1 48
108#define AM6_DEV_WKUP_PLLCTRL0 77
109#define AM6_DEV_PLLCTRL0 76
110#define AM6_DEV_USB3SS1 152
111#define AM6_DEV_USB3SS0 151
112#define AM6_DEV_MCU_MCSPI0 142
113#define AM6_DEV_MCSPI2 139
114#define AM6_DEV_MCU_MCSPI2 144
115#define AM6_DEV_MCSPI0 137
116#define AM6_DEV_MCSPI1 138
117#define AM6_DEV_MCSPI4 141
118#define AM6_DEV_MCSPI3 140
119#define AM6_DEV_MCU_MCSPI1 143
120#define AM6_DEV_DEBUGSS_WRAP0 21
121#define AM6_DEV_CBASS_INFRA0 85
122#define AM6_DEV_STM0 8
123#define AM6_DEV_MCU_RTI1 135
124#define AM6_DEV_RTI0 130
125#define AM6_DEV_RTI3 133
126#define AM6_DEV_RTI1 131
127#define AM6_DEV_MCU_RTI0 134
128#define AM6_DEV_RTI2 132
129#define AM6_DEV_PSRAMECC0 128
130#define AM6_DEV_EFUSE0 69
131#define AM6_DEV_MCASP0 104
132#define AM6_DEV_MCASP1 105
133#define AM6_DEV_MCASP2 106
134#define AM6_DEV_MCU_ARMSS0 129
135#define AM6_DEV_MCU_ARMSS0_CPU0 159
136#define AM6_DEV_MCU_ARMSS0_CPU1 245
137#define AM6_DEV_CCDEBUGSS0 66
138#define AM6_DEV_WKUP_CTRL_MMR0 155
139#define AM6_DEV_MCU_CBASS_FW0 91
140#define AM6_DEV_MCU_CPSW0 5
141#define AM6_DEV_SERDES0 153
142#define AM6_DEV_SERDES1 154
143#define AM6_DEV_OLDI_TX_CORE_MAIN_0 216
144#define AM6_DEV_MCU_ADC1 1
145#define AM6_DEV_MCU_ADC0 0
146#define AM6_DEV_WKUP_DMSC0 22
147#define AM6_DEV_MCU_PLL_MMR0 108
148#define AM6_DEV_MCU_SEC_MMR0 109
149#define AM6_DEV_GIC0 56
150#define AM6_DEV_MCU_DEBUGSS0 71
151#define AM6_DEV_EQEP0 49 86#define AM6_DEV_EQEP0 49
152#define AM6_DEV_EQEP2 51
153#define AM6_DEV_EQEP1 50 87#define AM6_DEV_EQEP1 50
154#define AM6_DEV_WKUP_GPIO0 59 88#define AM6_DEV_EQEP2 51
89#define AM6_DEV_ESM0 52
90#define AM6_DEV_MCU_ESM0 53
91#define AM6_DEV_WKUP_ESM0 54
92#define AM6_DEV_GIC0 56
155#define AM6_DEV_GPIO0 57 93#define AM6_DEV_GPIO0 57
156#define AM6_DEV_GPIO1 58 94#define AM6_DEV_GPIO1 58
157#define AM6_DEV_COMPUTE_CLUSTER_MSMC0 196 95#define AM6_DEV_WKUP_GPIO0 59
158#define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197 96#define AM6_DEV_GPMC0 60
159#define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198 97#define AM6_DEV_GTC0 61
160#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199
161#define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200
162#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201
163#define AM6_DEV_COMPUTE_CLUSTER_A53_0 202
164#define AM6_DEV_COMPUTE_CLUSTER_A53_1 203
165#define AM6_DEV_COMPUTE_CLUSTER_A53_2 204
166#define AM6_DEV_COMPUTE_CLUSTER_A53_3 205
167#define AM6_DEV_WKUP_CBASS0 94
168#define AM6_DEV_MCU_ROM0 78
169#define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217
170#define AM6_DEV_ESM0 52
171#define AM6_DEV_PRU_ICSSG2 64
172#define AM6_DEV_PRU_ICSSG0 62 98#define AM6_DEV_PRU_ICSSG0 62
173#define AM6_DEV_PRU_ICSSG1 63 99#define AM6_DEV_PRU_ICSSG1 63
174#define AM6_DEV_MCU_ESM0 53 100#define AM6_DEV_PRU_ICSSG2 64
175#define AM6_DEV_ECAP0 39 101#define AM6_DEV_GPU0 65
176#define AM6_DEV_WKUP_ESM0 54 102#define AM6_DEV_CCDEBUGSS0 66
177#define AM6_DEV_MCU_EFUSE0 72 103#define AM6_DEV_DSS0 67
178#define AM6_DEV_MCU_CTRL_MMR0 107 104#define AM6_DEV_DEBUGSS0 68
105#define AM6_DEV_EFUSE0 69
179#define AM6_DEV_PSC0 70 106#define AM6_DEV_PSC0 70
107#define AM6_DEV_MCU_DEBUGSS0 71
108#define AM6_DEV_MCU_EFUSE0 72
109#define AM6_DEV_PBIST0 73
110#define AM6_DEV_PBIST1 74
111#define AM6_DEV_MCU_PBIST0 75
112#define AM6_DEV_PLLCTRL0 76
113#define AM6_DEV_WKUP_PLLCTRL0 77
114#define AM6_DEV_MCU_ROM0 78
115#define AM6_DEV_WKUP_PSC0 79
116#define AM6_DEV_WKUP_VTM0 80
117#define AM6_DEV_DEBUGSUSPENDRTR0 81
118#define AM6_DEV_CBASS0 82
119#define AM6_DEV_CBASS_DEBUG0 83
120#define AM6_DEV_CBASS_FW0 84
121#define AM6_DEV_CBASS_INFRA0 85
122#define AM6_DEV_ECC_AGGR0 86
123#define AM6_DEV_ECC_AGGR1 87
124#define AM6_DEV_ECC_AGGR2 88
125#define AM6_DEV_MCU_CBASS0 89
126#define AM6_DEV_MCU_CBASS_DEBUG0 90
127#define AM6_DEV_MCU_CBASS_FW0 91
128#define AM6_DEV_MCU_ECC_AGGR0 92
129#define AM6_DEV_MCU_ECC_AGGR1 93
130#define AM6_DEV_WKUP_CBASS0 94
131#define AM6_DEV_WKUP_ECC_AGGR0 95
132#define AM6_DEV_WKUP_CBASS_FW0 96
133#define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97
134#define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98
180#define AM6_DEV_CTRL_MMR0 99 135#define AM6_DEV_CTRL_MMR0 99
136#define AM6_DEV_GPIOMUX_INTRTR0 100
137#define AM6_DEV_PLL_MMR0 101
181#define AM6_DEV_MCU_MCAN0 102 138#define AM6_DEV_MCU_MCAN0 102
182#define AM6_DEV_MCU_MCAN1 103 139#define AM6_DEV_MCU_MCAN1 103
183#define AM6_DEV_DDRSS0 20 140#define AM6_DEV_MCASP0 104
184#define AM6_DEV_MCU_NAVSS0 119 141#define AM6_DEV_MCASP1 105
185#define AM6_DEV_MCU_FSS0 55 142#define AM6_DEV_MCASP2 106
143#define AM6_DEV_MCU_CTRL_MMR0 107
144#define AM6_DEV_MCU_PLL_MMR0 108
145#define AM6_DEV_MCU_SEC_MMR0 109
146#define AM6_DEV_I2C0 110
147#define AM6_DEV_I2C1 111
148#define AM6_DEV_I2C2 112
149#define AM6_DEV_I2C3 113
150#define AM6_DEV_MCU_I2C0 114
151#define AM6_DEV_WKUP_I2C0 115
152#define AM6_DEV_MCU_MSRAM0 116
186#define AM6_DEV_DFTSS0 117 153#define AM6_DEV_DFTSS0 117
187#define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156 154#define AM6_DEV_NAVSS0 118
188#define AM6_DEV_GPIOMUX_INTRTR0 100 155#define AM6_DEV_MCU_NAVSS0 119
189#define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97 156#define AM6_DEV_PCIE0 120
190#define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98 157#define AM6_DEV_PCIE1 121
191#define AM6_DEV_ICEMELTER_WKUP_0 218
192#define AM6_DEV_GPU0 65
193#define AM6_DEV_PDMA_DEBUG0 122 158#define AM6_DEV_PDMA_DEBUG0 122
194#define AM6_DEV_PDMA0 123 159#define AM6_DEV_PDMA0 123
195#define AM6_DEV_PDMA1 124 160#define AM6_DEV_PDMA1 124
196#define AM6_DEV_MCU_PDMA0 125 161#define AM6_DEV_MCU_PDMA0 125
197#define AM6_DEV_MCU_PDMA1 126 162#define AM6_DEV_MCU_PDMA1 126
198#define AM6_DEV_MCU_MSRAM0 116
199#define AM6_DEV_CMPEVENT_INTRTR0 3
200#define AM6_DEV_DEBUGSUSPENDRTR0 81
201#define AM6_DEV_TIMESYNC_INTRTR0 145
202#define AM6_DEV_CBASS_DEBUG0 83
203#define AM6_DEV_CBASS_FW0 84
204#define AM6_DEV_MCU_CBASS_DEBUG0 90
205#define AM6_DEV_WKUP_CBASS_FW0 96
206#define AM6_DEV_PCIE0 120
207#define AM6_DEV_PCIE1 121
208#define AM6_DEV_GTC0 61
209#define AM6_DEV_K3_LED_MAIN_0 219
210#define AM6_DEV_WKUP_VTM0 80
211#define AM6_DEV_MMCSD0 47
212#define AM6_DEV_MCU_ECC_AGGR0 92
213#define AM6_DEV_ECC_AGGR1 87
214#define AM6_DEV_ECC_AGGR2 88
215#define AM6_DEV_MCU_ECC_AGGR1 93
216#define AM6_DEV_WKUP_ECC_AGGR0 95
217#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220
218#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221
219#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222
220#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223
221#define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224
222#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225
223#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226
224#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227
225#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228
226#define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229
227#define AM6_DEV_ECC_AGGR0 86
228#define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230
229#define AM6_DEV_MCU_PSRAM0 127 163#define AM6_DEV_MCU_PSRAM0 127
230#define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231 164#define AM6_DEV_PSRAMECC0 128
231#define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232 165#define AM6_DEV_MCU_ARMSS0 129
232#define AM6_DEV_MCU_CBASS0 89 166#define AM6_DEV_RTI0 130
233#define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233 167#define AM6_DEV_RTI1 131
234#define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234 168#define AM6_DEV_RTI2 132
235#define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235 169#define AM6_DEV_RTI3 133
236#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU 236 170#define AM6_DEV_MCU_RTI0 134
237#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA 237 171#define AM6_DEV_MCU_RTI1 135
238#define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC 238 172#define AM6_DEV_SA2_UL0 136
239#define AM6_DEV_DUMMY_IP_LPSC_DMSC 239 173#define AM6_DEV_MCSPI0 137
240#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA 240 174#define AM6_DEV_MCSPI1 138
241#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN 241 175#define AM6_DEV_MCSPI2 139
242#define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP 242 176#define AM6_DEV_MCSPI3 140
243#define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU 243 177#define AM6_DEV_MCSPI4 141
244#define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA 244 178#define AM6_DEV_MCU_MCSPI0 142
179#define AM6_DEV_MCU_MCSPI1 143
180#define AM6_DEV_MCU_MCSPI2 144
181#define AM6_DEV_TIMESYNC_INTRTR0 145
182#define AM6_DEV_UART0 146
183#define AM6_DEV_UART1 147
184#define AM6_DEV_UART2 148
185#define AM6_DEV_MCU_UART0 149
186#define AM6_DEV_WKUP_UART0 150
187#define AM6_DEV_USB3SS0 151
188#define AM6_DEV_USB3SS1 152
189#define AM6_DEV_SERDES0 153
190#define AM6_DEV_SERDES1 154
191#define AM6_DEV_WKUP_CTRL_MMR0 155
192#define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156
245#define AM6_DEV_BOARD0 157 193#define AM6_DEV_BOARD0 157
194#define AM6_DEV_MCU_ARMSS0_CPU0 159
246#define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161 195#define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161
247#define AM6_DEV_WKUP_DMSC0_INTR_AGGR_0 162
248#define AM6_DEV_NAVSS0_CPTS0 163 196#define AM6_DEV_NAVSS0_CPTS0 163
249#define AM6_DEV_NAVSS0_INTR_ROUTER_0 182
250#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164 197#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164
251#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165 198#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165
252#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166 199#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166
@@ -260,23 +207,76 @@
260#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174 207#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174
261#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175 208#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175
262#define AM6_DEV_NAVSS0_MCRC0 176 209#define AM6_DEV_NAVSS0_MCRC0 176
263#define AM6_DEV_NAVSS0_MODSS_INTA0 180
264#define AM6_DEV_NAVSS0_MODSS_INTA1 181
265#define AM6_DEV_NAVSS0_PROXY0 185
266#define AM6_DEV_NAVSS0_PVU0 177 210#define AM6_DEV_NAVSS0_PVU0 177
267#define AM6_DEV_NAVSS0_PVU1 178 211#define AM6_DEV_NAVSS0_PVU1 178
268#define AM6_DEV_NAVSS0_RINGACC0 187 212#define AM6_DEV_NAVSS0_UDMASS_INTA0 179
269#define AM6_DEV_NAVSS0_SEC_PROXY0 186 213#define AM6_DEV_NAVSS0_MODSS_INTA0 180
214#define AM6_DEV_NAVSS0_MODSS_INTA1 181
215#define AM6_DEV_NAVSS0_INTR_ROUTER_0 182
270#define AM6_DEV_NAVSS0_TIMER_MGR0 183 216#define AM6_DEV_NAVSS0_TIMER_MGR0 183
271#define AM6_DEV_NAVSS0_TIMER_MGR1 184 217#define AM6_DEV_NAVSS0_TIMER_MGR1 184
218#define AM6_DEV_NAVSS0_PROXY0 185
219#define AM6_DEV_NAVSS0_RINGACC0 187
272#define AM6_DEV_NAVSS0_UDMAP0 188 220#define AM6_DEV_NAVSS0_UDMAP0 188
273#define AM6_DEV_NAVSS0_UDMASS_INTA0 179
274#define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189 221#define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189
275#define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190 222#define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190
276#define AM6_DEV_MCU_NAVSS0_MCRC0 193
277#define AM6_DEV_MCU_NAVSS0_PROXY0 191 223#define AM6_DEV_MCU_NAVSS0_PROXY0 191
278#define AM6_DEV_MCU_NAVSS0_RINGACC0 195 224#define AM6_DEV_MCU_NAVSS0_MCRC0 193
279#define AM6_DEV_MCU_NAVSS0_SEC_PROXY0 192
280#define AM6_DEV_MCU_NAVSS0_UDMAP0 194 225#define AM6_DEV_MCU_NAVSS0_UDMAP0 194
226#define AM6_DEV_MCU_NAVSS0_RINGACC0 195
227#define AM6_DEV_COMPUTE_CLUSTER_MSMC0 196
228#define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197
229#define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198
230#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199
231#define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200
232#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201
233#define AM6_DEV_COMPUTE_CLUSTER_A53_0 202
234#define AM6_DEV_COMPUTE_CLUSTER_A53_1 203
235#define AM6_DEV_COMPUTE_CLUSTER_A53_2 204
236#define AM6_DEV_COMPUTE_CLUSTER_A53_3 205
237#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206
238#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207
239#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208
240#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209
241#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210
242#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211
243#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212
244#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213
245#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214
246#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215
247#define AM6_DEV_OLDI_TX_CORE_MAIN_0 216
248#define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217
249#define AM6_DEV_ICEMELTER_WKUP_0 218
250#define AM6_DEV_K3_LED_MAIN_0 219
251#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220
252#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221
253#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222
254#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223
255#define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224
256#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225
257#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226
258#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227
259#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228
260#define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229
261#define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230
262#define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231
263#define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232
264#define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233
265#define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234
266#define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235
267#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD 236
268#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD 237
269#define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD 238
270#define AM6_DEV_DUMMY_IP_LPSC_DMSC_VD 239
271#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD 240
272#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD 241
273#define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD 242
274#define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD 243
275#define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD 244
276#define AM6_DEV_MCU_ARMSS0_CPU1 245
277#define AM6_DEV_MCU_FSS0_FSAS_0 246
278#define AM6_DEV_MCU_FSS0_HYPERBUS0 247
279#define AM6_DEV_MCU_FSS0_OSPI_0 248
280#define AM6_DEV_MCU_FSS0_OSPI_1 249
281 281
282#endif /* SOC_AM6_DEVICES_H */ 282#endif /* SOC_AM6_DEVICES_H */
diff --git a/include/soc/am65x/resasg_types.h b/include/soc/am65x/resasg_types.h
index 3b42b35ed..686560f7a 100644
--- a/include/soc/am65x/resasg_types.h
+++ b/include/soc/am65x/resasg_types.h
@@ -60,259 +60,59 @@
60 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \ 60 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
61 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK)) 61 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
62 62
63/** Main domain Navigator Subsystem UDMASS IA0 */ 63/**
64#define RESASG_TYPE_MAIN_NAV_UDMASS_IA0 (0x000U) 64 * IA subtypes definitions
65/** Main domain Navigator Subsystem MODSS IA0 */ 65 */
66#define RESASG_TYPE_MAIN_NAV_MODSS_IA0 (0x001U) 66#define RESASG_SUBTYPE_IA_VINT (0x000AU)
67/** Main domain Navigator Subsystem MODSS IA1 */ 67#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
68#define RESASG_TYPE_MAIN_NAV_MODSS_IA1 (0x002U) 68#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
69/** MCU domain Navigator Subsystem UDMASS IA0 */ 69#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
70#define RESASG_TYPE_MCU_NAV_UDMASS_IA0 (0x003U) 70#define RESASG_SUBTYPES_IA_CNT (0x0004U)
71/** Main domain Navigator Subsystem MCRC */
72#define RESASG_TYPE_MAIN_NAV_MCRC (0x004U)
73/** MCU domain Navigator Subsystem MCRC */
74#define RESASG_TYPE_MCU_NAV_MCRC (0x005U)
75/** Main domain Navigator Subsystem UDMAP */
76#define RESASG_TYPE_MAIN_NAV_UDMAP (0x006U)
77/** MCU domain Navigator Subsystem UDMAP */
78#define RESASG_TYPE_MCU_NAV_UDMAP (0x007U)
79/** MSMC */
80#define RESASG_TYPE_MSMC (0x008U)
81/** Main domain Navigator Subsystem Ring Accelerator */
82#define RESASG_TYPE_MAIN_NAV_RA (0x009U)
83/** MCU domain Navigator Subsystem Ring Accelerator */
84#define RESASG_TYPE_MCU_NAV_RA (0x00AU)
85/** A53 GIC IRQ (input interrupts) */
86#define RESASG_TYPE_GIC_IRQ (0x00BU)
87/** Pulsar core 0 IRQ (input interrupts) */
88#define RESASG_TYPE_PULSAR_C0_IRQ (0x00CU)
89/** Pulsar core 1 IRQ (input interrupts) */
90#define RESASG_TYPE_PULSAR_C1_IRQ (0x00DU)
91/** ICSSG 0 IRQ (input interrupts) */
92#define RESASG_TYPE_ICSSG0_IRQ (0x00EU)
93/** ICSSG 1 IRQ (input interrupts) */
94#define RESASG_TYPE_ICSSG1_IRQ (0x00FU)
95/** ICSSG 2 IRQ (input interrupts) */
96#define RESASG_TYPE_ICSSG2_IRQ (0x010U)
97/** Main domain Navigator Subsystem proxy */
98#define RESASG_TYPE_MAIN_NAV_PROXY (0x011U)
99/** MCU domain Navigator Subsystem proxy */
100#define RESASG_TYPE_MCU_NAV_PROXY (0x012U)
101/** Maximum RESASG_TYPE value. DO NOT create types with a value
102 * greater than this */
103#define RESASG_TYPE_MAX (0x3FFU)
104
105/** Main Nav UDMASS IA0 virtual interrupts */
106#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT (0x00U)
107/** Main Nav UDMASS IA0 source events (SEVI) */
108#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI (0x01U)
109/** Main Nav UDMASS IA0 multicast events (MEVI) */
110#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI (0x02U)
111/** Main Nav UDMASS IA0 global counter events (GEVI) */
112#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI (0x03U)
113/** Main Nav Total UDMASS IA0 subtypes. Update when subtypes added */
114#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT (0x04U)
115
116/** Main Nav MODSS IA0 virtual interrupts */
117#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT (0x00U)
118/** Main Nav MODSS IA0 single events (SEVI) */
119#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI (0x01U)
120/** Total Main Nav MODSS IA0 subtypes. Update when subtypes added */
121#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT (0x02U)
122
123/** Main Nav MODSS IA1 virtual interrupts */
124#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT (0x00U)
125/** Main Nav MODSS IA1 single events (SEVI) */
126#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI (0x01U)
127/** Total Main Nav MODSS IA1 subtypes. Update when subtypes added */
128#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT (0x02U)
129
130/** MCU Nav UDMASS IA0 virtual interrupts */
131#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT (0x00U)
132/** MCU Nav UDMASS IA0 single events (SEVI) */
133#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI (0x01U)
134/** MCU Nav UDMASS IA0 multicast events (MEVI) */
135#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI (0x02U)
136/** MCU Nav UDMASS IA0 global counter events (GEVI) */
137#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI (0x03U)
138/** Total MCU Nav UDMASS IA0 subtypes. Update when subtypes added */
139#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT (0x04U)
140
141/** Main Nav MCRC local events (LEVI) */
142#define RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI (0x00U)
143/** Total Main Nav MCRC subtypes. Update when subtypes added */
144#define RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT (0x01U)
145
146/** MCU Nav MCRC local events (LEVI) */
147#define RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI (0x00U)
148/** Total MCU Nav MCRC subtypes. Update when subtypes are added */
149#define RESASG_SUBTYPE_MCU_NAV_MCRC_CNT (0x01U)
150
151/** Main Nav UDMAP trigger events */
152#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER (0x00U)
153/** Nav UDMAP driver high capacity transmit channels */
154#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN (0x01U)
155/** Main Nav UDMAP driver standard transmit channels */
156#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN (0x02U)
157/** Main Nav UDMAP driver external transmit channels */
158#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN (0x03U)
159/** Main Nav UDMAP driver high capacity receive channels */
160#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN (0x04U)
161/** Main Nav UDMAP driver standard receive channels */
162#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN (0x05U)
163/** Main Nav UDMAP driver common receive flows used by receive channel
164 * RCHAN_RFLOW_RNG parameters */
165#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON (0x06U)
166/** Main Nav UDMAP driver global config invalid flow OES register */
167#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES (0x07U)
168/** Main Nav UDMAP driver global config register region rd/wr access */
169#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG (0x08U)
170/** Total Main Nav UDMAP subtypes. Update when subtypes added */
171#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT (0x09U)
172
173/** MCU Nav UDMAP trigger events */
174#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER (0x00U)
175/** MCU Nav UDMAP driver high capacity transmit channels */
176#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN (0x01U)
177/** MCU Nav UDMAP driver standard transmit channels */
178#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN (0x02U)
179/** MCU Nav UDMAP driver high capacity receive channels */
180#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN (0x03U)
181/** MCU Nav UDMAP driver standard receive channels */
182#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN (0x04U)
183/** MCU Nav UDMAP driver common receive flows used by receive channel
184 * RCHAN_RFLOW_RNG parameters */
185#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON (0x05U)
186/** MCU Nav UDMAP driver global config invalid flow OES register */
187#define RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES (0x06U)
188/** MCU Nav UDMAP driver global config register region rd/wr access */
189#define RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG (0x07U)
190/** Total MCU Nav UDMAP subtypes. Update when subtypes added */
191#define RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT (0x08U)
192
193/** MSMC DRU events */
194#define RESASG_SUBTYPE_MSMC_DRU (0x00U)
195/** Total MSMC subtypes. Update when subtypes added */
196#define RESASG_SUBTYPE_MSMC_CNT (0x01U)
197
198/** Main Nav RA driver UDMAP tx rings */
199#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX (0x00U)
200/** Main Nav RA driver UDMAP rx rings */
201#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX (0x01U)
202/** Main Nav RA driver general purpose rings */
203#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP (0x02U)
204/** Main Nav RA driver global config error OES register */
205#define RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES (0x03U)
206/** Main Nav RA driver ring virtids */
207#define RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID (0x04U)
208/** Main Nav RA driver ring monitors */
209#define RESASG_SUBTYPE_MAIN_NAV_RA_MONITOR (0x05U)
210/** Total Main Nav RA subtypes. Update when subtypes are added */
211#define RESASG_SUBTYPE_MAIN_NAV_RA_CNT (0x06U)
212
213/** Main Nav proxy driver proxies */
214#define RESASG_SUBTYPE_MAIN_NAV_PROXY_PROXIES (0x00U)
215/** Total Main Nav proxy subtypes. Update when subtypes are added */
216#define RESASG_SUBTYPE_MAIN_NAV_PROXY_CNT (0x01U)
217
218/** MCU Nav RA driver UDMAP tx rings */
219#define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX (0x00U)
220/** MCU Nav RA driver UDMAP rx rings */
221#define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX (0x01U)
222/** MCU Nav RA driver general purpose rings */
223#define RESASG_SUBTYPE_MCU_NAV_RA_RING_GP (0x02U)
224/** MCU Nav RA driver global config error OES register */
225#define RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES (0x03U)
226/** MCU Nav RA driver ring virtids */
227#define RESASG_SUBTYPE_MCU_NAV_RA_VIRTID (0x04U)
228/** MCU Nav RA driver ring monitors */
229#define RESASG_SUBTYPE_MCU_NAV_RA_MONITOR (0x05U)
230/** Total MCU Nav RA subtypes. Update when subtypes added */
231#define RESASG_SUBTYPE_MCU_NAV_RA_CNT (0x06U)
232
233/** GIC IRQ inputs (64 - 127) from Main Nav */
234#define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 (0x00U)
235/** GIC IRQ inputs (392 - 423) from Main GPIO IR */
236#define RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO (0x01U)
237/** GIC IRQ inputs (448 - 503) from Main Nav */
238#define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 (0x02U)
239/** GIC IRQ inputs (544 - 559) from Compare event IR */
240#define RESASG_SUBTYPE_GIC_IRQ_COMP_EVT (0x03U)
241/** GIC IRQ inputs (712 - 727) from Wakeup GPIO IR */
242#define RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO (0x04U)
243/** Total GIC IRQ subtypes. Update when subtypes added */
244#define RESASG_SUBTYPE_GIC_IRQ_CNT (0x05U)
245
246/** Pulsar core 0 VIM IRQ inputs (64 - 95) from MCU Nav */
247#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV (0x00U)
248/** Pulsar core 0 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */
249#define RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO (0x01U)
250/** Pulsar core 0 VIM IRQ inputs (160 - 223) from Main2MCU level IR */
251#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL (0x02U)
252/** Pulsar core 0 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */
253#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS (0x03U)
254/** Total Pulsar core 0 IRQ subtypes. Update when subtypes added */
255#define RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT (0x04U)
256 71
257/** Pulsar core 1 VIM IRQ inputs (64 - 95) from MCU Nav */ 72/**
258#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV (0x00U) 73 * IR subtypes definitions
259/** Pulsar core 1 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */ 74 */
260#define RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO (0x01U) 75#define RESASG_SUBTYPE_IR_OUTPUT (0x0000U)
261/** Pulsar core 1 VIM IRQ inputs (160 - 223) from Main2MCU level IR */ 76#define RESASG_SUBTYPES_IR_CNT (0x0001U)
262#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL (0x02U)
263/** Pulsar core 1 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */
264#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS (0x03U)
265/** Total Pulsar core 1 IRQ subtypes. Update when subtypes added */
266#define RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT (0x04U)
267 77
268/** ICSSG0 IRQ inputs (110 - 117) from Main Nav */ 78/**
269#define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV (0x00U) 79 * Proxy subtypes definitions
270/** ICSSG0 IRQ inputs (152 - 159) from Main GPIO IR */ 80 */
271#define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO (0x01U) 81#define RESASG_SUBTYPE_PROXY_PROXIES (0x0000U)
272/** Total ICSSG 0 IRQ subtypes. Update when subtypes added */ 82#define RESASG_SUBTYPES_PROXY_CNT (0x0001U)
273#define RESASG_SUBTYPE_ICSSG0_IRQ_CNT (0x02U)
274 83
275/** ICSSG1 IRQ inputs (110 - 117) from Main Nav */ 84/**
276#define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV (0x00U) 85 * RA subtypes definitions
277/** ICSSG1 IRQ inputs (152 - 159) from Main GPIO IR */ 86 */
278#define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO (0x01U) 87#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
279/** Total ICSSG1 IRQ subtypes. Update when subtypes added */ 88#define RESASG_SUBTYPE_RA_GP (0x0001U)
280#define RESASG_SUBTYPE_ICSSG1_IRQ_CNT (0x02U) 89#define RESASG_SUBTYPE_RA_UDMAP_RX (0x0002U)
90#define RESASG_SUBTYPE_RA_UDMAP_TX (0x0003U)
91#define RESASG_SUBTYPE_RA_UDMAP_TX_EXT (0x0004U)
92#define RESASG_SUBTYPE_RA_UDMAP_RX_H (0x0005U)
93#define RESASG_SUBTYPE_RA_UDMAP_TX_H (0x0007U)
94#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
95#define RESASG_SUBTYPE_RA_MONITORS (0x000BU)
96#define RESASG_SUBTYPES_RA_CNT (0x0009U)
281 97
282/** ICSSG2 IRQ inputs (110 - 117) from Main Nav */ 98/**
283#define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV (0x00U) 99 * UDMAP subtypes definitions
284/** ICSSG2 IRQ inputs (152 - 159) from Main GPIO IR */ 100 */
285#define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO (0x01U) 101#define RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON (0x0000U)
286/** Total ICSSG2 IRQ subtypes. Update when subtypes added */ 102#define RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES (0x0001U)
287#define RESASG_SUBTYPE_ICSSG2_IRQ_CNT (0x02U) 103#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
104#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
105#define RESASG_SUBTYPE_UDMAP_RX_CHAN (0x000AU)
106#define RESASG_SUBTYPE_UDMAP_RX_HCHAN (0x000BU)
107#define RESASG_SUBTYPE_UDMAP_TX_CHAN (0x000DU)
108#define RESASG_SUBTYPE_UDMAP_TX_ECHAN (0x000EU)
109#define RESASG_SUBTYPE_UDMAP_TX_HCHAN (0x000FU)
110#define RESASG_SUBTYPES_UDMAP_CNT (0x0009U)
288 111
289/** MCU Nav proxy driver proxies */
290#define RESASG_SUBTYPE_MCU_NAV_PROXY_PROXIES (0x00U)
291/** Total MCU Nav proxy subtypes. Update when subtypes are added */
292#define RESASG_SUBTYPE_MCU_NAV_PROXY_CNT (0x01U)
293 112
294/** 113/**
295 * Total number of unique resource types for AM6 114 * Total number of unique resource types for SoC
296 */ 115 */
297#define RESASG_UTYPE_CNT \ 116#define RESASG_UTYPE_CNT 52U
298 (RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT + \
299 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT + \
300 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT + \
301 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT + \
302 RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT + \
303 RESASG_SUBTYPE_MCU_NAV_MCRC_CNT + \
304 RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT + \
305 RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT + \
306 RESASG_SUBTYPE_MSMC_CNT + \
307 RESASG_SUBTYPE_MAIN_NAV_RA_CNT + \
308 RESASG_SUBTYPE_MCU_NAV_RA_CNT + \
309 RESASG_SUBTYPE_MAIN_NAV_PROXY_CNT + \
310 RESASG_SUBTYPE_MCU_NAV_PROXY_CNT + \
311 RESASG_SUBTYPE_GIC_IRQ_CNT + \
312 RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT + \
313 RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT + \
314 RESASG_SUBTYPE_ICSSG0_IRQ_CNT + \
315 RESASG_SUBTYPE_ICSSG1_IRQ_CNT + \
316 RESASG_SUBTYPE_ICSSG2_IRQ_CNT)
317 117
318#endif /* RESASG_TYPES_H */ 118#endif /* RESASG_TYPES_H */