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authorAndreas Dannenberg2019-06-05 14:58:09 -0500
committerAndreas Dannenberg2019-06-10 11:42:05 -0500
commitf14250ffca824ac274b20d3431b60ed920c218ec (patch)
tree77bd66a5a000c4387b46fb40ff1e89fada481ac0 /include
parent5671047ceeac760212e44d9338d5863b0e4ce7d0 (diff)
downloadk3-image-gen-f14250ffca824ac274b20d3431b60ed920c218ec.tar.gz
k3-image-gen-f14250ffca824ac274b20d3431b60ed920c218ec.tar.xz
k3-image-gen-f14250ffca824ac274b20d3431b60ed920c218ec.zip
include: Add J721E specific headers corresponding to SYSFW
Introduce initial J721E specific headers Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/soc/j721e/devices.h337
-rw-r--r--include/soc/j721e/hosts.h101
-rw-r--r--include/soc/j721e/resasg_types.h206
3 files changed, 644 insertions, 0 deletions
diff --git a/include/soc/j721e/devices.h b/include/soc/j721e/devices.h
new file mode 100644
index 000000000..2d0458a79
--- /dev/null
+++ b/include/soc/j721e/devices.h
@@ -0,0 +1,337 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SOC_J721E_DEVICES_H
36#define SOC_J721E_DEVICES_H
37
38#define J721E_DEV_MCU_ADC0 0
39#define J721E_DEV_MCU_ADC1 1
40#define J721E_DEV_ATL0 2
41#define J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0 3
42#define J721E_DEV_A72SS0 4
43#define J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP 5
44#define J721E_DEV_COMPUTE_CLUSTER0_CLEC 6
45#define J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE 7
46#define J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW 8
47#define J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP 9
48#define J721E_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0 10
49#define J721E_DEV_COMPUTE_CLUSTER0_DIVP_TFT0 11
50#define J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP 12
51#define J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN 13
52#define J721E_DEV_COMPUTE_CLUSTER0_GIC500SS 14
53#define J721E_DEV_C71SS0 15
54#define J721E_DEV_C71SS0_MMA 16
55#define J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP 17
56#define J721E_DEV_MCU_CPSW0 18
57#define J721E_DEV_CPSW0 19
58#define J721E_DEV_CPT2_AGGR0 20
59#define J721E_DEV_CPT2_AGGR1 21
60#define J721E_DEV_DMSC_WKUP_0 22
61#define J721E_DEV_CPT2_AGGR2 23
62#define J721E_DEV_MCU_CPT2_AGGR0 24
63#define J721E_DEV_CSI_PSILSS0 25
64#define J721E_DEV_CSI_RX_IF0 26
65#define J721E_DEV_CSI_RX_IF1 27
66#define J721E_DEV_CSI_TX_IF0 28
67#define J721E_DEV_STM0 29
68#define J721E_DEV_DCC0 30
69#define J721E_DEV_DCC1 31
70#define J721E_DEV_DCC2 32
71#define J721E_DEV_DCC3 33
72#define J721E_DEV_DCC4 34
73#define J721E_DEV_MCU_TIMER0 35
74#define J721E_DEV_DCC5 36
75#define J721E_DEV_DCC6 37
76#define J721E_DEV_DCC7 38
77#define J721E_DEV_DCC8 39
78#define J721E_DEV_DCC9 40
79#define J721E_DEV_DCC10 41
80#define J721E_DEV_DCC11 42
81#define J721E_DEV_DCC12 43
82#define J721E_DEV_MCU_DCC0 44
83#define J721E_DEV_MCU_DCC1 45
84#define J721E_DEV_MCU_DCC2 46
85#define J721E_DEV_DDR0 47
86#define J721E_DEV_DMPAC_TOP_MAIN_0 48
87#define J721E_DEV_TIMER0 49
88#define J721E_DEV_TIMER1 50
89#define J721E_DEV_TIMER2 51
90#define J721E_DEV_TIMER3 52
91#define J721E_DEV_TIMER4 53
92#define J721E_DEV_TIMER5 54
93#define J721E_DEV_TIMER6 55
94#define J721E_DEV_TIMER7 57
95#define J721E_DEV_TIMER8 58
96#define J721E_DEV_TIMER9 59
97#define J721E_DEV_TIMER10 60
98#define J721E_DEV_GTC0 61
99#define J721E_DEV_TIMER11 62
100#define J721E_DEV_TIMER12 63
101#define J721E_DEV_TIMER13 64
102#define J721E_DEV_TIMER14 65
103#define J721E_DEV_TIMER15 66
104#define J721E_DEV_TIMER16 67
105#define J721E_DEV_TIMER17 68
106#define J721E_DEV_TIMER18 69
107#define J721E_DEV_TIMER19 70
108#define J721E_DEV_MCU_TIMER1 71
109#define J721E_DEV_MCU_TIMER2 72
110#define J721E_DEV_MCU_TIMER3 73
111#define J721E_DEV_MCU_TIMER4 74
112#define J721E_DEV_MCU_TIMER5 75
113#define J721E_DEV_MCU_TIMER6 76
114#define J721E_DEV_MCU_TIMER7 77
115#define J721E_DEV_MCU_TIMER8 78
116#define J721E_DEV_MCU_TIMER9 79
117#define J721E_DEV_ECAP0 80
118#define J721E_DEV_ECAP1 81
119#define J721E_DEV_ECAP2 82
120#define J721E_DEV_EHRPWM0 83
121#define J721E_DEV_EHRPWM1 84
122#define J721E_DEV_EHRPWM2 85
123#define J721E_DEV_EHRPWM3 86
124#define J721E_DEV_EHRPWM4 87
125#define J721E_DEV_EHRPWM5 88
126#define J721E_DEV_ELM0 89
127#define J721E_DEV_EMIF_DATA_0_VD 90
128#define J721E_DEV_MMCSD0 91
129#define J721E_DEV_MMCSD1 92
130#define J721E_DEV_MMCSD2 93
131#define J721E_DEV_EQEP0 94
132#define J721E_DEV_EQEP1 95
133#define J721E_DEV_EQEP2 96
134#define J721E_DEV_ESM0 97
135#define J721E_DEV_MCU_ESM0 98
136#define J721E_DEV_WKUP_ESM0 99
137#define J721E_DEV_FSS_MCU_0 100
138#define J721E_DEV_MCU_FSS0_FSAS_0 101
139#define J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 102
140#define J721E_DEV_MCU_FSS0_OSPI_0 103
141#define J721E_DEV_MCU_FSS0_OSPI_1 104
142#define J721E_DEV_GPIO0 105
143#define J721E_DEV_GPIO1 106
144#define J721E_DEV_GPIO2 107
145#define J721E_DEV_GPIO3 108
146#define J721E_DEV_GPIO4 109
147#define J721E_DEV_GPIO5 110
148#define J721E_DEV_GPIO6 111
149#define J721E_DEV_GPIO7 112
150#define J721E_DEV_WKUP_GPIO0 113
151#define J721E_DEV_WKUP_GPIO1 114
152#define J721E_DEV_GPMC0 115
153#define J721E_DEV_I3C0 116
154#define J721E_DEV_MCU_I3C0 117
155#define J721E_DEV_MCU_I3C1 118
156#define J721E_DEV_PRU_ICSSG0 119
157#define J721E_DEV_PRU_ICSSG1 120
158#define J721E_DEV_C66SS0_INTROUTER0 121
159#define J721E_DEV_C66SS1_INTROUTER0 122
160#define J721E_DEV_CMPEVENT_INTRTR0 123
161#define J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0 124
162#define J721E_DEV_GPU0_GPU_0 125
163#define J721E_DEV_GPU0_GPUCORE_0 126
164#define J721E_DEV_LED0 127
165#define J721E_DEV_MAIN2MCU_LVL_INTRTR0 128
166#define J721E_DEV_MAIN2MCU_PLS_INTRTR0 130
167#define J721E_DEV_GPIOMUX_INTRTR0 131
168#define J721E_DEV_WKUP_PORZ_SYNC0 132
169#define J721E_DEV_PSC0 133
170#define J721E_DEV_R5FSS0_INTROUTER0 134
171#define J721E_DEV_R5FSS1_INTROUTER0 135
172#define J721E_DEV_TIMESYNC_INTRTR0 136
173#define J721E_DEV_WKUP_GPIOMUX_INTRTR0 137
174#define J721E_DEV_WKUP_PSC0 138
175#define J721E_DEV_AASRC0 139
176#define J721E_DEV_K3_C66_COREPAC_MAIN_0 140
177#define J721E_DEV_K3_C66_COREPAC_MAIN_1 141
178#define J721E_DEV_C66SS0_CORE0 142
179#define J721E_DEV_C66SS1_CORE0 143
180#define J721E_DEV_DECODER0 144
181#define J721E_DEV_WKUP_DDPA0 145
182#define J721E_DEV_UART0 146
183#define J721E_DEV_DPHY_RX0 147
184#define J721E_DEV_DPHY_RX1 148
185#define J721E_DEV_MCU_UART0 149
186#define J721E_DEV_DSS_DSI0 150
187#define J721E_DEV_DSS_EDP0 151
188#define J721E_DEV_DSS0 152
189#define J721E_DEV_ENCODER0 153
190#define J721E_DEV_WKUP_VTM0 154
191#define J721E_DEV_MAIN2WKUPMCU_VD 155
192#define J721E_DEV_MCAN0 156
193#define J721E_DEV_BOARD0 157
194#define J721E_DEV_MCAN1 158
195#define J721E_DEV_MCAN2 160
196#define J721E_DEV_MCAN3 161
197#define J721E_DEV_MCAN4 162
198#define J721E_DEV_MCAN5 163
199#define J721E_DEV_MCAN6 164
200#define J721E_DEV_MCAN7 165
201#define J721E_DEV_MCAN8 166
202#define J721E_DEV_MCAN9 167
203#define J721E_DEV_MCAN10 168
204#define J721E_DEV_MCAN11 169
205#define J721E_DEV_MCAN12 170
206#define J721E_DEV_MCAN13 171
207#define J721E_DEV_MCU_MCAN0 172
208#define J721E_DEV_MCU_MCAN1 173
209#define J721E_DEV_MCASP0 174
210#define J721E_DEV_MCASP1 175
211#define J721E_DEV_MCASP2 176
212#define J721E_DEV_MCASP3 177
213#define J721E_DEV_MCASP4 178
214#define J721E_DEV_MCASP5 179
215#define J721E_DEV_MCASP6 180
216#define J721E_DEV_MCASP7 181
217#define J721E_DEV_MCASP8 182
218#define J721E_DEV_MCASP9 183
219#define J721E_DEV_MCASP10 184
220#define J721E_DEV_MCASP11 185
221#define J721E_DEV_MLB0 186
222#define J721E_DEV_I2C0 187
223#define J721E_DEV_I2C1 188
224#define J721E_DEV_I2C2 189
225#define J721E_DEV_I2C3 190
226#define J721E_DEV_I2C4 191
227#define J721E_DEV_I2C5 192
228#define J721E_DEV_I2C6 193
229#define J721E_DEV_MCU_I2C0 194
230#define J721E_DEV_MCU_I2C1 195
231#define J721E_DEV_WKUP_I2C0 197
232#define J721E_DEV_NAVSS512L_MAIN_0 199
233#define J721E_DEV_NAVSS0_CPTS_0 201
234#define J721E_DEV_A72SS0_CORE0 202
235#define J721E_DEV_A72SS0_CORE1 203
236#define J721E_DEV_NAVSS0_DTI_0 206
237#define J721E_DEV_NAVSS0_MODSS_INTAGGR_0 207
238#define J721E_DEV_NAVSS0_MODSS_INTAGGR_1 208
239#define J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 209
240#define J721E_DEV_NAVSS0_PROXY_0 210
241#define J721E_DEV_NAVSS0_RINGACC_0 211
242#define J721E_DEV_NAVSS0_UDMAP_0 212
243#define J721E_DEV_NAVSS0_INTR_ROUTER_0 213
244#define J721E_DEV_NAVSS0_MAILBOX_0 214
245#define J721E_DEV_NAVSS0_MAILBOX_1 215
246#define J721E_DEV_NAVSS0_MAILBOX_2 216
247#define J721E_DEV_NAVSS0_MAILBOX_3 217
248#define J721E_DEV_NAVSS0_MAILBOX_4 218
249#define J721E_DEV_NAVSS0_MAILBOX_5 219
250#define J721E_DEV_NAVSS0_MAILBOX_6 220
251#define J721E_DEV_NAVSS0_MAILBOX_7 221
252#define J721E_DEV_NAVSS0_MAILBOX_8 222
253#define J721E_DEV_NAVSS0_MAILBOX_9 223
254#define J721E_DEV_NAVSS0_MAILBOX_10 224
255#define J721E_DEV_NAVSS0_MAILBOX_11 225
256#define J721E_DEV_NAVSS0_SPINLOCK_0 226
257#define J721E_DEV_NAVSS0_MCRC_0 227
258#define J721E_DEV_NAVSS0_TBU_0 228
259#define J721E_DEV_NAVSS0_TCU_0 229
260#define J721E_DEV_NAVSS0_TIMERMGR_0 230
261#define J721E_DEV_NAVSS0_TIMERMGR_1 231
262#define J721E_DEV_NAVSS_MCU_J7_MCU_0 232
263#define J721E_DEV_MCU_NAVSS0_INTAGGR_0 233
264#define J721E_DEV_MCU_NAVSS0_PROXY_0 234
265#define J721E_DEV_MCU_NAVSS0_RINGACC_0 235
266#define J721E_DEV_MCU_NAVSS0_UDMAP_0 236
267#define J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0 237
268#define J721E_DEV_MCU_NAVSS0_MCRC_0 238
269#define J721E_DEV_PCIE0 239
270#define J721E_DEV_PCIE1 240
271#define J721E_DEV_PCIE2 241
272#define J721E_DEV_PCIE3 242
273#define J721E_DEV_PULSAR_SL_MAIN_0 243
274#define J721E_DEV_PULSAR_SL_MAIN_1 244
275#define J721E_DEV_R5FSS0_CORE0 245
276#define J721E_DEV_R5FSS0_CORE1 246
277#define J721E_DEV_R5FSS1_CORE0 247
278#define J721E_DEV_R5FSS1_CORE1 248
279#define J721E_DEV_PULSAR_SL_MCU_0 249
280#define J721E_DEV_MCU_R5FSS0_CORE0 250
281#define J721E_DEV_MCU_R5FSS0_CORE1 251
282#define J721E_DEV_RTI0 252
283#define J721E_DEV_RTI1 253
284#define J721E_DEV_RTI24 254
285#define J721E_DEV_RTI25 255
286#define J721E_DEV_RTI16 256
287#define J721E_DEV_RTI15 257
288#define J721E_DEV_RTI28 258
289#define J721E_DEV_RTI29 259
290#define J721E_DEV_RTI30 260
291#define J721E_DEV_RTI31 261
292#define J721E_DEV_MCU_RTI0 262
293#define J721E_DEV_MCU_RTI1 263
294#define J721E_DEV_SA2_UL0 264
295#define J721E_DEV_MCU_SA2_UL0 265
296#define J721E_DEV_MCSPI0 266
297#define J721E_DEV_MCSPI1 267
298#define J721E_DEV_MCSPI2 268
299#define J721E_DEV_MCSPI3 269
300#define J721E_DEV_MCSPI4 270
301#define J721E_DEV_MCSPI5 271
302#define J721E_DEV_MCSPI6 272
303#define J721E_DEV_MCSPI7 273
304#define J721E_DEV_MCU_MCSPI0 274
305#define J721E_DEV_MCU_MCSPI1 275
306#define J721E_DEV_MCU_MCSPI2 276
307#define J721E_DEV_UFS0 277
308#define J721E_DEV_UART1 278
309#define J721E_DEV_UART2 279
310#define J721E_DEV_UART3 280
311#define J721E_DEV_UART4 281
312#define J721E_DEV_UART5 282
313#define J721E_DEV_UART6 283
314#define J721E_DEV_UART7 284
315#define J721E_DEV_UART8 285
316#define J721E_DEV_UART9 286
317#define J721E_DEV_WKUP_UART0 287
318#define J721E_DEV_USB0 288
319#define J721E_DEV_USB1 289
320#define J721E_DEV_VPAC_TOP_MAIN_0 290
321#define J721E_DEV_VPFE0 291
322#define J721E_DEV_SERDES_16G0 292
323#define J721E_DEV_SERDES_16G1 293
324#define J721E_DEV_SERDES_16G2 294
325#define J721E_DEV_SERDES_16G3 295
326#define J721E_DEV_DPHY_TX0 296
327#define J721E_DEV_SERDES_10G0 297
328#define J721E_DEV_WKUPMCU2MAIN_VD 298
329#define J721E_DEV_NAVSS0_MODSS 299
330#define J721E_DEV_NAVSS0_UDMASS 300
331#define J721E_DEV_NAVSS0_VIRTSS 301
332#define J721E_DEV_MCU_NAVSS0_MODSS 302
333#define J721E_DEV_MCU_NAVSS0_UDMASS 303
334#define J721E_DEV_DEBUGSS_WRAP0 304
335#define J721E_DEV_DMPAC0_SDE_0 305
336
337#endif /* SOC_J721E_DEVICES_H */
diff --git a/include/soc/j721e/hosts.h b/include/soc/j721e/hosts.h
new file mode 100644
index 000000000..7a55f6084
--- /dev/null
+++ b/include/soc/j721e/hosts.h
@@ -0,0 +1,101 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef J721E_HOSTS_H
36#define J721E_HOSTS_H
37
38/* Host IDs for J721E Device */
39
40/** DMSC(Secure): Device Management and Security Control */
41#define HOST_ID_DMSC (0U)
42/** MCU_0_R5_0(Non Secure): Cortex R5 context 0 on MCU island */
43#define HOST_ID_MCU_0_R5_0 (3U)
44/** MCU_0_R5_1(Secure): Cortex R5 context 1 on MCU island(Boot) */
45#define HOST_ID_MCU_0_R5_1 (4U)
46/** MCU_0_R5_2(Non Secure): Cortex R5 context 2 on MCU island */
47#define HOST_ID_MCU_0_R5_2 (5U)
48/** MCU_0_R5_3(Secure): Cortex R5 context 3 on MCU island */
49#define HOST_ID_MCU_0_R5_3 (6U)
50/** A72_0(Secure): Cortex A72 context 0 on Main island */
51#define HOST_ID_A72_0 (10U)
52/** A72_1(Secure): Cortex A72 context 1 on Main island */
53#define HOST_ID_A72_1 (11U)
54/** A72_2(Non Secure): Cortex A72 context 2 on Main island */
55#define HOST_ID_A72_2 (12U)
56/** A72_3(Non Secure): Cortex A72 context 3 on Main island */
57#define HOST_ID_A72_3 (13U)
58/** A72_4(Non Secure): Cortex A72 context 4 on Main island */
59#define HOST_ID_A72_4 (14U)
60/** C7X_0(Secure): C7x Context 0 on Main island */
61#define HOST_ID_C7X_0 (20U)
62/** C7X_1(Non Secure): C7x context 1 on Main island */
63#define HOST_ID_C7X_1 (21U)
64/** C6X_0_0(Secure): C6x_0 Context 0 on Main island */
65#define HOST_ID_C6X_0_0 (25U)
66/** C6X_0_1(Non Secure): C6x_0 context 1 on Main island */
67#define HOST_ID_C6X_0_1 (26U)
68/** C6X_1_0(Secure): C6x_1 Context 0 on Main island */
69#define HOST_ID_C6X_1_0 (27U)
70/** C6X_1_1(Non Secure): C6x_1 context 1 on Main island */
71#define HOST_ID_C6X_1_1 (28U)
72/** GPU_0(Non Secure): RGX context 0 on Main island */
73#define HOST_ID_GPU_0 (30U)
74/** MAIN_0_R5_0(Non Secure): Cortex R5_0 context 0 on Main island */
75#define HOST_ID_MAIN_0_R5_0 (35U)
76/** MAIN_0_R5_1(Secure): Cortex R5_0 context 1 on Main island */
77#define HOST_ID_MAIN_0_R5_1 (36U)
78/** MAIN_0_R5_2(Non Secure): Cortex R5_0 context 2 on Main island */
79#define HOST_ID_MAIN_0_R5_2 (37U)
80/** MAIN_0_R5_3(Secure): Cortex R5_0 context 3 on MCU island */
81#define HOST_ID_MAIN_0_R5_3 (38U)
82/** MAIN_1_R5_0(Non Secure): Cortex R5_1 context 0 on Main island */
83#define HOST_ID_MAIN_1_R5_0 (40U)
84/** MAIN_1_R5_1(Secure): Cortex R5_1 context 1 on Main island */
85#define HOST_ID_MAIN_1_R5_1 (41U)
86/** MAIN_1_R5_2(Non Secure): Cortex R5_1 context 2 on Main island */
87#define HOST_ID_MAIN_1_R5_2 (42U)
88/** MAIN_1_R5_3(Secure): Cortex R5_1 context 3 on MCU island */
89#define HOST_ID_MAIN_1_R5_3 (43U)
90/** ICSSG_0(Non Secure): ICSSG context 0 on Main island */
91#define HOST_ID_ICSSG_0 (50U)
92
93/** Host catch all. Used in board configuration resource assignments to
94 * define resource ranges useable by all hosts. Cannot be used as a host
95 * in TISCI message headers */
96#define HOST_ID_ALL (128U)
97
98/** Number of unique hosts on the J721E SoC */
99#define HOST_ID_CNT (26U)
100
101#endif /* J721E_HOSTS_H */
diff --git a/include/soc/j721e/resasg_types.h b/include/soc/j721e/resasg_types.h
new file mode 100644
index 000000000..7265135c6
--- /dev/null
+++ b/include/soc/j721e/resasg_types.h
@@ -0,0 +1,206 @@
1/*
2 * K3 System Firmware Board Configuration Data Definitions
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef RESASG_TYPES_H
36#define RESASG_TYPES_H
37
38/**
39 * Resource assignment type shift
40 */
41#define RESASG_TYPE_SHIFT (0x0006U)
42
43/**
44 * Resource assignment type mask
45 */
46#define RESASG_TYPE_MASK (0xFFC0U)
47
48/**
49 * Resource assignment subtype shift
50 */
51#define RESASG_SUBTYPE_SHIFT (0x0000U)
52
53/**
54 * Resource assignment subtype mask
55 */
56#define RESASG_SUBTYPE_MASK (0x003FU)
57
58/**
59 * Macro to create unique resource assignment types using type and subtype
60 */
61#define RESASG_UTYPE(type, subtype) \
62 (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \
63 ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK))
64
65/**
66 * IA subtypes definitions
67 */
68#define RESASG_SUBTYPE_IA_VINT (0x000AU)
69#define RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)
70#define RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)
71#define RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)
72#define RESASG_SUBTYPES_IA_CNT (0x0004U)
73
74/**
75 * IRQ subtypes definitions
76 */
77#define RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS0_INTROUTER0 (0x0000U)
78#define RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS0_INTROUTER0 (0x0001U)
79#define RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS0_INTROUTER0 (0x0002U)
80#define RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS0_INTROUTER0 (0x0003U)
81#define RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS0_INTROUTER0 (0x0004U)
82#define RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS1_INTROUTER0 (0x0000U)
83#define RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS1_INTROUTER0 (0x0001U)
84#define RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS1_INTROUTER0 (0x0002U)
85#define RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS1_INTROUTER0 (0x0003U)
86#define RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS1_INTROUTER0 (0x0004U)
87#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0003U)
88#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
89#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0000U)
90#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0005U)
91#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 (0x0002U)
92#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0 (0x0004U)
93#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0003U)
94#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
95#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0000U)
96#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0005U)
97#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 (0x0002U)
98#define RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0 (0x0004U)
99#define RESASG_SUBTYPE_CPSW0_CPTS_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
100#define RESASG_SUBTYPE_CPSW0_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
101#define RESASG_SUBTYPE_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
102#define RESASG_SUBTYPE_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
103#define RESASG_SUBTYPE_CPSW0_CPTS_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0004U)
104#define RESASG_SUBTYPE_CPSW0_CPTS_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0005U)
105#define RESASG_SUBTYPE_CPSW0_CPTS_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0006U)
106#define RESASG_SUBTYPE_CPSW0_CPTS_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0007U)
107#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
108#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
109#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0002U)
110#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
111#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
112#define RESASG_SUBTYPE_MCU_NAVSS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
113#define RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
114#define RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
115#define RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
116#define RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0004U)
117#define RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
118#define RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
119#define RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
120#define RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
121#define RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0004U)
122#define RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
123#define RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0001U)
124#define RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0002U)
125#define RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
126#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
127#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
128#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
129#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
130#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0004U)
131#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0005U)
132#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0006U)
133#define RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0007U)
134#define RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
135#define RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
136#define RESASG_SUBTYPE_PCIE2_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
137#define RESASG_SUBTYPE_PCIE3_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
138#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
139#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
140#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
141#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
142#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
143#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
144#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
145#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
146#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
147#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
148#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
149#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
150#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
151#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
152#define RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
153#define RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0001U)
154#define RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0 (0x0002U)
155#define RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
156#define RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0001U)
157#define RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0 (0x0002U)
158#define RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
159#define RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0001U)
160#define RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0 (0x0002U)
161#define RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
162#define RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0001U)
163#define RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0 (0x0002U)
164#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
165#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
166#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0002U)
167#define RESASG_SUBTYPES_IRQ_CNT (0x005AU)
168
169/**
170 * RA subtypes definitions
171 */
172#define RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)
173#define RESASG_SUBTYPE_RA_GP (0x0001U)
174#define RESASG_SUBTYPE_RA_UDMAP_RX (0x0002U)
175#define RESASG_SUBTYPE_RA_UDMAP_TX (0x0003U)
176#define RESASG_SUBTYPE_RA_UDMAP_TX_EXT (0x0004U)
177#define RESASG_SUBTYPE_RA_UDMAP_RX_H (0x0005U)
178#define RESASG_SUBTYPE_RA_UDMAP_RX_UH (0x0006U)
179#define RESASG_SUBTYPE_RA_UDMAP_TX_H (0x0007U)
180#define RESASG_SUBTYPE_RA_UDMAP_TX_UH (0x0008U)
181#define RESASG_SUBTYPE_RA_VIRTID (0x000AU)
182#define RESASG_SUBTYPES_RA_CNT (0x000AU)
183
184/**
185 * UDMAP subtypes definitions
186 */
187#define RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON (0x0000U)
188#define RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES (0x0001U)
189#define RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)
190#define RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)
191#define RESASG_SUBTYPE_UDMAP_RX_CHAN (0x000AU)
192#define RESASG_SUBTYPE_UDMAP_RX_HCHAN (0x000BU)
193#define RESASG_SUBTYPE_UDMAP_RX_UHCHAN (0x000CU)
194#define RESASG_SUBTYPE_UDMAP_TX_CHAN (0x000DU)
195#define RESASG_SUBTYPE_UDMAP_TX_ECHAN (0x000EU)
196#define RESASG_SUBTYPE_UDMAP_TX_HCHAN (0x000FU)
197#define RESASG_SUBTYPE_UDMAP_TX_UHCHAN (0x0010U)
198#define RESASG_SUBTYPES_UDMAP_CNT (0x000BU)
199
200
201/**
202 * Total number of unique resource types for J721E
203 */
204#define RESASG_UTYPE_CNT 134U
205
206#endif /* RESASG_TYPES_H */