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author | Vignesh Raghavendra | 2019-07-31 03:02:05 -0500 |
---|---|---|
committer | Andreas Dannenberg | 2019-08-05 11:22:35 -0500 |
commit | 450325e6152bfedb3142e35f55cf80999bfde757 (patch) | |
tree | c5c34e52460f13a19f5cbfa2c8f121c41cdebbe4 /soc/am65x/evm | |
parent | 25db50f9c505fb5e870264930dce67a28817cde8 (diff) | |
download | k3-image-gen-450325e6152bfedb3142e35f55cf80999bfde757.tar.gz k3-image-gen-450325e6152bfedb3142e35f55cf80999bfde757.tar.xz k3-image-gen-450325e6152bfedb3142e35f55cf80999bfde757.zip |
am65x: rm-cfg: Add resources for secure context of MCU R5
ROM boots up MCU R5 in secure context and R5 SPL continues to run in the
same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU
NAVSS resources with MCU R5 secure host ID that is used by R5 SPL.
Resources allocated are same as those allocated for A53.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'soc/am65x/evm')
-rw-r--r-- | soc/am65x/evm/rm-cfg.c | 42 | ||||
-rw-r--r-- | soc/am65x/evm/sysfw_img_cfg.h | 2 |
2 files changed, 43 insertions, 1 deletions
diff --git a/soc/am65x/evm/rm-cfg.c b/soc/am65x/evm/rm-cfg.c index ac72f87fa..01a888acd 100644 --- a/soc/am65x/evm/rm-cfg.c +++ b/soc/am65x/evm/rm-cfg.c | |||
@@ -271,6 +271,27 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = { | |||
271 | .host_id = HOST_ID_A53_2, | 271 | .host_id = HOST_ID_A53_2, |
272 | }, | 272 | }, |
273 | { | 273 | { |
274 | .start_resource = 2, | ||
275 | .num_resource = 46, | ||
276 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, | ||
277 | RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN), | ||
278 | .host_id = HOST_ID_R5_1, | ||
279 | }, | ||
280 | { | ||
281 | .start_resource = 2, | ||
282 | .num_resource = 46, | ||
283 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, | ||
284 | RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN), | ||
285 | .host_id = HOST_ID_R5_1, | ||
286 | }, | ||
287 | { | ||
288 | .start_resource = 48, | ||
289 | .num_resource = 48, | ||
290 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, | ||
291 | RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON), | ||
292 | .host_id = HOST_ID_R5_1, | ||
293 | }, | ||
294 | { | ||
274 | .start_resource = 0, | 295 | .start_resource = 0, |
275 | .num_resource = 1, | 296 | .num_resource = 1, |
276 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, | 297 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, |
@@ -335,6 +356,27 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = { | |||
335 | }, | 356 | }, |
336 | { | 357 | { |
337 | .start_resource = 0, | 358 | .start_resource = 0, |
359 | .num_resource = 48, | ||
360 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, | ||
361 | RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX), | ||
362 | .host_id = HOST_ID_R5_1, | ||
363 | }, | ||
364 | { | ||
365 | .start_resource = 48, | ||
366 | .num_resource = 48, | ||
367 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, | ||
368 | RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX), | ||
369 | .host_id = HOST_ID_R5_1, | ||
370 | }, | ||
371 | { | ||
372 | .start_resource = 96, | ||
373 | .num_resource = 160, | ||
374 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, | ||
375 | RESASG_SUBTYPE_MCU_NAV_RA_RING_GP), | ||
376 | .host_id = HOST_ID_R5_1, | ||
377 | }, | ||
378 | { | ||
379 | .start_resource = 0, | ||
338 | .num_resource = 1, | 380 | .num_resource = 1, |
339 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, | 381 | .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, |
340 | RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES), | 382 | RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES), |
diff --git a/soc/am65x/evm/sysfw_img_cfg.h b/soc/am65x/evm/sysfw_img_cfg.h index de5f1ab00..20b33e07f 100644 --- a/soc/am65x/evm/sysfw_img_cfg.h +++ b/soc/am65x/evm/sysfw_img_cfg.h | |||
@@ -35,6 +35,6 @@ | |||
35 | #ifndef SYSFW_IMG_CFG_H | 35 | #ifndef SYSFW_IMG_CFG_H |
36 | #define SYSFW_IMG_CFG_H | 36 | #define SYSFW_IMG_CFG_H |
37 | 37 | ||
38 | #define BOARDCFG_RM_RESASG_ENTRIES 59 | 38 | #define BOARDCFG_RM_RESASG_ENTRIES 65 |
39 | 39 | ||
40 | #endif /* SYSFW_IMG_CFG_H */ | 40 | #endif /* SYSFW_IMG_CFG_H */ |