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authorLokesh Vutla2020-03-24 08:22:00 -0500
committerDave Gerlach2020-04-03 15:41:00 -0500
commitdb9b576019b674e822e8acf4252fb96ee4ed18e5 (patch)
treecde166e9469225f2848be9cffceb942ee266ff14 /soc/am65x/evm
parentd7e90ec350237720cf36c465bfa88178e81010c3 (diff)
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am65x: Update to ABI 3.0 resource types
Update the AM65x RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'soc/am65x/evm')
-rw-r--r--soc/am65x/evm/rm-cfg.c383
-rw-r--r--soc/am65x/evm/sysfw_img_cfg.h2
2 files changed, 136 insertions, 249 deletions
diff --git a/soc/am65x/evm/rm-cfg.c b/soc/am65x/evm/rm-cfg.c
index 3692b0b29..1894ac1c1 100644
--- a/soc/am65x/evm/rm-cfg.c
+++ b/soc/am65x/evm/rm-cfg.c
@@ -70,457 +70,344 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = {
70 { 70 {
71 .start_resource = 16, 71 .start_resource = 16,
72 .num_resource = 240, 72 .num_resource = 240,
73 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMASS_IA0, 73 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0,
74 RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT), 74 RESASG_SUBTYPE_IA_VINT),
75 .host_id = HOST_ID_A53_2, 75 .host_id = HOST_ID_A53_2,
76 }, 76 },
77 { 77 {
78 .start_resource = 16, 78 .start_resource = 16,
79 .num_resource = 4592, 79 .num_resource = 4592,
80 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMASS_IA0, 80 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0,
81 RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI), 81 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
82 .host_id = HOST_ID_A53_2,
83 },
84 {
85 .start_resource = 32768,
86 .num_resource = 512,
87 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
88 RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI),
89 .host_id = HOST_ID_A53_2,
90 },
91 {
92 .start_resource = 36864,
93 .num_resource = 512,
94 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
95 RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI),
96 .host_id = HOST_ID_A53_2, 82 .host_id = HOST_ID_A53_2,
97 }, 83 },
98 { 84 {
99 .start_resource = 0, 85 .start_resource = 0,
100 .num_resource = 64, 86 .num_resource = 64,
101 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_MODSS_IA0, 87 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0,
102 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT), 88 RESASG_SUBTYPE_IA_VINT),
103 .host_id = HOST_ID_A53_2, 89 .host_id = HOST_ID_A53_2,
104 }, 90 },
105 { 91 {
106 .start_resource = 20480, 92 .start_resource = 20480,
107 .num_resource = 1024, 93 .num_resource = 1024,
108 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_MODSS_IA0, 94 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0,
109 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI), 95 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
110 .host_id = HOST_ID_A53_2, 96 .host_id = HOST_ID_A53_2,
111 }, 97 },
112 { 98 {
113 .start_resource = 0, 99 .start_resource = 0,
114 .num_resource = 64, 100 .num_resource = 64,
115 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_MODSS_IA1, 101 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1,
116 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT), 102 RESASG_SUBTYPE_IA_VINT),
117 .host_id = HOST_ID_A53_2, 103 .host_id = HOST_ID_A53_2,
118 }, 104 },
119 { 105 {
120 .start_resource = 22528, 106 .start_resource = 22528,
121 .num_resource = 1024, 107 .num_resource = 1024,
122 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_MODSS_IA1, 108 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1,
123 RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI), 109 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
124 .host_id = HOST_ID_A53_2, 110 .host_id = HOST_ID_A53_2,
125 }, 111 },
126 { 112 {
127 .start_resource = 8, 113 .start_resource = 8,
128 .num_resource = 248, 114 .num_resource = 248,
129 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMASS_IA0, 115 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
130 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT), 116 RESASG_SUBTYPE_IA_VINT),
131 .host_id = HOST_ID_R5_0, 117 .host_id = HOST_ID_R5_0,
132 }, 118 },
133 { 119 {
134 .start_resource = 16392, 120 .start_resource = 16392,
135 .num_resource = 992, 121 .num_resource = 992,
136 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMASS_IA0, 122 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
137 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI), 123 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
138 .host_id = HOST_ID_R5_0, 124 .host_id = HOST_ID_R5_0,
139 }, 125 },
140 { 126 {
141 .start_resource = 17384, 127 .start_resource = 17384,
142 .num_resource = 536, 128 .num_resource = 536,
143 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMASS_IA0, 129 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
144 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI), 130 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
145 .host_id = HOST_ID_R5_0,
146 },
147 {
148 .start_resource = 34816,
149 .num_resource = 128,
150 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMASS_IA0,
151 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI),
152 .host_id = HOST_ID_R5_0,
153 },
154 {
155 .start_resource = 39936,
156 .num_resource = 256,
157 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMASS_IA0,
158 RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI),
159 .host_id = HOST_ID_R5_0,
160 },
161 {
162 .start_resource = 43008,
163 .num_resource = 4,
164 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_MCRC,
165 RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI),
166 .host_id = HOST_ID_R5_0,
167 },
168 {
169 .start_resource = 43136,
170 .num_resource = 4,
171 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_MCRC,
172 RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI),
173 .host_id = HOST_ID_R5_0, 131 .host_id = HOST_ID_R5_0,
174 }, 132 },
175 { 133 {
176 .start_resource = 49152, 134 .start_resource = 49152,
177 .num_resource = 1024, 135 .num_resource = 1024,
178 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 136 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
179 RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER), 137 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
180 .host_id = HOST_ID_A53_2, 138 .host_id = HOST_ID_A53_2,
181 }, 139 },
182 { 140 {
183 .start_resource = 1, 141 .start_resource = 1,
184 .num_resource = 7, 142 .num_resource = 7,
185 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 143 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
186 RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN), 144 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
187 .host_id = HOST_ID_A53_2, 145 .host_id = HOST_ID_A53_2,
188 }, 146 },
189 { 147 {
190 .start_resource = 8, 148 .start_resource = 8,
191 .num_resource = 112, 149 .num_resource = 112,
192 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 150 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
193 RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN), 151 RESASG_SUBTYPE_UDMAP_TX_CHAN),
194 .host_id = HOST_ID_A53_2, 152 .host_id = HOST_ID_A53_2,
195 }, 153 },
196 { 154 {
197 .start_resource = 120, 155 .start_resource = 120,
198 .num_resource = 32, 156 .num_resource = 32,
199 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 157 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
200 RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN), 158 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
201 .host_id = HOST_ID_A53_2, 159 .host_id = HOST_ID_A53_2,
202 }, 160 },
203 { 161 {
204 .start_resource = 2, 162 .start_resource = 2,
205 .num_resource = 6, 163 .num_resource = 6,
206 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 164 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
207 RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN), 165 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
208 .host_id = HOST_ID_A53_2, 166 .host_id = HOST_ID_A53_2,
209 }, 167 },
210 { 168 {
211 .start_resource = 8, 169 .start_resource = 8,
212 .num_resource = 142, 170 .num_resource = 142,
213 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 171 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
214 RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN), 172 RESASG_SUBTYPE_UDMAP_RX_CHAN),
215 .host_id = HOST_ID_A53_2, 173 .host_id = HOST_ID_A53_2,
216 }, 174 },
217 { 175 {
218 .start_resource = 150, 176 .start_resource = 150,
219 .num_resource = 150, 177 .num_resource = 150,
220 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 178 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
221 RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON), 179 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
222 .host_id = HOST_ID_A53_2, 180 .host_id = HOST_ID_A53_2,
223 }, 181 },
224 { 182 {
225 .start_resource = 0, 183 .start_resource = 0,
226 .num_resource = 1, 184 .num_resource = 1,
227 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_UDMAP, 185 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
228 RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES), 186 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
229 .host_id = HOST_ID_A53_2, 187 .host_id = HOST_ID_A53_2,
230 }, 188 },
231 { 189 {
232 .start_resource = 56320, 190 .start_resource = 56320,
233 .num_resource = 256, 191 .num_resource = 256,
234 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 192 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
235 RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER), 193 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
236 .host_id = HOST_ID_A53_2, 194 .host_id = HOST_ID_A53_2,
237 }, 195 },
238 { 196 {
239 .start_resource = 0, 197 .start_resource = 0,
240 .num_resource = 2, 198 .num_resource = 2,
241 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 199 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
242 RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN), 200 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
243 .host_id = HOST_ID_A53_2, 201 .host_id = HOST_ID_A53_2,
244 }, 202 },
245 { 203 {
246 .start_resource = 2, 204 .start_resource = 2,
247 .num_resource = 46, 205 .num_resource = 46,
248 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 206 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
249 RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN), 207 RESASG_SUBTYPE_UDMAP_TX_CHAN),
250 .host_id = HOST_ID_A53_2, 208 .host_id = HOST_ID_A53_2,
251 }, 209 },
252 { 210 {
253 .start_resource = 0, 211 .start_resource = 0,
254 .num_resource = 2, 212 .num_resource = 2,
255 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 213 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
256 RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN), 214 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
257 .host_id = HOST_ID_A53_2, 215 .host_id = HOST_ID_A53_2,
258 }, 216 },
259 { 217 {
260 .start_resource = 2, 218 .start_resource = 2,
261 .num_resource = 46, 219 .num_resource = 46,
262 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 220 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
263 RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN), 221 RESASG_SUBTYPE_UDMAP_RX_CHAN),
264 .host_id = HOST_ID_A53_2, 222 .host_id = HOST_ID_A53_2,
265 }, 223 },
266 { 224 {
267 .start_resource = 48, 225 .start_resource = 48,
268 .num_resource = 48, 226 .num_resource = 48,
269 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 227 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
270 RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON), 228 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
271 .host_id = HOST_ID_A53_2, 229 .host_id = HOST_ID_A53_2,
272 }, 230 },
273 { 231 {
274 .start_resource = 2, 232 .start_resource = 2,
275 .num_resource = 46, 233 .num_resource = 46,
276 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 234 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
277 RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN), 235 RESASG_SUBTYPE_UDMAP_TX_CHAN),
278 .host_id = HOST_ID_R5_1, 236 .host_id = HOST_ID_R5_1,
279 }, 237 },
280 { 238 {
281 .start_resource = 2, 239 .start_resource = 2,
282 .num_resource = 46, 240 .num_resource = 46,
283 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 241 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
284 RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN), 242 RESASG_SUBTYPE_UDMAP_RX_CHAN),
285 .host_id = HOST_ID_R5_1, 243 .host_id = HOST_ID_R5_1,
286 }, 244 },
287 { 245 {
288 .start_resource = 48, 246 .start_resource = 48,
289 .num_resource = 48, 247 .num_resource = 48,
290 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 248 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
291 RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON), 249 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
292 .host_id = HOST_ID_R5_1, 250 .host_id = HOST_ID_R5_1,
293 }, 251 },
294 { 252 {
295 .start_resource = 0, 253 .start_resource = 0,
296 .num_resource = 1, 254 .num_resource = 1,
297 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_UDMAP, 255 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
298 RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES), 256 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
299 .host_id = HOST_ID_A53_2, 257 .host_id = HOST_ID_A53_2,
300 }, 258 },
301 { 259 {
302 .start_resource = 61440, 260 .start_resource = 1,
303 .num_resource = 64, 261 .num_resource = 7,
304 .type = RESASG_UTYPE(RESASG_TYPE_MSMC, 262 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
305 RESASG_SUBTYPE_MSMC_DRU), 263 RESASG_SUBTYPE_RA_UDMAP_TX_H),
306 .host_id = HOST_ID_A53_2, 264 .host_id = HOST_ID_A53_2,
307 }, 265 },
308 { 266 {
309 .start_resource = 1, 267 .start_resource = 8,
310 .num_resource = 151, 268 .num_resource = 112,
311 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_RA, 269 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
312 RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX), 270 RESASG_SUBTYPE_RA_UDMAP_TX),
313 .host_id = HOST_ID_A53_2, 271 .host_id = HOST_ID_A53_2,
314 }, 272 },
315 { 273 {
316 .start_resource = 153, 274 .start_resource = 153,
317 .num_resource = 149, 275 .num_resource = 7,
318 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_RA, 276 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
319 RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX), 277 RESASG_SUBTYPE_RA_UDMAP_RX_H),
278 .host_id = HOST_ID_A53_2,
279 },
280 {
281 .start_resource = 160,
282 .num_resource = 142,
283 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
284 RESASG_SUBTYPE_RA_UDMAP_RX),
320 .host_id = HOST_ID_A53_2, 285 .host_id = HOST_ID_A53_2,
321 }, 286 },
322 { 287 {
323 .start_resource = 304, 288 .start_resource = 304,
324 .num_resource = 464, 289 .num_resource = 464,
325 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_RA, 290 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
326 RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP), 291 RESASG_SUBTYPE_RA_GP),
327 .host_id = HOST_ID_A53_2, 292 .host_id = HOST_ID_A53_2,
328 }, 293 },
329 { 294 {
330 .start_resource = 0, 295 .start_resource = 0,
331 .num_resource = 1, 296 .num_resource = 1,
332 .type = RESASG_UTYPE(RESASG_TYPE_MAIN_NAV_RA, 297 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
333 RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES), 298 RESASG_SUBTYPE_RA_ERROR_OES),
334 .host_id = HOST_ID_A53_2, 299 .host_id = HOST_ID_A53_2,
335 }, 300 },
336 { 301 {
337 .start_resource = 0, 302 .start_resource = 0,
338 .num_resource = 48, 303 .num_resource = 2,
339 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 304 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
340 RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX), 305 RESASG_SUBTYPE_RA_UDMAP_TX_H),
306 .host_id = HOST_ID_A53_2,
307 },
308 {
309 .start_resource = 2,
310 .num_resource = 46,
311 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
312 RESASG_SUBTYPE_RA_UDMAP_TX),
341 .host_id = HOST_ID_A53_2, 313 .host_id = HOST_ID_A53_2,
342 }, 314 },
343 { 315 {
344 .start_resource = 48, 316 .start_resource = 48,
345 .num_resource = 48, 317 .num_resource = 2,
346 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 318 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
347 RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX), 319 RESASG_SUBTYPE_RA_UDMAP_RX_H),
320 .host_id = HOST_ID_A53_2,
321 },
322 {
323 .start_resource = 50,
324 .num_resource = 46,
325 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
326 RESASG_SUBTYPE_RA_UDMAP_RX),
348 .host_id = HOST_ID_A53_2, 327 .host_id = HOST_ID_A53_2,
349 }, 328 },
350 { 329 {
351 .start_resource = 96, 330 .start_resource = 96,
352 .num_resource = 160, 331 .num_resource = 160,
353 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 332 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
354 RESASG_SUBTYPE_MCU_NAV_RA_RING_GP), 333 RESASG_SUBTYPE_RA_GP),
355 .host_id = HOST_ID_A53_2, 334 .host_id = HOST_ID_A53_2,
356 }, 335 },
357 { 336 {
358 .start_resource = 0, 337 .start_resource = 2,
359 .num_resource = 48, 338 .num_resource = 46,
360 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 339 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
361 RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX), 340 RESASG_SUBTYPE_RA_UDMAP_TX),
362 .host_id = HOST_ID_R5_1, 341 .host_id = HOST_ID_R5_1,
363 }, 342 },
364 { 343 {
365 .start_resource = 48, 344 .start_resource = 50,
366 .num_resource = 48, 345 .num_resource = 46,
367 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 346 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
368 RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX), 347 RESASG_SUBTYPE_RA_UDMAP_RX),
369 .host_id = HOST_ID_R5_1, 348 .host_id = HOST_ID_R5_1,
370 }, 349 },
371 { 350 {
372 .start_resource = 96, 351 .start_resource = 96,
373 .num_resource = 160, 352 .num_resource = 160,
374 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 353 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
375 RESASG_SUBTYPE_MCU_NAV_RA_RING_GP), 354 RESASG_SUBTYPE_RA_GP),
376 .host_id = HOST_ID_R5_1, 355 .host_id = HOST_ID_R5_1,
377 }, 356 },
378 { 357 {
379 .start_resource = 0, 358 .start_resource = 0,
380 .num_resource = 1, 359 .num_resource = 1,
381 .type = RESASG_UTYPE(RESASG_TYPE_MCU_NAV_RA, 360 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
382 RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES), 361 RESASG_SUBTYPE_RA_ERROR_OES),
383 .host_id = HOST_ID_A53_2,
384 },
385 {
386 .start_resource = 80,
387 .num_resource = 48,
388 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ,
389 RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0),
390 .host_id = HOST_ID_A53_2, 362 .host_id = HOST_ID_A53_2,
391 }, 363 },
392 { 364 {
393 .start_resource = 392, 365 .type = RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
366 .start_resource = 0,
394 .num_resource = 32, 367 .num_resource = 32,
395 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ,
396 RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO),
397 .host_id = HOST_ID_A53_2,
398 },
399 {
400 .start_resource = 448,
401 .num_resource = 50,
402 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ,
403 RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1),
404 .host_id = HOST_ID_A53_2,
405 },
406 {
407 .start_resource = 498,
408 .num_resource = 6,
409 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ,
410 RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1),
411 .host_id = HOST_ID_A53_2, 368 .host_id = HOST_ID_A53_2,
412 }, 369 },
413 { 370 {
414 .start_resource = 544, 371 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
415 .num_resource = 16, 372 .start_resource = 0,
416 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ, 373 .num_resource = 64,
417 RESASG_SUBTYPE_GIC_IRQ_COMP_EVT),
418 .host_id = HOST_ID_A53_2,
419 },
420 {
421 .start_resource = 712,
422 .num_resource = 16,
423 .type = RESASG_UTYPE(RESASG_TYPE_GIC_IRQ,
424 RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO),
425 .host_id = HOST_ID_A53_2,
426 },
427 {
428 .start_resource = 68,
429 .num_resource = 28,
430 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C0_IRQ,
431 RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV),
432 .host_id = HOST_ID_R5_0, 374 .host_id = HOST_ID_R5_0,
433 }, 375 },
434 { 376 {
435 .start_resource = 124, 377 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
436 .num_resource = 16, 378 .start_resource = 0,
437 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C0_IRQ, 379 .num_resource = 48,
438 RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO),
439 .host_id = HOST_ID_R5_0, 380 .host_id = HOST_ID_R5_0,
440 }, 381 },
441 { 382 {
442 .start_resource = 160, 383 .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
384 .start_resource = 0,
443 .num_resource = 32, 385 .num_resource = 32,
444 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C0_IRQ, 386 .host_id = HOST_ID_A53_2,
445 RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL),
446 .host_id = HOST_ID_R5_0,
447 },
448 {
449 .start_resource = 224,
450 .num_resource = 48,
451 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C0_IRQ,
452 RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS),
453 .host_id = HOST_ID_R5_0,
454 }, 387 },
455 { 388 {
456 .start_resource = 68, 389 .type = RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
457 .num_resource = 28, 390 .start_resource = 0,
458 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C1_IRQ, 391 .num_resource = 40,
459 RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV), 392 .host_id = HOST_ID_A53_2,
460 .host_id = HOST_ID_R5_0,
461 }, 393 },
462 { 394 {
463 .start_resource = 124, 395 .type = RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
396 .start_resource = 0,
464 .num_resource = 16, 397 .num_resource = 16,
465 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C1_IRQ, 398 .host_id = HOST_ID_A53_2,
466 RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO),
467 .host_id = HOST_ID_R5_0,
468 }, 399 },
469 { 400 {
470 .start_resource = 192, 401 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
471 .num_resource = 32, 402 .start_resource = 16,
472 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C1_IRQ, 403 .num_resource = 136,
473 RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL), 404 .host_id = HOST_ID_A53_2,
474 .host_id = HOST_ID_R5_2,
475 }, 405 },
476 { 406 {
477 .start_resource = 224, 407 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
478 .num_resource = 48, 408 .start_resource = 4,
479 .type = RESASG_UTYPE(RESASG_TYPE_PULSAR_C1_IRQ, 409 .num_resource = 28,
480 RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS),
481 .host_id = HOST_ID_R5_0, 410 .host_id = HOST_ID_R5_0,
482 }, 411 },
483 {
484 .start_resource = 46,
485 .num_resource = 8,
486 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG0_IRQ,
487 RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV),
488 .host_id = HOST_ID_ICSSG_0,
489 },
490 {
491 .start_resource = 88,
492 .num_resource = 8,
493 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG0_IRQ,
494 RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO),
495 .host_id = HOST_ID_ICSSG_0,
496 },
497 {
498 .start_resource = 46,
499 .num_resource = 8,
500 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG1_IRQ,
501 RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV),
502 .host_id = HOST_ID_ICSSG_1,
503 },
504 {
505 .start_resource = 88,
506 .num_resource = 8,
507 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG1_IRQ,
508 RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO),
509 .host_id = HOST_ID_ICSSG_1,
510 },
511 {
512 .start_resource = 46,
513 .num_resource = 8,
514 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG2_IRQ,
515 RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV),
516 .host_id = HOST_ID_ICSSG_2,
517 },
518 {
519 .start_resource = 88,
520 .num_resource = 8,
521 .type = RESASG_UTYPE(RESASG_TYPE_ICSSG2_IRQ,
522 RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO),
523 .host_id = HOST_ID_ICSSG_2,
524 },
525 }, 412 },
526}; 413};
diff --git a/soc/am65x/evm/sysfw_img_cfg.h b/soc/am65x/evm/sysfw_img_cfg.h
index 20b33e07f..d517fca9d 100644
--- a/soc/am65x/evm/sysfw_img_cfg.h
+++ b/soc/am65x/evm/sysfw_img_cfg.h
@@ -35,6 +35,6 @@
35#ifndef SYSFW_IMG_CFG_H 35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 36#define SYSFW_IMG_CFG_H
37 37
38#define BOARDCFG_RM_RESASG_ENTRIES 65 38#define BOARDCFG_RM_RESASG_ENTRIES 50
39 39
40#endif /* SYSFW_IMG_CFG_H */ 40#endif /* SYSFW_IMG_CFG_H */
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