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authorVignesh Raghavendra2021-11-18 11:21:18 -0600
committerVignesh Raghavendra2021-11-18 11:50:50 -0600
commit089ada578d3f367966a3e5eb8c6034d92702c325 (patch)
tree630af232c617b11640813fe0d8f263794ae3aeff /soc/am65x_sr2
parentf0761c3ce2c658c94114f0337a327f1ed6673706 (diff)
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am65x_sr2: Remove duplicate boardcfg files
With the SOC_BASE changes, we do not need duplicate boardcfg files. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Yogesh Siraswar <yogeshs@ti.com>
Diffstat (limited to 'soc/am65x_sr2')
-rw-r--r--soc/am65x_sr2/Makefile37
-rw-r--r--soc/am65x_sr2/evm/board-cfg.c92
-rw-r--r--soc/am65x_sr2/evm/pm-cfg.c43
-rw-r--r--soc/am65x_sr2/evm/rm-cfg.c1980
-rw-r--r--soc/am65x_sr2/evm/sec-cfg.c116
-rw-r--r--soc/am65x_sr2/evm/sysfw_img_cfg.h42
6 files changed, 0 insertions, 2310 deletions
diff --git a/soc/am65x_sr2/Makefile b/soc/am65x_sr2/Makefile
deleted file mode 100644
index 585f116dc..000000000
--- a/soc/am65x_sr2/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
1#
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions
6# are met:
7#
8# Redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer.
10#
11# Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the
14# distribution.
15#
16# Neither the name of Texas Instruments Incorporated nor the names of
17# its contributors may be used to endorse or promote products derived
18# from this software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31#
32
33LOADADDR ?= 0x40000
34SCIFS = sci
35
36.PHONY: all
37all: _objtree_build $(ITB) sysfw.itb
diff --git a/soc/am65x_sr2/evm/board-cfg.c b/soc/am65x_sr2/evm/board-cfg.c
deleted file mode 100644
index fe3381222..000000000
--- a/soc/am65x_sr2/evm/board-cfg.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * K3 System Firmware Board Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg am65_boardcfg_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_control */
45 .control = {
46 .subhdr = {
47 .magic = BOARDCFG_CONTROL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_control),
49 },
50 .main_isolation_enable = 0x5A,
51 .main_isolation_hostid = 0x2,
52 },
53
54 /* boardcfg sec_proxy */
55 .secproxy = {
56 .subhdr = {
57 .magic = BOARDCFG_SECPROXY_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_secproxy),
59 },
60 .scaling_factor = 0x1,
61 .scaling_profile = 0x1,
62 .disable_main_nav_secure_proxy = 0,
63 },
64
65 /* boardcfg_msmc */
66 .msmc = {
67 .subhdr = {
68 .magic = BOARDCFG_MSMC_MAGIC_NUM,
69 .size = sizeof(struct boardcfg_msmc),
70 },
71 .msmc_cache_size = 0x10,
72 },
73
74 /* boardcfg_dbg_cfg */
75 .debug_cfg = {
76 .subhdr = {
77 .magic = BOARDCFG_DBG_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dbg_cfg),
79 },
80#ifdef ENABLE_TRACE
81 .trace_dst_enables = BOARDCFG_TRACE_DST_UART0 |
82 BOARDCFG_TRACE_DST_ITM |
83 BOARDCFG_TRACE_DST_MEM,
84 .trace_src_enables = BOARDCFG_TRACE_SRC_PM |
85 BOARDCFG_TRACE_SRC_RM |
86 BOARDCFG_TRACE_SRC_SEC |
87 BOARDCFG_TRACE_SRC_BASE |
88 BOARDCFG_TRACE_SRC_USER |
89 BOARDCFG_TRACE_SRC_SUPR,
90#endif
91 },
92};
diff --git a/soc/am65x_sr2/evm/pm-cfg.c b/soc/am65x_sr2/evm/pm-cfg.c
deleted file mode 100644
index ff3efbd07..000000000
--- a/soc/am65x_sr2/evm/pm-cfg.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * K3 System Firmware Power Management Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_pm am65_boardcfg_pm_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43};
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c
deleted file mode 100644
index 2ac407c72..000000000
--- a/soc/am65x_sr2/evm/rm-cfg.c
+++ /dev/null
@@ -1,1980 +0,0 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37#include <hosts.h>
38#include <devices.h>
39#include <resasg_types.h>
40
41const struct boardcfg_rm_local am65x_boardcfg_rm_data = {
42 .rm_boardcfg = {
43 /* boardcfg_abi_rev */
44 .rev = {
45 .boardcfg_abi_maj = 0x0,
46 .boardcfg_abi_min = 0x1,
47 },
48
49 /* boardcfg_rm_host_cfg */
50 .host_cfg = {
51 .subhdr = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 },
55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_R5_0,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_R5_2,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_A53_2,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 {
81 .host_id = HOST_ID_A53_3,
82 .allowed_atype = 0b101010,
83 .allowed_qos = 0xAAAA,
84 .allowed_orderid = 0xAAAAAAAA,
85 .allowed_priority = 0xAAAA,
86 .allowed_sched_priority = 0xAA,
87 },
88 }
89 },
90
91 /* boardcfg_rm_resasg */
92 .resasg = {
93 .subhdr = {
94 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
95 .size = sizeof (struct boardcfg_rm_resasg),
96 },
97 .resasg_entries_size =
98 BOARDCFG_RM_RESASG_ENTRIES *
99 sizeof (struct boardcfg_rm_resasg_entry),
100 .reserved = 0,
101 /* .resasg_entries is set via boardcfg_rm_local */
102 },
103 },
104
105 /* This is actually part of .resasg */
106 .resasg_entries = {
107 /* Compare event Interrupt router */
108 {
109 .start_resource = 0,
110 .num_resource = 12,
111 .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0,
112 RESASG_SUBTYPE_IR_OUTPUT),
113 .host_id = HOST_ID_A53_2,
114 },
115 {
116 .start_resource = 12,
117 .num_resource = 4,
118 .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0,
119 RESASG_SUBTYPE_IR_OUTPUT),
120 .host_id = HOST_ID_A53_3,
121 },
122 {
123 .start_resource = 16,
124 .num_resource = 8,
125 .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0,
126 RESASG_SUBTYPE_IR_OUTPUT),
127 .host_id = HOST_ID_R5_0,
128 },
129 {
130 .start_resource = 16,
131 .num_resource = 8,
132 .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0,
133 RESASG_SUBTYPE_IR_OUTPUT),
134 .host_id = HOST_ID_R5_1,
135 },
136 {
137 .start_resource = 24,
138 .num_resource = 8,
139 .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0,
140 RESASG_SUBTYPE_IR_OUTPUT),
141 .host_id = HOST_ID_R5_2,
142 },
143 /* Main 2 MCU Level Interrupt Router */
144 {
145 .start_resource = 0,
146 .num_resource = 32,
147 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_LVL_INTRTR0,
148 RESASG_SUBTYPE_IR_OUTPUT),
149 .host_id = HOST_ID_R5_0,
150 },
151 {
152 .start_resource = 0,
153 .num_resource = 32,
154 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_LVL_INTRTR0,
155 RESASG_SUBTYPE_IR_OUTPUT),
156 .host_id = HOST_ID_R5_1,
157 },
158 {
159 .start_resource = 32,
160 .num_resource = 32,
161 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_LVL_INTRTR0,
162 RESASG_SUBTYPE_IR_OUTPUT),
163 .host_id = HOST_ID_R5_2,
164 },
165 /* Main 2 MCU Pulse Interrupt Router */
166 {
167 .start_resource = 0,
168 .num_resource = 24,
169 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_PLS_INTRTR0,
170 RESASG_SUBTYPE_IR_OUTPUT),
171 .host_id = HOST_ID_R5_0,
172 },
173 {
174 .start_resource = 0,
175 .num_resource = 24,
176 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_PLS_INTRTR0,
177 RESASG_SUBTYPE_IR_OUTPUT),
178 .host_id = HOST_ID_R5_1,
179 },
180 {
181 .start_resource = 24,
182 .num_resource = 24,
183 .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_PLS_INTRTR0,
184 RESASG_SUBTYPE_IR_OUTPUT),
185 .host_id = HOST_ID_R5_2,
186 },
187 /* Main GPIO Interrupt Router */
188 {
189 .start_resource = 0,
190 .num_resource = 20,
191 .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0,
192 RESASG_SUBTYPE_IR_OUTPUT),
193 .host_id = HOST_ID_A53_2,
194 },
195 {
196 .start_resource = 20,
197 .num_resource = 4,
198 .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0,
199 RESASG_SUBTYPE_IR_OUTPUT),
200 .host_id = HOST_ID_A53_3,
201 },
202 {
203 .start_resource = 24,
204 .num_resource = 4,
205 .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0,
206 RESASG_SUBTYPE_IR_OUTPUT),
207 .host_id = HOST_ID_R5_0,
208 },
209 {
210 .start_resource = 24,
211 .num_resource = 4,
212 .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0,
213 RESASG_SUBTYPE_IR_OUTPUT),
214 .host_id = HOST_ID_R5_1,
215 },
216 {
217 .start_resource = 28,
218 .num_resource = 4,
219 .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0,
220 RESASG_SUBTYPE_IR_OUTPUT),
221 .host_id = HOST_ID_R5_2,
222 },
223 /* Timesync Interrupt router */
224 {
225 .start_resource = 0,
226 .num_resource = 16,
227 .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0,
228 RESASG_SUBTYPE_IR_OUTPUT),
229 .host_id = HOST_ID_R5_0,
230 },
231 {
232 .start_resource = 0,
233 .num_resource = 16,
234 .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0,
235 RESASG_SUBTYPE_IR_OUTPUT),
236 .host_id = HOST_ID_R5_1,
237 },
238 {
239 .start_resource = 16,
240 .num_resource = 16,
241 .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0,
242 RESASG_SUBTYPE_IR_OUTPUT),
243 .host_id = HOST_ID_R5_2,
244 },
245 {
246 .start_resource = 32,
247 .num_resource = 8,
248 .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0,
249 RESASG_SUBTYPE_IR_OUTPUT),
250 .host_id = HOST_ID_ALL,
251 },
252 /* Wakeup GPIO Interrupt router */
253 {
254 .start_resource = 0,
255 .num_resource = 4,
256 .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0,
257 RESASG_SUBTYPE_IR_OUTPUT),
258 .host_id = HOST_ID_A53_2,
259 },
260 {
261 .start_resource = 4,
262 .num_resource = 4,
263 .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0,
264 RESASG_SUBTYPE_IR_OUTPUT),
265 .host_id = HOST_ID_A53_3,
266 },
267 {
268 .start_resource = 8,
269 .num_resource = 4,
270 .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0,
271 RESASG_SUBTYPE_IR_OUTPUT),
272 .host_id = HOST_ID_R5_0,
273 },
274 {
275 .start_resource = 8,
276 .num_resource = 4,
277 .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0,
278 RESASG_SUBTYPE_IR_OUTPUT),
279 .host_id = HOST_ID_R5_1,
280 },
281 {
282 .start_resource = 12,
283 .num_resource = 4,
284 .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0,
285 RESASG_SUBTYPE_IR_OUTPUT),
286 .host_id = HOST_ID_R5_2,
287 },
288 /* Main NAVSS UDMA Interrupt aggregator Virtual interrupts */
289 {
290 .start_resource = 16,
291 .num_resource = 80,
292 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
293 RESASG_SUBTYPE_IA_VINT),
294 .host_id = HOST_ID_A53_2,
295 },
296 {
297 .start_resource = 96,
298 .num_resource = 30,
299 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
300 RESASG_SUBTYPE_IA_VINT),
301 .host_id = HOST_ID_A53_3,
302 },
303 {
304 .start_resource = 126,
305 .num_resource = 50,
306 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
307 RESASG_SUBTYPE_IA_VINT),
308 .host_id = HOST_ID_R5_0,
309 },
310 {
311 .start_resource = 126,
312 .num_resource = 50,
313 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
314 RESASG_SUBTYPE_IA_VINT),
315 .host_id = HOST_ID_R5_1,
316 },
317 {
318 .start_resource = 176,
319 .num_resource = 50,
320 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
321 RESASG_SUBTYPE_IA_VINT),
322 .host_id = HOST_ID_R5_2,
323 },
324 {
325 .start_resource = 226,
326 .num_resource = 30,
327 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
328 RESASG_SUBTYPE_IA_VINT),
329 .host_id = HOST_ID_ALL,
330 },
331 /* Main NAVSS UDMA Interrupt aggregator Global events */
332 {
333 .start_resource = 16,
334 .num_resource = 1024,
335 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
336 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
337 .host_id = HOST_ID_A53_2,
338 },
339 {
340 .start_resource = 1040,
341 .num_resource = 512,
342 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
343 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
344 .host_id = HOST_ID_A53_3,
345 },
346 {
347 .start_resource = 1552,
348 .num_resource = 512,
349 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
350 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
351 .host_id = HOST_ID_R5_0,
352 },
353 {
354 .start_resource = 1552,
355 .num_resource = 512,
356 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
357 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
358 .host_id = HOST_ID_R5_1,
359 },
360 {
361 .start_resource = 2064,
362 .num_resource = 512,
363 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
364 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
365 .host_id = HOST_ID_R5_2,
366 },
367 {
368 .start_resource = 2576,
369 .num_resource = 2032,
370 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0,
371 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
372 .host_id = HOST_ID_ALL,
373 },
374 /* MODSS Interrupt aggregator0 Virtual interrupts */
375 {
376 .start_resource = 0,
377 .num_resource = 64,
378 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA0,
379 RESASG_SUBTYPE_IA_VINT),
380 .host_id = HOST_ID_ALL,
381 },
382 /* MODSS Interrupt aggregator0 Global events */
383 {
384 .start_resource = 20480,
385 .num_resource = 1024,
386 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA0,
387 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
388 .host_id = HOST_ID_ALL,
389 },
390 /* MODSS Interrupt aggregator1 Virtual interrupts */
391 {
392 .start_resource = 0,
393 .num_resource = 64,
394 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA1,
395 RESASG_SUBTYPE_IA_VINT),
396 .host_id = HOST_ID_ALL,
397 },
398 /* MODSS Interrupt aggregator1 Global events */
399 {
400 .start_resource = 22528,
401 .num_resource = 1024,
402 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA1,
403 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
404 .host_id = HOST_ID_ALL,
405 },
406 /* Main NAVSS Interrupt Router */
407 {
408 .start_resource = 16,
409 .num_resource = 64,
410 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
411 RESASG_SUBTYPE_IR_OUTPUT),
412 .host_id = HOST_ID_A53_2,
413 },
414 {
415 .start_resource = 80,
416 .num_resource = 40,
417 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
418 RESASG_SUBTYPE_IR_OUTPUT),
419 .host_id = HOST_ID_A53_3,
420 },
421 {
422 .start_resource = 120,
423 .num_resource = 4,
424 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
425 RESASG_SUBTYPE_IR_OUTPUT),
426 .host_id = HOST_ID_R5_0,
427 },
428 {
429 .start_resource = 120,
430 .num_resource = 4,
431 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
432 RESASG_SUBTYPE_IR_OUTPUT),
433 .host_id = HOST_ID_R5_1,
434 },
435 {
436 .start_resource = 124,
437 .num_resource = 4,
438 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
439 RESASG_SUBTYPE_IR_OUTPUT),
440 .host_id = HOST_ID_R5_2,
441 },
442 {
443 .start_resource = 128,
444 .num_resource = 24,
445 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0,
446 RESASG_SUBTYPE_IR_OUTPUT),
447 .host_id = HOST_ID_ALL,
448 },
449 /* Main NAVSS Non secure proxies */
450 {
451 .start_resource = 1,
452 .num_resource = 12,
453 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
454 RESASG_SUBTYPE_PROXY_PROXIES),
455 .host_id = HOST_ID_A53_2,
456 },
457 {
458 .start_resource = 13,
459 .num_resource = 4,
460 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
461 RESASG_SUBTYPE_PROXY_PROXIES),
462 .host_id = HOST_ID_A53_3,
463 },
464 {
465 .start_resource = 17,
466 .num_resource = 16,
467 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
468 RESASG_SUBTYPE_PROXY_PROXIES),
469 .host_id = HOST_ID_R5_0,
470 },
471 {
472 .start_resource = 17,
473 .num_resource = 16,
474 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
475 RESASG_SUBTYPE_PROXY_PROXIES),
476 .host_id = HOST_ID_R5_1,
477 },
478 {
479 .start_resource = 33,
480 .num_resource = 16,
481 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
482 RESASG_SUBTYPE_PROXY_PROXIES),
483 .host_id = HOST_ID_R5_2,
484 },
485 {
486 .start_resource = 49,
487 .num_resource = 15,
488 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0,
489 RESASG_SUBTYPE_PROXY_PROXIES),
490 .host_id = HOST_ID_ALL,
491 },
492 /* Main NAVSS Ring accelerator Error event config */
493 {
494 .start_resource = 0,
495 .num_resource = 1,
496 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
497 RESASG_SUBTYPE_RA_ERROR_OES),
498 .host_id = HOST_ID_ALL,
499 },
500 /* Main NAVSS Ring accelerator Free rings */
501 {
502 .start_resource = 304,
503 .num_resource = 100,
504 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
505 RESASG_SUBTYPE_RA_GP),
506 .host_id = HOST_ID_A53_2,
507 },
508 {
509 .start_resource = 404,
510 .num_resource = 50,
511 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
512 RESASG_SUBTYPE_RA_GP),
513 .host_id = HOST_ID_A53_3,
514 },
515 {
516 .start_resource = 454,
517 .num_resource = 256,
518 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
519 RESASG_SUBTYPE_RA_GP),
520 .host_id = HOST_ID_R5_0,
521 },
522 {
523 .start_resource = 454,
524 .num_resource = 256,
525 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
526 RESASG_SUBTYPE_RA_GP),
527 .host_id = HOST_ID_R5_1,
528 },
529 {
530 .start_resource = 710,
531 .num_resource = 32,
532 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
533 RESASG_SUBTYPE_RA_GP),
534 .host_id = HOST_ID_R5_2,
535 },
536 {
537 .start_resource = 742,
538 .num_resource = 26,
539 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
540 RESASG_SUBTYPE_RA_GP),
541 .host_id = HOST_ID_ALL,
542 },
543 /* Main NAVSS Rings for Normal capacity Rx channels */
544 {
545 .start_resource = 160,
546 .num_resource = 12,
547 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
548 RESASG_SUBTYPE_RA_UDMAP_RX),
549 .host_id = HOST_ID_A53_2,
550 },
551 {
552 .start_resource = 172,
553 .num_resource = 4,
554 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
555 RESASG_SUBTYPE_RA_UDMAP_RX),
556 .host_id = HOST_ID_R5_0,
557 },
558 {
559 .start_resource = 172,
560 .num_resource = 4,
561 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
562 RESASG_SUBTYPE_RA_UDMAP_RX),
563 .host_id = HOST_ID_R5_1,
564 },
565 {
566 .start_resource = 172,
567 .num_resource = 0,
568 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
569 RESASG_SUBTYPE_RA_UDMAP_RX),
570 .host_id = HOST_ID_A53_3,
571 },
572 {
573 .start_resource = 176,
574 .num_resource = 2,
575 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
576 RESASG_SUBTYPE_RA_UDMAP_RX),
577 .host_id = HOST_ID_R5_2,
578 },
579 {
580 .start_resource = 178,
581 .num_resource = 52,
582 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
583 RESASG_SUBTYPE_RA_UDMAP_RX),
584 .host_id = HOST_ID_A53_2,
585 },
586 {
587 .start_resource = 230,
588 .num_resource = 8,
589 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
590 RESASG_SUBTYPE_RA_UDMAP_RX),
591 .host_id = HOST_ID_A53_3,
592 },
593 {
594 .start_resource = 238,
595 .num_resource = 32,
596 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
597 RESASG_SUBTYPE_RA_UDMAP_RX),
598 .host_id = HOST_ID_R5_0,
599 },
600 {
601 .start_resource = 238,
602 .num_resource = 32,
603 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
604 RESASG_SUBTYPE_RA_UDMAP_RX),
605 .host_id = HOST_ID_R5_1,
606 },
607 {
608 .start_resource = 270,
609 .num_resource = 14,
610 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
611 RESASG_SUBTYPE_RA_UDMAP_RX),
612 .host_id = HOST_ID_R5_2,
613 },
614 {
615 .start_resource = 284,
616 .num_resource = 18,
617 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
618 RESASG_SUBTYPE_RA_UDMAP_RX),
619 .host_id = HOST_ID_ALL,
620 },
621 /* Main NAVSS Rings for Normal capacity Tx channels */
622 {
623 .start_resource = 8,
624 .num_resource = 12,
625 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
626 RESASG_SUBTYPE_RA_UDMAP_TX),
627 .host_id = HOST_ID_A53_2,
628 },
629 {
630 .start_resource = 20,
631 .num_resource = 4,
632 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
633 RESASG_SUBTYPE_RA_UDMAP_TX),
634 .host_id = HOST_ID_R5_0,
635 },
636 {
637 .start_resource = 20,
638 .num_resource = 4,
639 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
640 RESASG_SUBTYPE_RA_UDMAP_TX),
641 .host_id = HOST_ID_R5_1,
642 },
643 {
644 .start_resource = 20,
645 .num_resource = 0,
646 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
647 RESASG_SUBTYPE_RA_UDMAP_TX),
648 .host_id = HOST_ID_A53_3,
649 },
650 {
651 .start_resource = 24,
652 .num_resource = 2,
653 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
654 RESASG_SUBTYPE_RA_UDMAP_TX),
655 .host_id = HOST_ID_R5_2,
656 },
657 {
658 .start_resource = 26,
659 .num_resource = 38,
660 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
661 RESASG_SUBTYPE_RA_UDMAP_TX),
662 .host_id = HOST_ID_A53_2,
663 },
664 {
665 .start_resource = 64,
666 .num_resource = 8,
667 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
668 RESASG_SUBTYPE_RA_UDMAP_TX),
669 .host_id = HOST_ID_A53_3,
670 },
671 {
672 .start_resource = 72,
673 .num_resource = 32,
674 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
675 RESASG_SUBTYPE_RA_UDMAP_TX),
676 .host_id = HOST_ID_R5_0,
677 },
678 {
679 .start_resource = 72,
680 .num_resource = 32,
681 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
682 RESASG_SUBTYPE_RA_UDMAP_TX),
683 .host_id = HOST_ID_R5_1,
684 },
685 {
686 .start_resource = 104,
687 .num_resource = 14,
688 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
689 RESASG_SUBTYPE_RA_UDMAP_TX),
690 .host_id = HOST_ID_R5_2,
691 },
692 {
693 .start_resource = 118,
694 .num_resource = 2,
695 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
696 RESASG_SUBTYPE_RA_UDMAP_TX),
697 .host_id = HOST_ID_ALL,
698 },
699 /* Main NAVSS Rings for extended Tx channels */
700 {
701 .start_resource = 120,
702 .num_resource = 4,
703 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
704 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
705 .host_id = HOST_ID_A53_2,
706 },
707 {
708 .start_resource = 124,
709 .num_resource = 4,
710 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
711 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
712 .host_id = HOST_ID_A53_3,
713 },
714 {
715 .start_resource = 128,
716 .num_resource = 12,
717 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
718 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
719 .host_id = HOST_ID_R5_0,
720 },
721 {
722 .start_resource = 128,
723 .num_resource = 12,
724 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
725 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
726 .host_id = HOST_ID_R5_1,
727 },
728 {
729 .start_resource = 140,
730 .num_resource = 12,
731 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
732 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
733 .host_id = HOST_ID_R5_2,
734 },
735 /* Main NAVSS Rings for High capacity Rx channels */
736 {
737 .start_resource = 154,
738 .num_resource = 0,
739 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
740 RESASG_SUBTYPE_RA_UDMAP_RX_H),
741 .host_id = HOST_ID_R5_0,
742 },
743 {
744 .start_resource = 154,
745 .num_resource = 0,
746 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
747 RESASG_SUBTYPE_RA_UDMAP_RX_H),
748 .host_id = HOST_ID_R5_1,
749 },
750 {
751 .start_resource = 154,
752 .num_resource = 0,
753 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
754 RESASG_SUBTYPE_RA_UDMAP_RX_H),
755 .host_id = HOST_ID_R5_2,
756 },
757 {
758 .start_resource = 154,
759 .num_resource = 0,
760 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
761 RESASG_SUBTYPE_RA_UDMAP_RX_H),
762 .host_id = HOST_ID_A53_2,
763 },
764 {
765 .start_resource = 154,
766 .num_resource = 2,
767 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
768 RESASG_SUBTYPE_RA_UDMAP_RX_H),
769 .host_id = HOST_ID_A53_2,
770 },
771 {
772 .start_resource = 156,
773 .num_resource = 2,
774 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
775 RESASG_SUBTYPE_RA_UDMAP_RX_H),
776 .host_id = HOST_ID_R5_0,
777 },
778 {
779 .start_resource = 156,
780 .num_resource = 2,
781 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
782 RESASG_SUBTYPE_RA_UDMAP_RX_H),
783 .host_id = HOST_ID_R5_1,
784 },
785 {
786 .start_resource = 158,
787 .num_resource = 2,
788 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
789 RESASG_SUBTYPE_RA_UDMAP_RX_H),
790 .host_id = HOST_ID_R5_2,
791 },
792 /* Main NAVSS Rings for High capacity Tx channels */
793 {
794 .start_resource = 1,
795 .num_resource = 0,
796 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
797 RESASG_SUBTYPE_RA_UDMAP_TX_H),
798 .host_id = HOST_ID_R5_0,
799 },
800 {
801 .start_resource = 1,
802 .num_resource = 0,
803 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
804 RESASG_SUBTYPE_RA_UDMAP_TX_H),
805 .host_id = HOST_ID_R5_1,
806 },
807 {
808 .start_resource = 1,
809 .num_resource = 0,
810 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
811 RESASG_SUBTYPE_RA_UDMAP_TX_H),
812 .host_id = HOST_ID_R5_2,
813 },
814 {
815 .start_resource = 1,
816 .num_resource = 0,
817 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
818 RESASG_SUBTYPE_RA_UDMAP_TX_H),
819 .host_id = HOST_ID_A53_2,
820 },
821 {
822 .start_resource = 1,
823 .num_resource = 3,
824 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
825 RESASG_SUBTYPE_RA_UDMAP_TX_H),
826 .host_id = HOST_ID_A53_2,
827 },
828 {
829 .start_resource = 4,
830 .num_resource = 2,
831 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
832 RESASG_SUBTYPE_RA_UDMAP_TX_H),
833 .host_id = HOST_ID_R5_0,
834 },
835 {
836 .start_resource = 4,
837 .num_resource = 2,
838 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
839 RESASG_SUBTYPE_RA_UDMAP_TX_H),
840 .host_id = HOST_ID_R5_1,
841 },
842 {
843 .start_resource = 6,
844 .num_resource = 2,
845 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
846 RESASG_SUBTYPE_RA_UDMAP_TX_H),
847 .host_id = HOST_ID_R5_2,
848 },
849 /* Main NAVSS Ring accelerator virt_id range */
850 {
851 .start_resource = 2,
852 .num_resource = 1,
853 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
854 RESASG_SUBTYPE_RA_VIRTID),
855 .host_id = HOST_ID_A53_2,
856 },
857 {
858 .start_resource = 3,
859 .num_resource = 1,
860 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
861 RESASG_SUBTYPE_RA_VIRTID),
862 .host_id = HOST_ID_A53_3,
863 },
864 /* Main NAVSS Ring monitors */
865 {
866 .start_resource = 0,
867 .num_resource = 8,
868 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
869 RESASG_SUBTYPE_RA_MONITORS),
870 .host_id = HOST_ID_A53_2,
871 },
872 {
873 .start_resource = 8,
874 .num_resource = 8,
875 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
876 RESASG_SUBTYPE_RA_MONITORS),
877 .host_id = HOST_ID_R5_0,
878 },
879 {
880 .start_resource = 8,
881 .num_resource = 8,
882 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
883 RESASG_SUBTYPE_RA_MONITORS),
884 .host_id = HOST_ID_R5_1,
885 },
886 {
887 .start_resource = 16,
888 .num_resource = 8,
889 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
890 RESASG_SUBTYPE_RA_MONITORS),
891 .host_id = HOST_ID_R5_2,
892 },
893 {
894 .start_resource = 24,
895 .num_resource = 8,
896 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0,
897 RESASG_SUBTYPE_RA_MONITORS),
898 .host_id = HOST_ID_ALL,
899 },
900 /* Main NAVSS UDMA Rx Free flows */
901 {
902 .start_resource = 150,
903 .num_resource = 64,
904 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
905 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
906 .host_id = HOST_ID_A53_2,
907 },
908 {
909 .start_resource = 214,
910 .num_resource = 8,
911 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
912 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
913 .host_id = HOST_ID_A53_3,
914 },
915 {
916 .start_resource = 222,
917 .num_resource = 64,
918 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
919 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
920 .host_id = HOST_ID_R5_0,
921 },
922 {
923 .start_resource = 222,
924 .num_resource = 64,
925 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
926 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
927 .host_id = HOST_ID_R5_1,
928 },
929 {
930 .start_resource = 286,
931 .num_resource = 8,
932 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
933 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
934 .host_id = HOST_ID_R5_2,
935 },
936 {
937 .start_resource = 294,
938 .num_resource = 6,
939 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
940 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
941 .host_id = HOST_ID_ALL,
942 },
943 /* Main NAVSS UDMA invalid flow event config */
944 {
945 .start_resource = 0,
946 .num_resource = 1,
947 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
948 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
949 .host_id = HOST_ID_ALL,
950 },
951 /* Main NAVSS UDMA global event trigger */
952 {
953 .start_resource = 49152,
954 .num_resource = 1024,
955 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
956 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
957 .host_id = HOST_ID_ALL,
958 },
959 /* Main NAVSS UDMA global config */
960 {
961 .start_resource = 0,
962 .num_resource = 1,
963 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
964 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
965 .host_id = HOST_ID_ALL,
966 },
967 /* Main NAVSS UDMA Normal capacity Rx channels */
968 {
969 .start_resource = 8,
970 .num_resource = 12,
971 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
972 RESASG_SUBTYPE_UDMAP_RX_CHAN),
973 .host_id = HOST_ID_A53_2,
974 },
975 {
976 .start_resource = 20,
977 .num_resource = 4,
978 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
979 RESASG_SUBTYPE_UDMAP_RX_CHAN),
980 .host_id = HOST_ID_R5_0,
981 },
982 {
983 .start_resource = 20,
984 .num_resource = 4,
985 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
986 RESASG_SUBTYPE_UDMAP_RX_CHAN),
987 .host_id = HOST_ID_R5_1,
988 },
989 {
990 .start_resource = 20,
991 .num_resource = 0,
992 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
993 RESASG_SUBTYPE_UDMAP_RX_CHAN),
994 .host_id = HOST_ID_A53_3,
995 },
996 {
997 .start_resource = 24,
998 .num_resource = 2,
999 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1000 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1001 .host_id = HOST_ID_R5_2,
1002 },
1003 {
1004 .start_resource = 26,
1005 .num_resource = 52,
1006 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1007 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1008 .host_id = HOST_ID_A53_2,
1009 },
1010 {
1011 .start_resource = 78,
1012 .num_resource = 8,
1013 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1014 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1015 .host_id = HOST_ID_A53_3,
1016 },
1017 {
1018 .start_resource = 86,
1019 .num_resource = 32,
1020 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1021 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1022 .host_id = HOST_ID_R5_0,
1023 },
1024 {
1025 .start_resource = 86,
1026 .num_resource = 32,
1027 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1028 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1029 .host_id = HOST_ID_R5_1,
1030 },
1031 {
1032 .start_resource = 118,
1033 .num_resource = 14,
1034 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1035 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1036 .host_id = HOST_ID_R5_2,
1037 },
1038 {
1039 .start_resource = 132,
1040 .num_resource = 18,
1041 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1042 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1043 .host_id = HOST_ID_ALL,
1044 },
1045 /* Main NAVSS UDMA High capacity Rx channels */
1046 {
1047 .start_resource = 2,
1048 .num_resource = 0,
1049 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1050 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1051 .host_id = HOST_ID_R5_0,
1052 },
1053 {
1054 .start_resource = 2,
1055 .num_resource = 0,
1056 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1057 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1058 .host_id = HOST_ID_R5_1,
1059 },
1060 {
1061 .start_resource = 2,
1062 .num_resource = 0,
1063 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1064 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1065 .host_id = HOST_ID_R5_2,
1066 },
1067 {
1068 .start_resource = 2,
1069 .num_resource = 0,
1070 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1071 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1072 .host_id = HOST_ID_A53_2,
1073 },
1074 {
1075 .start_resource = 2,
1076 .num_resource = 2,
1077 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1078 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1079 .host_id = HOST_ID_A53_2,
1080 },
1081 {
1082 .start_resource = 4,
1083 .num_resource = 2,
1084 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1085 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1086 .host_id = HOST_ID_R5_0,
1087 },
1088 {
1089 .start_resource = 4,
1090 .num_resource = 2,
1091 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1092 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1093 .host_id = HOST_ID_R5_1,
1094 },
1095 {
1096 .start_resource = 6,
1097 .num_resource = 2,
1098 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1099 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1100 .host_id = HOST_ID_R5_2,
1101 },
1102 /* Main NAVSS UDMA Normal capacity Tx channels */
1103 {
1104 .start_resource = 8,
1105 .num_resource = 12,
1106 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1107 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1108 .host_id = HOST_ID_A53_2,
1109 },
1110 {
1111 .start_resource = 20,
1112 .num_resource = 4,
1113 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1114 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1115 .host_id = HOST_ID_R5_0,
1116 },
1117 {
1118 .start_resource = 20,
1119 .num_resource = 4,
1120 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1121 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1122 .host_id = HOST_ID_R5_1,
1123 },
1124 {
1125 .start_resource = 20,
1126 .num_resource = 0,
1127 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1128 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1129 .host_id = HOST_ID_A53_3,
1130 },
1131 {
1132 .start_resource = 24,
1133 .num_resource = 2,
1134 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1135 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1136 .host_id = HOST_ID_R5_2,
1137 },
1138 {
1139 .start_resource = 26,
1140 .num_resource = 38,
1141 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1142 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1143 .host_id = HOST_ID_A53_2,
1144 },
1145 {
1146 .start_resource = 64,
1147 .num_resource = 8,
1148 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1149 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1150 .host_id = HOST_ID_A53_3,
1151 },
1152 {
1153 .start_resource = 72,
1154 .num_resource = 32,
1155 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1156 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1157 .host_id = HOST_ID_R5_0,
1158 },
1159 {
1160 .start_resource = 72,
1161 .num_resource = 32,
1162 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1163 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1164 .host_id = HOST_ID_R5_1,
1165 },
1166 {
1167 .start_resource = 104,
1168 .num_resource = 14,
1169 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1170 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1171 .host_id = HOST_ID_R5_2,
1172 },
1173 {
1174 .start_resource = 118,
1175 .num_resource = 2,
1176 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1177 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1178 .host_id = HOST_ID_ALL,
1179 },
1180 /* Main NAVSS UDMA extended Tx channels */
1181 {
1182 .start_resource = 120,
1183 .num_resource = 4,
1184 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1185 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1186 .host_id = HOST_ID_A53_2,
1187 },
1188 {
1189 .start_resource = 124,
1190 .num_resource = 4,
1191 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1192 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1193 .host_id = HOST_ID_A53_3,
1194 },
1195 {
1196 .start_resource = 128,
1197 .num_resource = 12,
1198 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1199 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1200 .host_id = HOST_ID_R5_0,
1201 },
1202 {
1203 .start_resource = 128,
1204 .num_resource = 12,
1205 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1206 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1207 .host_id = HOST_ID_R5_1,
1208 },
1209 {
1210 .start_resource = 140,
1211 .num_resource = 12,
1212 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1213 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1214 .host_id = HOST_ID_R5_2,
1215 },
1216 /* Main NAVSS UDMA High capacity Tx channels */
1217 {
1218 .start_resource = 1,
1219 .num_resource = 0,
1220 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1221 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1222 .host_id = HOST_ID_R5_0,
1223 },
1224 {
1225 .start_resource = 1,
1226 .num_resource = 0,
1227 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1228 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1229 .host_id = HOST_ID_R5_1,
1230 },
1231 {
1232 .start_resource = 1,
1233 .num_resource = 0,
1234 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1235 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1236 .host_id = HOST_ID_R5_2,
1237 },
1238 {
1239 .start_resource = 1,
1240 .num_resource = 0,
1241 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1242 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1243 .host_id = HOST_ID_A53_2,
1244 },
1245 {
1246 .start_resource = 1,
1247 .num_resource = 3,
1248 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1249 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1250 .host_id = HOST_ID_A53_2,
1251 },
1252 {
1253 .start_resource = 4,
1254 .num_resource = 2,
1255 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1256 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1257 .host_id = HOST_ID_R5_0,
1258 },
1259 {
1260 .start_resource = 4,
1261 .num_resource = 2,
1262 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1263 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1264 .host_id = HOST_ID_R5_1,
1265 },
1266 {
1267 .start_resource = 6,
1268 .num_resource = 2,
1269 .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0,
1270 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1271 .host_id = HOST_ID_R5_2,
1272 },
1273 /* MCU NAVSS Interrupt aggregator Virtual interrupts */
1274 {
1275 .start_resource = 8,
1276 .num_resource = 80,
1277 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1278 RESASG_SUBTYPE_IA_VINT),
1279 .host_id = HOST_ID_A53_2,
1280 },
1281 {
1282 .start_resource = 88,
1283 .num_resource = 30,
1284 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1285 RESASG_SUBTYPE_IA_VINT),
1286 .host_id = HOST_ID_A53_3,
1287 },
1288 {
1289 .start_resource = 118,
1290 .num_resource = 50,
1291 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1292 RESASG_SUBTYPE_IA_VINT),
1293 .host_id = HOST_ID_R5_0,
1294 },
1295 {
1296 .start_resource = 118,
1297 .num_resource = 50,
1298 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1299 RESASG_SUBTYPE_IA_VINT),
1300 .host_id = HOST_ID_R5_1,
1301 },
1302 {
1303 .start_resource = 168,
1304 .num_resource = 50,
1305 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1306 RESASG_SUBTYPE_IA_VINT),
1307 .host_id = HOST_ID_R5_2,
1308 },
1309 {
1310 .start_resource = 218,
1311 .num_resource = 38,
1312 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1313 RESASG_SUBTYPE_IA_VINT),
1314 .host_id = HOST_ID_ALL,
1315 },
1316 /* MCU NAVSS Interrupt aggregator Global events */
1317 {
1318 .start_resource = 16392,
1319 .num_resource = 512,
1320 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1321 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1322 .host_id = HOST_ID_A53_2,
1323 },
1324 {
1325 .start_resource = 16904,
1326 .num_resource = 128,
1327 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1328 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1329 .host_id = HOST_ID_A53_3,
1330 },
1331 {
1332 .start_resource = 17032,
1333 .num_resource = 256,
1334 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1335 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1336 .host_id = HOST_ID_R5_0,
1337 },
1338 {
1339 .start_resource = 17032,
1340 .num_resource = 256,
1341 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1342 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1343 .host_id = HOST_ID_R5_1,
1344 },
1345 {
1346 .start_resource = 17288,
1347 .num_resource = 256,
1348 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1349 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1350 .host_id = HOST_ID_R5_2,
1351 },
1352 {
1353 .start_resource = 17544,
1354 .num_resource = 376,
1355 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
1356 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1357 .host_id = HOST_ID_ALL,
1358 },
1359 /* MCU NAVSS Interrupt router */
1360 {
1361 .start_resource = 4,
1362 .num_resource = 28,
1363 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0,
1364 RESASG_SUBTYPE_IR_OUTPUT),
1365 .host_id = HOST_ID_R5_0,
1366 },
1367 {
1368 .start_resource = 4,
1369 .num_resource = 28,
1370 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0,
1371 RESASG_SUBTYPE_IR_OUTPUT),
1372 .host_id = HOST_ID_R5_1,
1373 },
1374 {
1375 .start_resource = 36,
1376 .num_resource = 28,
1377 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0,
1378 RESASG_SUBTYPE_IR_OUTPUT),
1379 .host_id = HOST_ID_R5_2,
1380 },
1381 /* MCU NAVSS Non secure proxies */
1382 {
1383 .start_resource = 0,
1384 .num_resource = 12,
1385 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0,
1386 RESASG_SUBTYPE_PROXY_PROXIES),
1387 .host_id = HOST_ID_A53_2,
1388 },
1389 {
1390 .start_resource = 12,
1391 .num_resource = 4,
1392 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0,
1393 RESASG_SUBTYPE_PROXY_PROXIES),
1394 .host_id = HOST_ID_A53_3,
1395 },
1396 {
1397 .start_resource = 16,
1398 .num_resource = 24,
1399 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0,
1400 RESASG_SUBTYPE_PROXY_PROXIES),
1401 .host_id = HOST_ID_R5_0,
1402 },
1403 {
1404 .start_resource = 16,
1405 .num_resource = 24,
1406 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0,
1407 RESASG_SUBTYPE_PROXY_PROXIES),
1408 .host_id = HOST_ID_R5_1,
1409 },
1410 {
1411 .start_resource = 40,
1412 .num_resource = 24,
1413 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0,
1414 RESASG_SUBTYPE_PROXY_PROXIES),
1415 .host_id = HOST_ID_R5_2,
1416 },
1417 /* MCU NAVSS UDMA Rx free flows */
1418 {
1419 .start_resource = 48,
1420 .num_resource = 16,
1421 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1422 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1423 .host_id = HOST_ID_A53_2,
1424 },
1425 {
1426 .start_resource = 64,
1427 .num_resource = 4,
1428 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1429 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1430 .host_id = HOST_ID_A53_3,
1431 },
1432 {
1433 .start_resource = 68,
1434 .num_resource = 16,
1435 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1436 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1437 .host_id = HOST_ID_R5_0,
1438 },
1439 {
1440 .start_resource = 68,
1441 .num_resource = 16,
1442 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1443 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1444 .host_id = HOST_ID_R5_1,
1445 },
1446 {
1447 .start_resource = 84,
1448 .num_resource = 8,
1449 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1450 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1451 .host_id = HOST_ID_R5_2,
1452 },
1453 {
1454 .start_resource = 92,
1455 .num_resource = 4,
1456 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1457 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1458 .host_id = HOST_ID_ALL,
1459 },
1460 /* MCU NAVSS invalid flow event config */
1461 {
1462 .start_resource = 0,
1463 .num_resource = 1,
1464 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1465 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
1466 .host_id = HOST_ID_ALL,
1467 },
1468 /* MCU NAVSS UDMA global event trigger */
1469 {
1470 .start_resource = 56320,
1471 .num_resource = 256,
1472 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1473 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
1474 .host_id = HOST_ID_ALL,
1475 },
1476 /* MCU NAVSS UDMA global config */
1477 {
1478 .start_resource = 0,
1479 .num_resource = 1,
1480 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1481 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
1482 .host_id = HOST_ID_ALL,
1483 },
1484 /* MCU NAVSS UDMA Normal capacity Rx channels */
1485 {
1486 .start_resource = 2,
1487 .num_resource = 2,
1488 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1489 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1490 .host_id = HOST_ID_A53_2,
1491 },
1492 {
1493 .start_resource = 4,
1494 .num_resource = 4,
1495 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1496 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1497 .host_id = HOST_ID_R5_0,
1498 },
1499 {
1500 .start_resource = 4,
1501 .num_resource = 4,
1502 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1503 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1504 .host_id = HOST_ID_R5_1,
1505 },
1506 {
1507 .start_resource = 4,
1508 .num_resource = 0,
1509 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1510 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1511 .host_id = HOST_ID_A53_3,
1512 },
1513 {
1514 .start_resource = 8,
1515 .num_resource = 2,
1516 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1517 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1518 .host_id = HOST_ID_R5_2,
1519 },
1520 {
1521 .start_resource = 10,
1522 .num_resource = 12,
1523 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1524 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1525 .host_id = HOST_ID_A53_2,
1526 },
1527 {
1528 .start_resource = 22,
1529 .num_resource = 4,
1530 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1531 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1532 .host_id = HOST_ID_A53_3,
1533 },
1534 {
1535 .start_resource = 26,
1536 .num_resource = 10,
1537 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1538 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1539 .host_id = HOST_ID_R5_0,
1540 },
1541 {
1542 .start_resource = 26,
1543 .num_resource = 10,
1544 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1545 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1546 .host_id = HOST_ID_R5_1,
1547 },
1548 {
1549 .start_resource = 36,
1550 .num_resource = 12,
1551 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1552 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1553 .host_id = HOST_ID_R5_2,
1554 },
1555 /* MCU NAVSS UDMA High capacity Rx channels */
1556 {
1557 .start_resource = 0,
1558 .num_resource = 0,
1559 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1560 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1561 .host_id = HOST_ID_R5_0,
1562 },
1563 {
1564 .start_resource = 0,
1565 .num_resource = 2,
1566 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1567 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1568 .host_id = HOST_ID_R5_0,
1569 },
1570 {
1571 .start_resource = 0,
1572 .num_resource = 0,
1573 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1574 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1575 .host_id = HOST_ID_R5_1,
1576 },
1577 {
1578 .start_resource = 0,
1579 .num_resource = 2,
1580 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1581 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1582 .host_id = HOST_ID_R5_1,
1583 },
1584 /* MCU NAVSS UDMA Normal capacity Tx channels */
1585 {
1586 .start_resource = 2,
1587 .num_resource = 2,
1588 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1589 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1590 .host_id = HOST_ID_A53_2,
1591 },
1592 {
1593 .start_resource = 4,
1594 .num_resource = 4,
1595 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1596 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1597 .host_id = HOST_ID_R5_0,
1598 },
1599 {
1600 .start_resource = 4,
1601 .num_resource = 4,
1602 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1603 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1604 .host_id = HOST_ID_R5_1,
1605 },
1606 {
1607 .start_resource = 4,
1608 .num_resource = 0,
1609 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1610 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1611 .host_id = HOST_ID_A53_3,
1612 },
1613 {
1614 .start_resource = 8,
1615 .num_resource = 2,
1616 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1617 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1618 .host_id = HOST_ID_R5_2,
1619 },
1620 {
1621 .start_resource = 10,
1622 .num_resource = 12,
1623 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1624 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1625 .host_id = HOST_ID_A53_2,
1626 },
1627 {
1628 .start_resource = 22,
1629 .num_resource = 4,
1630 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1631 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1632 .host_id = HOST_ID_A53_3,
1633 },
1634 {
1635 .start_resource = 26,
1636 .num_resource = 10,
1637 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1638 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1639 .host_id = HOST_ID_R5_0,
1640 },
1641 {
1642 .start_resource = 26,
1643 .num_resource = 10,
1644 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1645 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1646 .host_id = HOST_ID_R5_1,
1647 },
1648 {
1649 .start_resource = 36,
1650 .num_resource = 12,
1651 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1652 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1653 .host_id = HOST_ID_R5_2,
1654 },
1655 /* MCU NAVSS UDMA High capacity Tx channels */
1656 {
1657 .start_resource = 0,
1658 .num_resource = 0,
1659 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1660 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1661 .host_id = HOST_ID_R5_0,
1662 },
1663 {
1664 .start_resource = 0,
1665 .num_resource = 2,
1666 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1667 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1668 .host_id = HOST_ID_R5_0,
1669 },
1670 {
1671 .start_resource = 0,
1672 .num_resource = 0,
1673 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1674 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1675 .host_id = HOST_ID_R5_1,
1676 },
1677 {
1678 .start_resource = 0,
1679 .num_resource = 2,
1680 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0,
1681 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1682 .host_id = HOST_ID_R5_1,
1683 },
1684 /* MCU NAVSS Ring accelerator error event config */
1685 {
1686 .start_resource = 0,
1687 .num_resource = 1,
1688 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1689 RESASG_SUBTYPE_RA_ERROR_OES),
1690 .host_id = HOST_ID_ALL,
1691 },
1692 /* MCU NAVSS Ring accelerator Free rings */
1693 {
1694 .start_resource = 96,
1695 .num_resource = 32,
1696 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1697 RESASG_SUBTYPE_RA_GP),
1698 .host_id = HOST_ID_A53_2,
1699 },
1700 {
1701 .start_resource = 128,
1702 .num_resource = 8,
1703 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1704 RESASG_SUBTYPE_RA_GP),
1705 .host_id = HOST_ID_A53_3,
1706 },
1707 {
1708 .start_resource = 136,
1709 .num_resource = 60,
1710 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1711 RESASG_SUBTYPE_RA_GP),
1712 .host_id = HOST_ID_R5_0,
1713 },
1714 {
1715 .start_resource = 136,
1716 .num_resource = 60,
1717 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1718 RESASG_SUBTYPE_RA_GP),
1719 .host_id = HOST_ID_R5_1,
1720 },
1721 {
1722 .start_resource = 196,
1723 .num_resource = 60,
1724 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1725 RESASG_SUBTYPE_RA_GP),
1726 .host_id = HOST_ID_R5_2,
1727 },
1728 /* MCU NAVSS Rings for Normal capacity Rx channels */
1729 {
1730 .start_resource = 50,
1731 .num_resource = 2,
1732 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1733 RESASG_SUBTYPE_RA_UDMAP_RX),
1734 .host_id = HOST_ID_A53_2,
1735 },
1736 {
1737 .start_resource = 52,
1738 .num_resource = 4,
1739 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1740 RESASG_SUBTYPE_RA_UDMAP_RX),
1741 .host_id = HOST_ID_R5_0,
1742 },
1743 {
1744 .start_resource = 52,
1745 .num_resource = 4,
1746 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1747 RESASG_SUBTYPE_RA_UDMAP_RX),
1748 .host_id = HOST_ID_R5_1,
1749 },
1750 {
1751 .start_resource = 52,
1752 .num_resource = 0,
1753 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1754 RESASG_SUBTYPE_RA_UDMAP_RX),
1755 .host_id = HOST_ID_A53_3,
1756 },
1757 {
1758 .start_resource = 56,
1759 .num_resource = 2,
1760 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1761 RESASG_SUBTYPE_RA_UDMAP_RX),
1762 .host_id = HOST_ID_R5_2,
1763 },
1764 {
1765 .start_resource = 58,
1766 .num_resource = 12,
1767 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1768 RESASG_SUBTYPE_RA_UDMAP_RX),
1769 .host_id = HOST_ID_A53_2,
1770 },
1771 {
1772 .start_resource = 70,
1773 .num_resource = 4,
1774 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1775 RESASG_SUBTYPE_RA_UDMAP_RX),
1776 .host_id = HOST_ID_A53_3,
1777 },
1778 {
1779 .start_resource = 74,
1780 .num_resource = 10,
1781 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1782 RESASG_SUBTYPE_RA_UDMAP_RX),
1783 .host_id = HOST_ID_R5_0,
1784 },
1785 {
1786 .start_resource = 74,
1787 .num_resource = 10,
1788 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1789 RESASG_SUBTYPE_RA_UDMAP_RX),
1790 .host_id = HOST_ID_R5_1,
1791 },
1792 {
1793 .start_resource = 84,
1794 .num_resource = 12,
1795 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1796 RESASG_SUBTYPE_RA_UDMAP_RX),
1797 .host_id = HOST_ID_R5_2,
1798 },
1799 /* MCU NAVSS Rings for Normal capacity Tx channels */
1800 {
1801 .start_resource = 2,
1802 .num_resource = 2,
1803 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1804 RESASG_SUBTYPE_RA_UDMAP_TX),
1805 .host_id = HOST_ID_A53_2,
1806 },
1807 {
1808 .start_resource = 4,
1809 .num_resource = 4,
1810 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1811 RESASG_SUBTYPE_RA_UDMAP_TX),
1812 .host_id = HOST_ID_R5_0,
1813 },
1814 {
1815 .start_resource = 4,
1816 .num_resource = 4,
1817 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1818 RESASG_SUBTYPE_RA_UDMAP_TX),
1819 .host_id = HOST_ID_R5_1,
1820 },
1821 {
1822 .start_resource = 4,
1823 .num_resource = 0,
1824 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1825 RESASG_SUBTYPE_RA_UDMAP_TX),
1826 .host_id = HOST_ID_A53_3,
1827 },
1828 {
1829 .start_resource = 8,
1830 .num_resource = 2,
1831 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1832 RESASG_SUBTYPE_RA_UDMAP_TX),
1833 .host_id = HOST_ID_R5_2,
1834 },
1835 {
1836 .start_resource = 10,
1837 .num_resource = 12,
1838 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1839 RESASG_SUBTYPE_RA_UDMAP_TX),
1840 .host_id = HOST_ID_A53_2,
1841 },
1842 {
1843 .start_resource = 22,
1844 .num_resource = 4,
1845 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1846 RESASG_SUBTYPE_RA_UDMAP_TX),
1847 .host_id = HOST_ID_A53_3,
1848 },
1849 {
1850 .start_resource = 26,
1851 .num_resource = 10,
1852 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1853 RESASG_SUBTYPE_RA_UDMAP_TX),
1854 .host_id = HOST_ID_R5_0,
1855 },
1856 {
1857 .start_resource = 26,
1858 .num_resource = 10,
1859 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1860 RESASG_SUBTYPE_RA_UDMAP_TX),
1861 .host_id = HOST_ID_R5_1,
1862 },
1863 {
1864 .start_resource = 36,
1865 .num_resource = 12,
1866 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1867 RESASG_SUBTYPE_RA_UDMAP_TX),
1868 .host_id = HOST_ID_R5_2,
1869 },
1870 /* MCU NAVSS Rings for High capacity Rx channels */
1871 {
1872 .start_resource = 48,
1873 .num_resource = 0,
1874 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1875 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1876 .host_id = HOST_ID_R5_0,
1877 },
1878 {
1879 .start_resource = 48,
1880 .num_resource = 2,
1881 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1882 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1883 .host_id = HOST_ID_R5_0,
1884 },
1885 {
1886 .start_resource = 48,
1887 .num_resource = 0,
1888 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1889 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1890 .host_id = HOST_ID_R5_1,
1891 },
1892 {
1893 .start_resource = 48,
1894 .num_resource = 2,
1895 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1896 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1897 .host_id = HOST_ID_R5_1,
1898 },
1899 /* MCU NAVSS Rings for High capacity Tx channels */
1900 {
1901 .start_resource = 0,
1902 .num_resource = 0,
1903 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1904 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1905 .host_id = HOST_ID_R5_0,
1906 },
1907 {
1908 .start_resource = 0,
1909 .num_resource = 2,
1910 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1911 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1912 .host_id = HOST_ID_R5_0,
1913 },
1914 {
1915 .start_resource = 0,
1916 .num_resource = 0,
1917 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1918 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1919 .host_id = HOST_ID_R5_1,
1920 },
1921 {
1922 .start_resource = 0,
1923 .num_resource = 2,
1924 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1925 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1926 .host_id = HOST_ID_R5_1,
1927 },
1928 /* MCU NAVSS Ring accelerator virt_id range */
1929 {
1930 .start_resource = 2,
1931 .num_resource = 1,
1932 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1933 RESASG_SUBTYPE_RA_VIRTID),
1934 .host_id = HOST_ID_A53_2,
1935 },
1936 {
1937 .start_resource = 3,
1938 .num_resource = 1,
1939 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1940 RESASG_SUBTYPE_RA_VIRTID),
1941 .host_id = HOST_ID_A53_3,
1942 },
1943 /* MCU NAVSS Ring monitors */
1944 {
1945 .start_resource = 0,
1946 .num_resource = 8,
1947 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1948 RESASG_SUBTYPE_RA_MONITORS),
1949 .host_id = HOST_ID_A53_2,
1950 },
1951 {
1952 .start_resource = 8,
1953 .num_resource = 8,
1954 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1955 RESASG_SUBTYPE_RA_MONITORS),
1956 .host_id = HOST_ID_R5_0,
1957 },
1958 {
1959 .start_resource = 8,
1960 .num_resource = 8,
1961 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1962 RESASG_SUBTYPE_RA_MONITORS),
1963 .host_id = HOST_ID_R5_1,
1964 },
1965 {
1966 .start_resource = 16,
1967 .num_resource = 8,
1968 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1969 RESASG_SUBTYPE_RA_MONITORS),
1970 .host_id = HOST_ID_R5_2,
1971 },
1972 {
1973 .start_resource = 24,
1974 .num_resource = 8,
1975 .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0,
1976 RESASG_SUBTYPE_RA_MONITORS),
1977 .host_id = HOST_ID_ALL,
1978 },
1979 },
1980};
diff --git a/soc/am65x_sr2/evm/sec-cfg.c b/soc/am65x_sr2/evm/sec-cfg.c
deleted file mode 100644
index f51d5bbe9..000000000
--- a/soc/am65x_sr2/evm/sec-cfg.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * K3 System Firmware Security Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_security am65_boardcfg_security_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_proc_acl */
45 .processor_acl_list = {
46 .subhdr = {
47 .magic = BOARDCFG_PROC_ACL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_proc_acl),
49 },
50 .proc_acl_entries = {{ 0 } },
51 },
52
53 /* boardcfg_host_hierarchy */
54 .host_hierarchy = {
55 .subhdr = {
56 .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
57 .size = sizeof(struct boardcfg_host_hierarchy),
58 },
59 .host_hierarchy_entries = {{ 0 } },
60 },
61
62 /* OTP access configuration */
63 .otp_config = {
64 .subhdr = {
65 .magic = BOARDCFG_OTP_CFG_MAGIC_NUM,
66 .size = sizeof(struct boardcfg_extended_otp),
67 },
68 /* Host ID 0 is DMSC. This means no host has write access to OTP array */
69 .write_host_id = 0,
70 /* This is an array with 32 entries */
71 .otp_entry = {{ 0 } },
72 },
73
74 /* DKEK configuration */
75 .dkek_config = {
76 .subhdr = {
77 .magic = BOARDCFG_DKEK_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dkek),
79 },
80 .allowed_hosts = { HOST_ID_ALL, 0, 0, 0 },
81 .allow_dkek_export_tisci = 0x5A,
82 .rsvd = {0, 0, 0},
83 },
84
85 /* SA2UL configuration */
86 .sa2ul_cfg = {
87 .subhdr = {
88 .magic = BOARDCFG_SA2UL_CFG_MAGIC_NUM_RSVD,
89 .size = 0,
90 },
91 .rsvd = {0, 0, 0, 0},
92 },
93
94 /* Secure JTAG Unlock Configuration */
95 .sec_dbg_config = {
96 .subhdr = {
97 .magic = BOARDCFG_SEC_DBG_CTRL_MAGIC_NUM,
98 .size = sizeof(struct boardcfg_secure_debug_config),
99 },
100 .allow_jtag_unlock = 0x5A,
101 .allow_wildcard_unlock = 0x5A,
102 .min_cert_rev = 0x0,
103 .jtag_unlock_hosts = {0, 0, 0, 0},
104 },
105
106 /* Secure Handover Configuration */
107 .sec_handover_cfg = {
108 .subhdr = {
109 .magic = BOARDCFG_SEC_HANDOVER_CFG_MAGIC_NUM,
110 .size = sizeof(struct boardcfg_sec_handover),
111 },
112 .handover_msg_sender = 0,
113 .handover_to_host_id = 0,
114 .rsvd = {0,0,0,0},
115 },
116};
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h
deleted file mode 100644
index b27ad73b9..000000000
--- a/soc/am65x_sr2/evm/sysfw_img_cfg.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * K3 System Firmware Resource Management Board Config Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 *
6 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H
39
40#define BOARDCFG_RM_RESASG_ENTRIES 260
41
42#endif /* SYSFW_IMG_CFG_H */
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