aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSuman Anna2020-05-04 16:08:41 -0500
committerDave Gerlach2020-05-05 13:15:15 -0500
commit6408ecb8c790cbec0aa41e93565d5e3d4cbe5776 (patch)
treeb0e22d10ce97904932dd43eb917ea2819484e91b /soc/am65x_sr2
parent8cfe64e7ca5729b0fbb4930bc2fed66ddf19049f (diff)
downloadk3-image-gen-6408ecb8c790cbec0aa41e93565d5e3d4cbe5776.tar.gz
k3-image-gen-6408ecb8c790cbec0aa41e93565d5e3d4cbe5776.tar.xz
k3-image-gen-6408ecb8c790cbec0aa41e93565d5e3d4cbe5776.zip
am65x,am65x_sr2: rm-cfg: Fix Main NavSS IR outputs after ABI 3.0
The Main NavSS IR on AM65x SoCs has a total of 152 output interrupt lines, out of which the first 16 are reserved for System Firmware. The ABI 3.0 resource updates have assigned all the remaining IR output lines to the A53 host context HOST_ID_A53_2, which is wrong. The Main NavSS IR also supports some interrupt lines for the MCU R5F cores (connected through MAIN2MCU LVL IR) and for each of the 3 ICSSG subsystems. Fix up the Main NavSS IR outputs properly by adding resources for each of the processor subsystems. The output lines [120:127] are split equally for each of the MCU R5F cores (to support Split-mode), leaving only 104 usable interrupts for the A53 core. The output lines [128:151] are associated with the ICSSG subsystems. Signed-off-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'soc/am65x_sr2')
-rw-r--r--soc/am65x_sr2/evm/rm-cfg.c34
-rw-r--r--soc/am65x_sr2/evm/sysfw_img_cfg.h2
2 files changed, 33 insertions, 3 deletions
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c
index 1894ac1c1..5abb3c31c 100644
--- a/soc/am65x_sr2/evm/rm-cfg.c
+++ b/soc/am65x_sr2/evm/rm-cfg.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * 3 *
4 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com> 5 * Andreas Dannenberg <dannenberg@ti.com>
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
@@ -400,10 +400,40 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = {
400 { 400 {
401 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), 401 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
402 .start_resource = 16, 402 .start_resource = 16,
403 .num_resource = 136, 403 .num_resource = 104,
404 .host_id = HOST_ID_A53_2, 404 .host_id = HOST_ID_A53_2,
405 }, 405 },
406 { 406 {
407 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
408 .start_resource = 120,
409 .num_resource = 4,
410 .host_id = HOST_ID_R5_0,
411 },
412 {
413 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
414 .start_resource = 124,
415 .num_resource = 4,
416 .host_id = HOST_ID_R5_2,
417 },
418 {
419 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
420 .start_resource = 128,
421 .num_resource = 8,
422 .host_id = HOST_ID_ICSSG_0,
423 },
424 {
425 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
426 .start_resource = 136,
427 .num_resource = 8,
428 .host_id = HOST_ID_ICSSG_1,
429 },
430 {
431 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
432 .start_resource = 144,
433 .num_resource = 8,
434 .host_id = HOST_ID_ICSSG_2,
435 },
436 {
407 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), 437 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
408 .start_resource = 4, 438 .start_resource = 4,
409 .num_resource = 28, 439 .num_resource = 28,
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h
index a69f6c6d3..f1a01f8ea 100644
--- a/soc/am65x_sr2/evm/sysfw_img_cfg.h
+++ b/soc/am65x_sr2/evm/sysfw_img_cfg.h
@@ -35,6 +35,6 @@
35#ifndef SYSFW_IMG_CFG_H 35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 36#define SYSFW_IMG_CFG_H
37 37
38#define BOARDCFG_RM_RESASG_ENTRIES 50 38#define BOARDCFG_RM_RESASG_ENTRIES 55
39 39
40#endif /* SYSFW_IMG_CFG_H */ 40#endif /* SYSFW_IMG_CFG_H */