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authorDave Gerlach2020-03-24 22:44:30 -0500
committerDave Gerlach2020-03-26 19:54:51 -0500
commit721ebec2a3d1f93248ce5f1660f35b50dd31780c (patch)
tree0ccbf2eb7f78fa70cb7ce67411342197153ac3a2 /soc/am65x_sr2
parentca0b17080a239e6eb69f7b36de6cfd36ddc67b4d (diff)
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soc: am65x_sr2: Introduce support for evm
Add support for AM65x SR2 SoCs which have slightly different board configuration requirements than AM65x and also require a specific firmware image. Also update the SYSFW_GIT_HASH to point to the latest ti-linux-firmware repo which contains v2019.12b SR2 binary. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'soc/am65x_sr2')
-rw-r--r--soc/am65x_sr2/evm/board-cfg.c92
-rw-r--r--soc/am65x_sr2/evm/pm-cfg.c43
-rw-r--r--soc/am65x_sr2/evm/rm-cfg.c460
-rw-r--r--soc/am65x_sr2/evm/sec-cfg.c73
-rw-r--r--soc/am65x_sr2/evm/sysfw_img_cfg.h40
5 files changed, 708 insertions, 0 deletions
diff --git a/soc/am65x_sr2/evm/board-cfg.c b/soc/am65x_sr2/evm/board-cfg.c
new file mode 100644
index 000000000..fe3381222
--- /dev/null
+++ b/soc/am65x_sr2/evm/board-cfg.c
@@ -0,0 +1,92 @@
1/*
2 * K3 System Firmware Board Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg am65_boardcfg_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_control */
45 .control = {
46 .subhdr = {
47 .magic = BOARDCFG_CONTROL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_control),
49 },
50 .main_isolation_enable = 0x5A,
51 .main_isolation_hostid = 0x2,
52 },
53
54 /* boardcfg sec_proxy */
55 .secproxy = {
56 .subhdr = {
57 .magic = BOARDCFG_SECPROXY_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_secproxy),
59 },
60 .scaling_factor = 0x1,
61 .scaling_profile = 0x1,
62 .disable_main_nav_secure_proxy = 0,
63 },
64
65 /* boardcfg_msmc */
66 .msmc = {
67 .subhdr = {
68 .magic = BOARDCFG_MSMC_MAGIC_NUM,
69 .size = sizeof(struct boardcfg_msmc),
70 },
71 .msmc_cache_size = 0x10,
72 },
73
74 /* boardcfg_dbg_cfg */
75 .debug_cfg = {
76 .subhdr = {
77 .magic = BOARDCFG_DBG_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dbg_cfg),
79 },
80#ifdef ENABLE_TRACE
81 .trace_dst_enables = BOARDCFG_TRACE_DST_UART0 |
82 BOARDCFG_TRACE_DST_ITM |
83 BOARDCFG_TRACE_DST_MEM,
84 .trace_src_enables = BOARDCFG_TRACE_SRC_PM |
85 BOARDCFG_TRACE_SRC_RM |
86 BOARDCFG_TRACE_SRC_SEC |
87 BOARDCFG_TRACE_SRC_BASE |
88 BOARDCFG_TRACE_SRC_USER |
89 BOARDCFG_TRACE_SRC_SUPR,
90#endif
91 },
92};
diff --git a/soc/am65x_sr2/evm/pm-cfg.c b/soc/am65x_sr2/evm/pm-cfg.c
new file mode 100644
index 000000000..ff3efbd07
--- /dev/null
+++ b/soc/am65x_sr2/evm/pm-cfg.c
@@ -0,0 +1,43 @@
1/*
2 * K3 System Firmware Power Management Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_pm am65_boardcfg_pm_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43};
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c
new file mode 100644
index 000000000..71927b30c
--- /dev/null
+++ b/soc/am65x_sr2/evm/rm-cfg.c
@@ -0,0 +1,460 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_rm_local am65_boardcfg_rm_data = {
38 .rm_boardcfg = {
39 /* boardcfg_abi_rev */
40 .rev = {
41 .boardcfg_abi_maj = 0x0,
42 .boardcfg_abi_min = 0x1,
43 },
44
45 /* boardcfg_rm_host_cfg */
46 .host_cfg = {
47 .subhdr = {
48 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
49 .size = sizeof(struct boardcfg_rm_host_cfg),
50 },
51 .host_cfg_entries = {{ 0 } },
52 },
53
54 /* boardcfg_rm_resasg */
55 .resasg = {
56 .subhdr = {
57 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_rm_resasg),
59 },
60 .resasg_entries_size = BOARDCFG_RM_RESASG_ENTRIES *
61 sizeof(struct boardcfg_rm_resasg_entry),
62 .reserved = 0,
63 /* .resasg_entries is set via boardcfg_rm_local */
64 },
65 },
66
67 /* This is actually part of .resasg */
68 .resasg_entries = {
69 {
70 .start_resource = 16,
71 .num_resource = 240,
72 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_IA_VINT),
73 .host_id = HOST_ID_A53_2,
74 },
75 {
76 .start_resource = 16,
77 .num_resource = 4592,
78 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
79 .host_id = HOST_ID_A53_2,
80 },
81 {
82 .start_resource = 0,
83 .num_resource = 64,
84 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_IA_VINT),
85 .host_id = HOST_ID_A53_2,
86 },
87 {
88 .start_resource = 20480,
89 .num_resource = 1024,
90 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
91 .host_id = HOST_ID_A53_2,
92 },
93 {
94 .start_resource = 0,
95 .num_resource = 64,
96 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_IA_VINT),
97 .host_id = HOST_ID_A53_2,
98 },
99 {
100 .start_resource = 22528,
101 .num_resource = 1024,
102 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
103 .host_id = HOST_ID_A53_2,
104 },
105 {
106 .start_resource = 8,
107 .num_resource = 248,
108 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_IA_VINT),
109 .host_id = HOST_ID_R5_0,
110 },
111 {
112 .start_resource = 16392,
113 .num_resource = 992,
114 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
115 .host_id = HOST_ID_R5_0,
116 },
117 {
118 .start_resource = 17384,
119 .num_resource = 536,
120 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
121 .host_id = HOST_ID_R5_0,
122 },
123 {
124 .start_resource = 49152,
125 .num_resource = 1024,
126 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
127 .host_id = HOST_ID_A53_2,
128 },
129 {
130 .start_resource = 1,
131 .num_resource = 7,
132 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN),
133 .host_id = HOST_ID_A53_2,
134 },
135 {
136 .start_resource = 8,
137 .num_resource = 112,
138 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
139 .host_id = HOST_ID_A53_2,
140 },
141 {
142 .start_resource = 120,
143 .num_resource = 32,
144 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_ECHAN),
145 .host_id = HOST_ID_A53_2,
146 },
147 {
148 .start_resource = 2,
149 .num_resource = 6,
150 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
151 .host_id = HOST_ID_A53_2,
152 },
153 {
154 .start_resource = 8,
155 .num_resource = 142,
156 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
157 .host_id = HOST_ID_A53_2,
158 },
159 {
160 .start_resource = 150,
161 .num_resource = 150,
162 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
163 .host_id = HOST_ID_A53_2,
164 },
165 {
166 .start_resource = 0,
167 .num_resource = 1,
168 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
169 .host_id = HOST_ID_A53_2,
170 },
171 {
172 .start_resource = 56320,
173 .num_resource = 256,
174 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
175 .host_id = HOST_ID_A53_2,
176 },
177 {
178 .start_resource = 0,
179 .num_resource = 2,
180 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN),
181 .host_id = HOST_ID_A53_2,
182 },
183 {
184 .start_resource = 2,
185 .num_resource = 46,
186 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
187 .host_id = HOST_ID_A53_2,
188 },
189 {
190 .start_resource = 0,
191 .num_resource = 2,
192 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
193 .host_id = HOST_ID_A53_2,
194 },
195 {
196 .start_resource = 2,
197 .num_resource = 46,
198 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
199 .host_id = HOST_ID_A53_2,
200 },
201 {
202 .start_resource = 48,
203 .num_resource = 48,
204 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
205 .host_id = HOST_ID_A53_2,
206 },
207 {
208 .start_resource = 2,
209 .num_resource = 46,
210 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
211 .host_id = HOST_ID_R5_1,
212 },
213 {
214 .start_resource = 2,
215 .num_resource = 46,
216 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
217 .host_id = HOST_ID_R5_1,
218 },
219 {
220 .start_resource = 48,
221 .num_resource = 48,
222 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
223 .host_id = HOST_ID_R5_1,
224 },
225 {
226 .start_resource = 0,
227 .num_resource = 1,
228 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
229 .host_id = HOST_ID_A53_2,
230 },
231 {
232 .start_resource = 1,
233 .num_resource = 7,
234 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
235 .host_id = HOST_ID_A53_2,
236 },
237 {
238 .start_resource = 8,
239 .num_resource = 112,
240 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
241 .host_id = HOST_ID_A53_2,
242 },
243 {
244 .start_resource = 120,
245 .num_resource = 32,
246 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
247 .host_id = HOST_ID_A53_2,
248 },
249 {
250 .start_resource = 153,
251 .num_resource = 7,
252 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
253 .host_id = HOST_ID_A53_2,
254 },
255 {
256 .start_resource = 160,
257 .num_resource = 142,
258 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
259 .host_id = HOST_ID_A53_2,
260 },
261 {
262 .start_resource = 304,
263 .num_resource = 464,
264 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
265 .host_id = HOST_ID_A53_2,
266 },
267 {
268 .start_resource = 0,
269 .num_resource = 1,
270 .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES),
271 .host_id = HOST_ID_A53_2,
272 },
273 {
274 .start_resource = 0,
275 .num_resource = 2,
276 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
277 .host_id = HOST_ID_A53_2,
278 },
279 {
280 .start_resource = 2,
281 .num_resource = 46,
282 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
283 .host_id = HOST_ID_A53_2,
284 },
285 {
286 .start_resource = 48,
287 .num_resource = 2,
288 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
289 .host_id = HOST_ID_A53_2,
290 },
291 {
292 .start_resource = 50,
293 .num_resource = 46,
294 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
295 .host_id = HOST_ID_A53_2,
296 },
297 {
298 .start_resource = 96,
299 .num_resource = 160,
300 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
301 .host_id = HOST_ID_A53_2,
302 },
303 {
304 .start_resource = 0,
305 .num_resource = 2,
306 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
307 .host_id = HOST_ID_R5_1,
308 },
309 {
310 .start_resource = 2,
311 .num_resource = 46,
312 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
313 .host_id = HOST_ID_R5_1,
314 },
315 {
316 .start_resource = 48,
317 .num_resource = 2,
318 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
319 .host_id = HOST_ID_R5_1,
320 },
321 {
322 .start_resource = 50,
323 .num_resource = 46,
324 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
325 .host_id = HOST_ID_R5_1,
326 },
327 {
328 .start_resource = 96,
329 .num_resource = 160,
330 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
331 .host_id = HOST_ID_R5_1,
332 },
333 {
334 .start_resource = 0,
335 .num_resource = 1,
336 .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES),
337 .host_id = HOST_ID_A53_2,
338 },
339 {
340 .start_resource = 80,
341 .num_resource = 48,
342 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
343 .host_id = HOST_ID_A53_2,
344 },
345 {
346 .start_resource = 392,
347 .num_resource = 32,
348 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
349 .host_id = HOST_ID_A53_2,
350 },
351 {
352 .start_resource = 448,
353 .num_resource = 50,
354 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
355 .host_id = HOST_ID_A53_2,
356 },
357 {
358 .start_resource = 498,
359 .num_resource = 6,
360 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
361 .host_id = HOST_ID_A53_2,
362 },
363 {
364 .start_resource = 544,
365 .num_resource = 16,
366 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0),
367 .host_id = HOST_ID_A53_2,
368 },
369 {
370 .start_resource = 712,
371 .num_resource = 16,
372 .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
373 .host_id = HOST_ID_A53_2,
374 },
375 {
376 .start_resource = 68,
377 .num_resource = 28,
378 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
379 .host_id = HOST_ID_R5_0,
380 },
381 {
382 .start_resource = 124,
383 .num_resource = 16,
384 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
385 .host_id = HOST_ID_R5_0,
386 },
387 {
388 .start_resource = 160,
389 .num_resource = 32,
390 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
391 .host_id = HOST_ID_R5_0,
392 },
393 {
394 .start_resource = 224,
395 .num_resource = 48,
396 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
397 .host_id = HOST_ID_R5_0,
398 },
399 {
400 .start_resource = 68,
401 .num_resource = 28,
402 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
403 .host_id = HOST_ID_R5_0,
404 },
405 {
406 .start_resource = 124,
407 .num_resource = 16,
408 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
409 .host_id = HOST_ID_R5_0,
410 },
411 {
412 .start_resource = 192,
413 .num_resource = 32,
414 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
415 .host_id = HOST_ID_R5_2,
416 },
417 {
418 .start_resource = 224,
419 .num_resource = 48,
420 .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
421 .host_id = HOST_ID_R5_0,
422 },
423 {
424 .start_resource = 46,
425 .num_resource = 8,
426 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
427 .host_id = HOST_ID_ICSSG_0,
428 },
429 {
430 .start_resource = 88,
431 .num_resource = 8,
432 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
433 .host_id = HOST_ID_ICSSG_0,
434 },
435 {
436 .start_resource = 46,
437 .num_resource = 8,
438 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
439 .host_id = HOST_ID_ICSSG_1,
440 },
441 {
442 .start_resource = 88,
443 .num_resource = 8,
444 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
445 .host_id = HOST_ID_ICSSG_1,
446 },
447 {
448 .start_resource = 46,
449 .num_resource = 8,
450 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
451 .host_id = HOST_ID_ICSSG_2,
452 },
453 {
454 .start_resource = 88,
455 .num_resource = 8,
456 .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
457 .host_id = HOST_ID_ICSSG_2,
458 },
459 },
460};
diff --git a/soc/am65x_sr2/evm/sec-cfg.c b/soc/am65x_sr2/evm/sec-cfg.c
new file mode 100644
index 000000000..ea7007664
--- /dev/null
+++ b/soc/am65x_sr2/evm/sec-cfg.c
@@ -0,0 +1,73 @@
1/*
2 * K3 System Firmware Security Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_security am65_boardcfg_security_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_proc_acl */
45 .processor_acl_list = {
46 .subhdr = {
47 .magic = BOARDCFG_PROC_ACL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_proc_acl),
49 },
50 .proc_acl_entries = {{ 0 } },
51 },
52
53 /* boardcfg_host_hierarchy */
54 .host_hierarchy = {
55 .subhdr = {
56 .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
57 .size = sizeof(struct boardcfg_host_hierarchy),
58 },
59 .host_hierarchy_entries = {{ 0 } },
60 },
61
62 /* OTP access configuration */
63 .otp_config = {
64 .subhdr = {
65 .magic = BOARDCFG_OTP_CFG_MAGIC_NUM,
66 .size = sizeof(struct boardcfg_extended_otp),
67 },
68 /* Host ID 0 is DMSC. This means no host has write access to OTP array */
69 .write_host_id = 0,
70 /* This is an array with 32 entries */
71 .otp_entry = {{ 0 } },
72 },
73};
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h
new file mode 100644
index 000000000..204369441
--- /dev/null
+++ b/soc/am65x_sr2/evm/sysfw_img_cfg.h
@@ -0,0 +1,40 @@
1/*
2 * K3 System Firmware Configuration Data
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H
37
38#define BOARDCFG_RM_RESASG_ENTRIES 65
39
40#endif /* SYSFW_IMG_CFG_H */
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