diff options
author | Dave Gerlach | 2020-04-02 22:01:21 -0500 |
---|---|---|
committer | Dave Gerlach | 2020-04-22 09:24:38 -0500 |
commit | c9e26b71b5349d885eb0866e0edffd983f5d505b (patch) | |
tree | 446deea32d7689ecad219e314b8da32de894dfd3 /soc/am65x_sr2 | |
parent | 93c0ee5566a075d1f82678b3ba607bfe3f0d1ce6 (diff) | |
download | k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.tar.gz k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.tar.xz k3-image-gen-c9e26b71b5349d885eb0866e0edffd983f5d505b.zip |
am65x_sr2: Update to ABI 3.0 resource types
Update the AM65x SR2 RM board configuration to use ABI 3.0 resource type
definitions.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Diffstat (limited to 'soc/am65x_sr2')
-rw-r--r-- | soc/am65x_sr2/evm/rm-cfg.c | 269 | ||||
-rw-r--r-- | soc/am65x_sr2/evm/sysfw_img_cfg.h | 2 |
2 files changed, 112 insertions, 159 deletions
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c index 71927b30c..1894ac1c1 100644 --- a/soc/am65x_sr2/evm/rm-cfg.c +++ b/soc/am65x_sr2/evm/rm-cfg.c | |||
@@ -1,7 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * K3 System Firmware Resource Management Configuration Data | 2 | * K3 System Firmware Resource Management Configuration Data |
3 | * | 3 | * |
4 | * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ | 4 | * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ |
5 | * Andreas Dannenberg <dannenberg@ti.com> | ||
5 | * | 6 | * |
6 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions |
@@ -69,392 +70,344 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = { | |||
69 | { | 70 | { |
70 | .start_resource = 16, | 71 | .start_resource = 16, |
71 | .num_resource = 240, | 72 | .num_resource = 240, |
72 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_IA_VINT), | 73 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, |
74 | RESASG_SUBTYPE_IA_VINT), | ||
73 | .host_id = HOST_ID_A53_2, | 75 | .host_id = HOST_ID_A53_2, |
74 | }, | 76 | }, |
75 | { | 77 | { |
76 | .start_resource = 16, | 78 | .start_resource = 16, |
77 | .num_resource = 4592, | 79 | .num_resource = 4592, |
78 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 80 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, |
81 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
79 | .host_id = HOST_ID_A53_2, | 82 | .host_id = HOST_ID_A53_2, |
80 | }, | 83 | }, |
81 | { | 84 | { |
82 | .start_resource = 0, | 85 | .start_resource = 0, |
83 | .num_resource = 64, | 86 | .num_resource = 64, |
84 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_IA_VINT), | 87 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, |
88 | RESASG_SUBTYPE_IA_VINT), | ||
85 | .host_id = HOST_ID_A53_2, | 89 | .host_id = HOST_ID_A53_2, |
86 | }, | 90 | }, |
87 | { | 91 | { |
88 | .start_resource = 20480, | 92 | .start_resource = 20480, |
89 | .num_resource = 1024, | 93 | .num_resource = 1024, |
90 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 94 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, |
95 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
91 | .host_id = HOST_ID_A53_2, | 96 | .host_id = HOST_ID_A53_2, |
92 | }, | 97 | }, |
93 | { | 98 | { |
94 | .start_resource = 0, | 99 | .start_resource = 0, |
95 | .num_resource = 64, | 100 | .num_resource = 64, |
96 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_IA_VINT), | 101 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, |
102 | RESASG_SUBTYPE_IA_VINT), | ||
97 | .host_id = HOST_ID_A53_2, | 103 | .host_id = HOST_ID_A53_2, |
98 | }, | 104 | }, |
99 | { | 105 | { |
100 | .start_resource = 22528, | 106 | .start_resource = 22528, |
101 | .num_resource = 1024, | 107 | .num_resource = 1024, |
102 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 108 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, |
109 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
103 | .host_id = HOST_ID_A53_2, | 110 | .host_id = HOST_ID_A53_2, |
104 | }, | 111 | }, |
105 | { | 112 | { |
106 | .start_resource = 8, | 113 | .start_resource = 8, |
107 | .num_resource = 248, | 114 | .num_resource = 248, |
108 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_IA_VINT), | 115 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
116 | RESASG_SUBTYPE_IA_VINT), | ||
109 | .host_id = HOST_ID_R5_0, | 117 | .host_id = HOST_ID_R5_0, |
110 | }, | 118 | }, |
111 | { | 119 | { |
112 | .start_resource = 16392, | 120 | .start_resource = 16392, |
113 | .num_resource = 992, | 121 | .num_resource = 992, |
114 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 122 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
123 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
115 | .host_id = HOST_ID_R5_0, | 124 | .host_id = HOST_ID_R5_0, |
116 | }, | 125 | }, |
117 | { | 126 | { |
118 | .start_resource = 17384, | 127 | .start_resource = 17384, |
119 | .num_resource = 536, | 128 | .num_resource = 536, |
120 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 129 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
130 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
121 | .host_id = HOST_ID_R5_0, | 131 | .host_id = HOST_ID_R5_0, |
122 | }, | 132 | }, |
123 | { | 133 | { |
124 | .start_resource = 49152, | 134 | .start_resource = 49152, |
125 | .num_resource = 1024, | 135 | .num_resource = 1024, |
126 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | 136 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
137 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
127 | .host_id = HOST_ID_A53_2, | 138 | .host_id = HOST_ID_A53_2, |
128 | }, | 139 | }, |
129 | { | 140 | { |
130 | .start_resource = 1, | 141 | .start_resource = 1, |
131 | .num_resource = 7, | 142 | .num_resource = 7, |
132 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN), | 143 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
144 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
133 | .host_id = HOST_ID_A53_2, | 145 | .host_id = HOST_ID_A53_2, |
134 | }, | 146 | }, |
135 | { | 147 | { |
136 | .start_resource = 8, | 148 | .start_resource = 8, |
137 | .num_resource = 112, | 149 | .num_resource = 112, |
138 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN), | 150 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
151 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
139 | .host_id = HOST_ID_A53_2, | 152 | .host_id = HOST_ID_A53_2, |
140 | }, | 153 | }, |
141 | { | 154 | { |
142 | .start_resource = 120, | 155 | .start_resource = 120, |
143 | .num_resource = 32, | 156 | .num_resource = 32, |
144 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_ECHAN), | 157 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
158 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
145 | .host_id = HOST_ID_A53_2, | 159 | .host_id = HOST_ID_A53_2, |
146 | }, | 160 | }, |
147 | { | 161 | { |
148 | .start_resource = 2, | 162 | .start_resource = 2, |
149 | .num_resource = 6, | 163 | .num_resource = 6, |
150 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN), | 164 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
165 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
151 | .host_id = HOST_ID_A53_2, | 166 | .host_id = HOST_ID_A53_2, |
152 | }, | 167 | }, |
153 | { | 168 | { |
154 | .start_resource = 8, | 169 | .start_resource = 8, |
155 | .num_resource = 142, | 170 | .num_resource = 142, |
156 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN), | 171 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
172 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
157 | .host_id = HOST_ID_A53_2, | 173 | .host_id = HOST_ID_A53_2, |
158 | }, | 174 | }, |
159 | { | 175 | { |
160 | .start_resource = 150, | 176 | .start_resource = 150, |
161 | .num_resource = 150, | 177 | .num_resource = 150, |
162 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 178 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
179 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
163 | .host_id = HOST_ID_A53_2, | 180 | .host_id = HOST_ID_A53_2, |
164 | }, | 181 | }, |
165 | { | 182 | { |
166 | .start_resource = 0, | 183 | .start_resource = 0, |
167 | .num_resource = 1, | 184 | .num_resource = 1, |
168 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | 185 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, |
186 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | ||
169 | .host_id = HOST_ID_A53_2, | 187 | .host_id = HOST_ID_A53_2, |
170 | }, | 188 | }, |
171 | { | 189 | { |
172 | .start_resource = 56320, | 190 | .start_resource = 56320, |
173 | .num_resource = 256, | 191 | .num_resource = 256, |
174 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | 192 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
193 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
175 | .host_id = HOST_ID_A53_2, | 194 | .host_id = HOST_ID_A53_2, |
176 | }, | 195 | }, |
177 | { | 196 | { |
178 | .start_resource = 0, | 197 | .start_resource = 0, |
179 | .num_resource = 2, | 198 | .num_resource = 2, |
180 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN), | 199 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
200 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
181 | .host_id = HOST_ID_A53_2, | 201 | .host_id = HOST_ID_A53_2, |
182 | }, | 202 | }, |
183 | { | 203 | { |
184 | .start_resource = 2, | 204 | .start_resource = 2, |
185 | .num_resource = 46, | 205 | .num_resource = 46, |
186 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN), | 206 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
207 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
187 | .host_id = HOST_ID_A53_2, | 208 | .host_id = HOST_ID_A53_2, |
188 | }, | 209 | }, |
189 | { | 210 | { |
190 | .start_resource = 0, | 211 | .start_resource = 0, |
191 | .num_resource = 2, | 212 | .num_resource = 2, |
192 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN), | 213 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
214 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
193 | .host_id = HOST_ID_A53_2, | 215 | .host_id = HOST_ID_A53_2, |
194 | }, | 216 | }, |
195 | { | 217 | { |
196 | .start_resource = 2, | 218 | .start_resource = 2, |
197 | .num_resource = 46, | 219 | .num_resource = 46, |
198 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN), | 220 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
221 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
199 | .host_id = HOST_ID_A53_2, | 222 | .host_id = HOST_ID_A53_2, |
200 | }, | 223 | }, |
201 | { | 224 | { |
202 | .start_resource = 48, | 225 | .start_resource = 48, |
203 | .num_resource = 48, | 226 | .num_resource = 48, |
204 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 227 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
228 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
205 | .host_id = HOST_ID_A53_2, | 229 | .host_id = HOST_ID_A53_2, |
206 | }, | 230 | }, |
207 | { | 231 | { |
208 | .start_resource = 2, | 232 | .start_resource = 2, |
209 | .num_resource = 46, | 233 | .num_resource = 46, |
210 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN), | 234 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
235 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
211 | .host_id = HOST_ID_R5_1, | 236 | .host_id = HOST_ID_R5_1, |
212 | }, | 237 | }, |
213 | { | 238 | { |
214 | .start_resource = 2, | 239 | .start_resource = 2, |
215 | .num_resource = 46, | 240 | .num_resource = 46, |
216 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN), | 241 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
242 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
217 | .host_id = HOST_ID_R5_1, | 243 | .host_id = HOST_ID_R5_1, |
218 | }, | 244 | }, |
219 | { | 245 | { |
220 | .start_resource = 48, | 246 | .start_resource = 48, |
221 | .num_resource = 48, | 247 | .num_resource = 48, |
222 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 248 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
249 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
223 | .host_id = HOST_ID_R5_1, | 250 | .host_id = HOST_ID_R5_1, |
224 | }, | 251 | }, |
225 | { | 252 | { |
226 | .start_resource = 0, | 253 | .start_resource = 0, |
227 | .num_resource = 1, | 254 | .num_resource = 1, |
228 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | 255 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, |
256 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | ||
229 | .host_id = HOST_ID_A53_2, | 257 | .host_id = HOST_ID_A53_2, |
230 | }, | 258 | }, |
231 | { | 259 | { |
232 | .start_resource = 1, | 260 | .start_resource = 1, |
233 | .num_resource = 7, | 261 | .num_resource = 7, |
234 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H), | 262 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
263 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
235 | .host_id = HOST_ID_A53_2, | 264 | .host_id = HOST_ID_A53_2, |
236 | }, | 265 | }, |
237 | { | 266 | { |
238 | .start_resource = 8, | 267 | .start_resource = 8, |
239 | .num_resource = 112, | 268 | .num_resource = 112, |
240 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX), | 269 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
241 | .host_id = HOST_ID_A53_2, | 270 | RESASG_SUBTYPE_RA_UDMAP_TX), |
242 | }, | ||
243 | { | ||
244 | .start_resource = 120, | ||
245 | .num_resource = 32, | ||
246 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
247 | .host_id = HOST_ID_A53_2, | 271 | .host_id = HOST_ID_A53_2, |
248 | }, | 272 | }, |
249 | { | 273 | { |
250 | .start_resource = 153, | 274 | .start_resource = 153, |
251 | .num_resource = 7, | 275 | .num_resource = 7, |
252 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H), | 276 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
277 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
253 | .host_id = HOST_ID_A53_2, | 278 | .host_id = HOST_ID_A53_2, |
254 | }, | 279 | }, |
255 | { | 280 | { |
256 | .start_resource = 160, | 281 | .start_resource = 160, |
257 | .num_resource = 142, | 282 | .num_resource = 142, |
258 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX), | 283 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
284 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
259 | .host_id = HOST_ID_A53_2, | 285 | .host_id = HOST_ID_A53_2, |
260 | }, | 286 | }, |
261 | { | 287 | { |
262 | .start_resource = 304, | 288 | .start_resource = 304, |
263 | .num_resource = 464, | 289 | .num_resource = 464, |
264 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP), | 290 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
291 | RESASG_SUBTYPE_RA_GP), | ||
265 | .host_id = HOST_ID_A53_2, | 292 | .host_id = HOST_ID_A53_2, |
266 | }, | 293 | }, |
267 | { | 294 | { |
268 | .start_resource = 0, | 295 | .start_resource = 0, |
269 | .num_resource = 1, | 296 | .num_resource = 1, |
270 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES), | 297 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, |
298 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
271 | .host_id = HOST_ID_A53_2, | 299 | .host_id = HOST_ID_A53_2, |
272 | }, | 300 | }, |
273 | { | 301 | { |
274 | .start_resource = 0, | 302 | .start_resource = 0, |
275 | .num_resource = 2, | 303 | .num_resource = 2, |
276 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H), | 304 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
305 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
277 | .host_id = HOST_ID_A53_2, | 306 | .host_id = HOST_ID_A53_2, |
278 | }, | 307 | }, |
279 | { | 308 | { |
280 | .start_resource = 2, | 309 | .start_resource = 2, |
281 | .num_resource = 46, | 310 | .num_resource = 46, |
282 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX), | 311 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
312 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
283 | .host_id = HOST_ID_A53_2, | 313 | .host_id = HOST_ID_A53_2, |
284 | }, | 314 | }, |
285 | { | 315 | { |
286 | .start_resource = 48, | 316 | .start_resource = 48, |
287 | .num_resource = 2, | 317 | .num_resource = 2, |
288 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H), | 318 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
319 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
289 | .host_id = HOST_ID_A53_2, | 320 | .host_id = HOST_ID_A53_2, |
290 | }, | 321 | }, |
291 | { | 322 | { |
292 | .start_resource = 50, | 323 | .start_resource = 50, |
293 | .num_resource = 46, | 324 | .num_resource = 46, |
294 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX), | 325 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
326 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
295 | .host_id = HOST_ID_A53_2, | 327 | .host_id = HOST_ID_A53_2, |
296 | }, | 328 | }, |
297 | { | 329 | { |
298 | .start_resource = 96, | 330 | .start_resource = 96, |
299 | .num_resource = 160, | 331 | .num_resource = 160, |
300 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP), | 332 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
333 | RESASG_SUBTYPE_RA_GP), | ||
301 | .host_id = HOST_ID_A53_2, | 334 | .host_id = HOST_ID_A53_2, |
302 | }, | 335 | }, |
303 | { | 336 | { |
304 | .start_resource = 0, | ||
305 | .num_resource = 2, | ||
306 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
307 | .host_id = HOST_ID_R5_1, | ||
308 | }, | ||
309 | { | ||
310 | .start_resource = 2, | 337 | .start_resource = 2, |
311 | .num_resource = 46, | 338 | .num_resource = 46, |
312 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX), | 339 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
313 | .host_id = HOST_ID_R5_1, | 340 | RESASG_SUBTYPE_RA_UDMAP_TX), |
314 | }, | ||
315 | { | ||
316 | .start_resource = 48, | ||
317 | .num_resource = 2, | ||
318 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
319 | .host_id = HOST_ID_R5_1, | 341 | .host_id = HOST_ID_R5_1, |
320 | }, | 342 | }, |
321 | { | 343 | { |
322 | .start_resource = 50, | 344 | .start_resource = 50, |
323 | .num_resource = 46, | 345 | .num_resource = 46, |
324 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX), | 346 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
347 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
325 | .host_id = HOST_ID_R5_1, | 348 | .host_id = HOST_ID_R5_1, |
326 | }, | 349 | }, |
327 | { | 350 | { |
328 | .start_resource = 96, | 351 | .start_resource = 96, |
329 | .num_resource = 160, | 352 | .num_resource = 160, |
330 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP), | 353 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
354 | RESASG_SUBTYPE_RA_GP), | ||
331 | .host_id = HOST_ID_R5_1, | 355 | .host_id = HOST_ID_R5_1, |
332 | }, | 356 | }, |
333 | { | 357 | { |
334 | .start_resource = 0, | 358 | .start_resource = 0, |
335 | .num_resource = 1, | 359 | .num_resource = 1, |
336 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES), | 360 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, |
337 | .host_id = HOST_ID_A53_2, | 361 | RESASG_SUBTYPE_RA_ERROR_OES), |
338 | }, | ||
339 | { | ||
340 | .start_resource = 80, | ||
341 | .num_resource = 48, | ||
342 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0), | ||
343 | .host_id = HOST_ID_A53_2, | 362 | .host_id = HOST_ID_A53_2, |
344 | }, | 363 | }, |
345 | { | 364 | { |
346 | .start_resource = 392, | 365 | .type = RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
366 | .start_resource = 0, | ||
347 | .num_resource = 32, | 367 | .num_resource = 32, |
348 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0), | ||
349 | .host_id = HOST_ID_A53_2, | ||
350 | }, | ||
351 | { | ||
352 | .start_resource = 448, | ||
353 | .num_resource = 50, | ||
354 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0), | ||
355 | .host_id = HOST_ID_A53_2, | ||
356 | }, | ||
357 | { | ||
358 | .start_resource = 498, | ||
359 | .num_resource = 6, | ||
360 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0), | ||
361 | .host_id = HOST_ID_A53_2, | ||
362 | }, | ||
363 | { | ||
364 | .start_resource = 544, | ||
365 | .num_resource = 16, | ||
366 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0), | ||
367 | .host_id = HOST_ID_A53_2, | 368 | .host_id = HOST_ID_A53_2, |
368 | }, | 369 | }, |
369 | { | 370 | { |
370 | .start_resource = 712, | 371 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
371 | .num_resource = 16, | 372 | .start_resource = 0, |
372 | .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0), | 373 | .num_resource = 64, |
373 | .host_id = HOST_ID_A53_2, | ||
374 | }, | ||
375 | { | ||
376 | .start_resource = 68, | ||
377 | .num_resource = 28, | ||
378 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0), | ||
379 | .host_id = HOST_ID_R5_0, | 374 | .host_id = HOST_ID_R5_0, |
380 | }, | 375 | }, |
381 | { | 376 | { |
382 | .start_resource = 124, | 377 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
383 | .num_resource = 16, | 378 | .start_resource = 0, |
384 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0), | 379 | .num_resource = 48, |
385 | .host_id = HOST_ID_R5_0, | 380 | .host_id = HOST_ID_R5_0, |
386 | }, | 381 | }, |
387 | { | 382 | { |
388 | .start_resource = 160, | 383 | .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
384 | .start_resource = 0, | ||
389 | .num_resource = 32, | 385 | .num_resource = 32, |
390 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0), | 386 | .host_id = HOST_ID_A53_2, |
391 | .host_id = HOST_ID_R5_0, | ||
392 | }, | ||
393 | { | ||
394 | .start_resource = 224, | ||
395 | .num_resource = 48, | ||
396 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0), | ||
397 | .host_id = HOST_ID_R5_0, | ||
398 | }, | 387 | }, |
399 | { | 388 | { |
400 | .start_resource = 68, | 389 | .type = RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
401 | .num_resource = 28, | 390 | .start_resource = 0, |
402 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0), | 391 | .num_resource = 40, |
403 | .host_id = HOST_ID_R5_0, | 392 | .host_id = HOST_ID_A53_2, |
404 | }, | 393 | }, |
405 | { | 394 | { |
406 | .start_resource = 124, | 395 | .type = RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), |
396 | .start_resource = 0, | ||
407 | .num_resource = 16, | 397 | .num_resource = 16, |
408 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0), | 398 | .host_id = HOST_ID_A53_2, |
409 | .host_id = HOST_ID_R5_0, | ||
410 | }, | 399 | }, |
411 | { | 400 | { |
412 | .start_resource = 192, | 401 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), |
413 | .num_resource = 32, | 402 | .start_resource = 16, |
414 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0), | 403 | .num_resource = 136, |
415 | .host_id = HOST_ID_R5_2, | 404 | .host_id = HOST_ID_A53_2, |
416 | }, | 405 | }, |
417 | { | 406 | { |
418 | .start_resource = 224, | 407 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), |
419 | .num_resource = 48, | 408 | .start_resource = 4, |
420 | .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0), | 409 | .num_resource = 28, |
421 | .host_id = HOST_ID_R5_0, | 410 | .host_id = HOST_ID_R5_0, |
422 | }, | 411 | }, |
423 | { | ||
424 | .start_resource = 46, | ||
425 | .num_resource = 8, | ||
426 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0), | ||
427 | .host_id = HOST_ID_ICSSG_0, | ||
428 | }, | ||
429 | { | ||
430 | .start_resource = 88, | ||
431 | .num_resource = 8, | ||
432 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0), | ||
433 | .host_id = HOST_ID_ICSSG_0, | ||
434 | }, | ||
435 | { | ||
436 | .start_resource = 46, | ||
437 | .num_resource = 8, | ||
438 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0), | ||
439 | .host_id = HOST_ID_ICSSG_1, | ||
440 | }, | ||
441 | { | ||
442 | .start_resource = 88, | ||
443 | .num_resource = 8, | ||
444 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0), | ||
445 | .host_id = HOST_ID_ICSSG_1, | ||
446 | }, | ||
447 | { | ||
448 | .start_resource = 46, | ||
449 | .num_resource = 8, | ||
450 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0), | ||
451 | .host_id = HOST_ID_ICSSG_2, | ||
452 | }, | ||
453 | { | ||
454 | .start_resource = 88, | ||
455 | .num_resource = 8, | ||
456 | .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0), | ||
457 | .host_id = HOST_ID_ICSSG_2, | ||
458 | }, | ||
459 | }, | 412 | }, |
460 | }; | 413 | }; |
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h index 204369441..a69f6c6d3 100644 --- a/soc/am65x_sr2/evm/sysfw_img_cfg.h +++ b/soc/am65x_sr2/evm/sysfw_img_cfg.h | |||
@@ -35,6 +35,6 @@ | |||
35 | #ifndef SYSFW_IMG_CFG_H | 35 | #ifndef SYSFW_IMG_CFG_H |
36 | #define SYSFW_IMG_CFG_H | 36 | #define SYSFW_IMG_CFG_H |
37 | 37 | ||
38 | #define BOARDCFG_RM_RESASG_ENTRIES 65 | 38 | #define BOARDCFG_RM_RESASG_ENTRIES 50 |
39 | 39 | ||
40 | #endif /* SYSFW_IMG_CFG_H */ | 40 | #endif /* SYSFW_IMG_CFG_H */ |