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authorVignesh Raghavendra2020-09-17 02:07:30 -0500
committerDave Gerlach2020-09-21 20:33:25 -0500
commit09256d5c21e6281d224646c1d4163d4dd0925238 (patch)
tree0c1956694e990088fee83d9815308edf734205b3 /soc/j7200
parent2550cf307da335dda0f3f005477b228100615556 (diff)
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soc: j7200: rm-cfg: Allocate one HC channel pair for A7207.01.00.003
Allocate 1 HC channel pair each in MAIN UDMA and MCU UDMA for A72 so as to enable Linux/U-Boot to demonstrate max performance with HyperFlash and OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'soc/j7200')
-rw-r--r--soc/j7200/evm/rm-cfg.c88
-rw-r--r--soc/j7200/evm/sysfw_img_cfg.h2
2 files changed, 73 insertions, 17 deletions
diff --git a/soc/j7200/evm/rm-cfg.c b/soc/j7200/evm/rm-cfg.c
index 9dc7048fa..3fe2ff777 100644
--- a/soc/j7200/evm/rm-cfg.c
+++ b/soc/j7200/evm/rm-cfg.c
@@ -699,7 +699,14 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
699 /* Main NAVSS Rings for High capacity Rx channels */ 699 /* Main NAVSS Rings for High capacity Rx channels */
700 { 700 {
701 .start_resource = 62, 701 .start_resource = 62,
702 .num_resource = 2, 702 .num_resource = 1,
703 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
704 RESASG_SUBTYPE_RA_UDMAP_RX_H),
705 .host_id = HOST_ID_A72_2,
706 },
707 {
708 .start_resource = 63,
709 .num_resource = 1,
703 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 710 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
704 RESASG_SUBTYPE_RA_UDMAP_RX_H), 711 RESASG_SUBTYPE_RA_UDMAP_RX_H),
705 .host_id = HOST_ID_MAIN_0_R5_0, 712 .host_id = HOST_ID_MAIN_0_R5_0,
@@ -715,7 +722,14 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
715 /* Main NAVSS Rings for High capacity Tx channels */ 722 /* Main NAVSS Rings for High capacity Tx channels */
716 { 723 {
717 .start_resource = 2, 724 .start_resource = 2,
718 .num_resource = 2, 725 .num_resource = 1,
726 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
727 RESASG_SUBTYPE_RA_UDMAP_TX_H),
728 .host_id = HOST_ID_A72_2,
729 },
730 {
731 .start_resource = 3,
732 .num_resource = 1,
719 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0, 733 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_RINGACC_0,
720 RESASG_SUBTYPE_RA_UDMAP_TX_H), 734 RESASG_SUBTYPE_RA_UDMAP_TX_H),
721 .host_id = HOST_ID_MAIN_0_R5_0, 735 .host_id = HOST_ID_MAIN_0_R5_0,
@@ -941,7 +955,14 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
941 /* Main NAVSS UDMA High capacity Rx channels */ 955 /* Main NAVSS UDMA High capacity Rx channels */
942 { 956 {
943 .start_resource = 2, 957 .start_resource = 2,
944 .num_resource = 2, 958 .num_resource = 1,
959 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
960 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
961 .host_id = HOST_ID_A72_2,
962 },
963 {
964 .start_resource = 3,
965 .num_resource = 1,
945 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 966 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
946 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 967 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
947 .host_id = HOST_ID_MAIN_0_R5_0, 968 .host_id = HOST_ID_MAIN_0_R5_0,
@@ -1042,7 +1063,14 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1042 /* Main NAVSS UDMA High capacity Tx channels */ 1063 /* Main NAVSS UDMA High capacity Tx channels */
1043 { 1064 {
1044 .start_resource = 2, 1065 .start_resource = 2,
1045 .num_resource = 2, 1066 .num_resource = 1,
1067 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1068 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1069 .host_id = HOST_ID_A72_2,
1070 },
1071 {
1072 .start_resource = 3,
1073 .num_resource = 1,
1046 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0, 1074 .type = RESASG_UTYPE (J7200_DEV_NAVSS0_UDMAP_0,
1047 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 1075 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1048 .host_id = HOST_ID_MAIN_0_R5_0, 1076 .host_id = HOST_ID_MAIN_0_R5_0,
@@ -1556,14 +1584,21 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1556 /* MCU NAVSS Rings for High capacity Rx channels */ 1584 /* MCU NAVSS Rings for High capacity Rx channels */
1557 { 1585 {
1558 .start_resource = 48, 1586 .start_resource = 48,
1559 .num_resource = 2, 1587 .num_resource = 1,
1588 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1589 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1590 .host_id = HOST_ID_A72_2,
1591 },
1592 {
1593 .start_resource = 49,
1594 .num_resource = 1,
1560 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1595 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1561 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1596 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1562 .host_id = HOST_ID_MCU_0_R5_0, 1597 .host_id = HOST_ID_MCU_0_R5_0,
1563 }, 1598 },
1564 { 1599 {
1565 .start_resource = 48, 1600 .start_resource = 49,
1566 .num_resource = 2, 1601 .num_resource = 1,
1567 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1602 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1568 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1603 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1569 .host_id = HOST_ID_MCU_0_R5_1, 1604 .host_id = HOST_ID_MCU_0_R5_1,
@@ -1571,14 +1606,21 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1571 /* MCU NAVSS Rings for High capacity Tx channels */ 1606 /* MCU NAVSS Rings for High capacity Tx channels */
1572 { 1607 {
1573 .start_resource = 0, 1608 .start_resource = 0,
1574 .num_resource = 2, 1609 .num_resource = 1,
1610 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1611 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1612 .host_id = HOST_ID_A72_2,
1613 },
1614 {
1615 .start_resource = 1,
1616 .num_resource = 1,
1575 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1617 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1576 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1618 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1577 .host_id = HOST_ID_MCU_0_R5_0, 1619 .host_id = HOST_ID_MCU_0_R5_0,
1578 }, 1620 },
1579 { 1621 {
1580 .start_resource = 0, 1622 .start_resource = 1,
1581 .num_resource = 2, 1623 .num_resource = 1,
1582 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0, 1624 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_RINGACC0,
1583 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1625 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1584 .host_id = HOST_ID_MCU_0_R5_1, 1626 .host_id = HOST_ID_MCU_0_R5_1,
@@ -1845,14 +1887,21 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1845 /* MCU NAVSS UDMA High capacity Rx channels */ 1887 /* MCU NAVSS UDMA High capacity Rx channels */
1846 { 1888 {
1847 .start_resource = 0, 1889 .start_resource = 0,
1848 .num_resource = 2, 1890 .num_resource = 1,
1891 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1892 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1893 .host_id = HOST_ID_A72_2,
1894 },
1895 {
1896 .start_resource = 1,
1897 .num_resource = 1,
1849 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1898 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1850 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1899 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1851 .host_id = HOST_ID_MCU_0_R5_0, 1900 .host_id = HOST_ID_MCU_0_R5_0,
1852 }, 1901 },
1853 { 1902 {
1854 .start_resource = 0, 1903 .start_resource = 1,
1855 .num_resource = 2, 1904 .num_resource = 1,
1856 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 1905 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1857 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1906 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1858 .host_id = HOST_ID_MCU_0_R5_1, 1907 .host_id = HOST_ID_MCU_0_R5_1,
@@ -1966,14 +2015,21 @@ const struct boardcfg_rm_local j7200_boardcfg_rm_data = {
1966 /* MCU NAVSS UDMA High capacity Tx channels */ 2015 /* MCU NAVSS UDMA High capacity Tx channels */
1967 { 2016 {
1968 .start_resource = 0, 2017 .start_resource = 0,
1969 .num_resource = 2, 2018 .num_resource = 1,
2019 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
2020 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2021 .host_id = HOST_ID_A72_2,
2022 },
2023 {
2024 .start_resource = 1,
2025 .num_resource = 1,
1970 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 2026 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1971 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 2027 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1972 .host_id = HOST_ID_MCU_0_R5_0, 2028 .host_id = HOST_ID_MCU_0_R5_0,
1973 }, 2029 },
1974 { 2030 {
1975 .start_resource = 0, 2031 .start_resource = 1,
1976 .num_resource = 2, 2032 .num_resource = 1,
1977 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0, 2033 .type = RESASG_UTYPE (J7200_DEV_MCU_NAVSS0_UDMAP_0,
1978 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 2034 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1979 .host_id = HOST_ID_MCU_0_R5_1, 2035 .host_id = HOST_ID_MCU_0_R5_1,
diff --git a/soc/j7200/evm/sysfw_img_cfg.h b/soc/j7200/evm/sysfw_img_cfg.h
index 7392fe41a..c206c2653 100644
--- a/soc/j7200/evm/sysfw_img_cfg.h
+++ b/soc/j7200/evm/sysfw_img_cfg.h
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 261 40#define BOARDCFG_RM_RESASG_ENTRIES 269
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */
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