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authorAndreas Dannenberg2019-06-05 15:00:05 -0500
committerAndreas Dannenberg2019-06-10 11:42:06 -0500
commitd2c74f403c761be1f20e7fd4de8b37220d0f5454 (patch)
treeeb50381e6e1e42aa27d55bd8a608c0d0c5c48c18 /soc/j721e
parentf14250ffca824ac274b20d3431b60ed920c218ec (diff)
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Introduce initial J721E EVM support
Add the consolidated configuration files that were arrived at during J721E silicon wakeup. Note that SYSFW debug trace both to memory as well as to the UART is disabled in alignment with the production configuration used on AM65x. If debug trace output is desired during development refer to the SYSFW release documentation (referenced in the included README.md file) discussion related to 'trace_dst_enables' and 'trace_src_enables'. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Nikhil Devshatwar <nikhil.nd@ti.com>
Diffstat (limited to 'soc/j721e')
-rw-r--r--soc/j721e/evm/board-cfg.c82
-rw-r--r--soc/j721e/evm/pm-cfg.c44
-rw-r--r--soc/j721e/evm/rm-cfg.c1728
-rw-r--r--soc/j721e/evm/sec-cfg.c62
-rw-r--r--soc/j721e/evm/sysfw_img_cfg.h40
5 files changed, 1956 insertions, 0 deletions
diff --git a/soc/j721e/evm/board-cfg.c b/soc/j721e/evm/board-cfg.c
new file mode 100644
index 000000000..74ceee781
--- /dev/null
+++ b/soc/j721e/evm/board-cfg.c
@@ -0,0 +1,82 @@
1/*
2 * K3 System Firmware Board Configuration Data
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37
38const struct boardcfg j721e_boardcfg_data = {
39 /* boardcfg_abi_rev */
40 .rev = {
41 .boardcfg_abi_maj = 0x0,
42 .boardcfg_abi_min = 0x1,
43 },
44
45 /* boardcfg_control */
46 .control = {
47 .subhdr = {
48 .magic = BOARDCFG_CONTROL_MAGIC_NUM,
49 .size = sizeof(struct boardcfg_control),
50 },
51 .main_isolation_enable = 0x5A,
52 .main_isolation_hostid = 0x2,
53 },
54
55 /* boardcfg sec_proxy */
56 .secproxy = {
57 .subhdr = {
58 .magic = BOARDCFG_SECPROXY_MAGIC_NUM,
59 .size = sizeof(struct boardcfg_secproxy),
60 },
61 .scaling_factor = 0x1,
62 .scaling_profile = 0x1,
63 .disable_main_nav_secure_proxy = 0,
64 },
65
66 /* boardcfg_msmc */
67 .msmc = {
68 .subhdr = {
69 .magic = BOARDCFG_MSMC_MAGIC_NUM,
70 .size = sizeof(struct boardcfg_msmc),
71 },
72 .msmc_cache_size = 0x10,
73 },
74
75 /* boardcfg_dbg_cfg */
76 .debug_cfg = {
77 .subhdr = {
78 .magic = BOARDCFG_DBG_CFG_MAGIC_NUM,
79 .size = sizeof(struct boardcfg_dbg_cfg),
80 },
81 },
82};
diff --git a/soc/j721e/evm/pm-cfg.c b/soc/j721e/evm/pm-cfg.c
new file mode 100644
index 000000000..a3fd12029
--- /dev/null
+++ b/soc/j721e/evm/pm-cfg.c
@@ -0,0 +1,44 @@
1/*
2 * K3 System Firmware Power Management Configuration Data
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37
38const struct boardcfg_pm j721e_boardcfg_pm_data = {
39 /* boardcfg_abi_rev */
40 .rev = {
41 .boardcfg_abi_maj = 0x0,
42 .boardcfg_abi_min = 0x1,
43 },
44};
diff --git a/soc/j721e/evm/rm-cfg.c b/soc/j721e/evm/rm-cfg.c
new file mode 100644
index 000000000..fbb1cf970
--- /dev/null
+++ b/soc/j721e/evm/rm-cfg.c
@@ -0,0 +1,1728 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37#include <hosts.h>
38#include <devices.h>
39#include <resasg_types.h>
40
41const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
42 .rm_boardcfg = {
43 /* boardcfg_abi_rev */
44 .rev = {
45 .boardcfg_abi_maj = 0x0,
46 .boardcfg_abi_min = 0x1,
47 },
48
49 /* boardcfg_rm_host_cfg */
50 .host_cfg = {
51 .subhdr = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 },
55 .host_cfg_entries = {{0}},
56 },
57
58 /* boardcfg_rm_resasg */
59 .resasg = {
60 .subhdr = {
61 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
62 .size = sizeof (struct boardcfg_rm_resasg),
63 },
64 .resasg_entries_size =
65 BOARDCFG_RM_RESASG_ENTRIES *
66 sizeof (struct boardcfg_rm_resasg_entry),
67 .reserved = 0,
68 /* .resasg_entries is set via boardcfg_rm_local */
69 },
70 },
71
72 /* This is actually part of .resasg */
73 .resasg_entries = {
74
75 /* GIC/CLEC slot assignment for NAVSS INTR */
76 {
77 .start_resource = 74,
78 .num_resource = 54,
79 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
80 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
81 .host_id = HOST_ID_A72_2,
82 },
83 {
84 .start_resource = 392,
85 .num_resource = 56,
86 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
87 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
88 .host_id = HOST_ID_A72_2,
89 },
90 {
91 .start_resource = 448,
92 .num_resource = 64,
93 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
94 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
95 .host_id = HOST_ID_A72_2,
96 },
97 {
98 .start_resource = 672,
99 .num_resource = 14,
100 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
101 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0),
102 .host_id = HOST_ID_A72_2,
103 },
104 {
105 .start_resource = 686,
106 .num_resource = 32,
107 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
108 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0),
109 .host_id = HOST_ID_A72_3,
110 },
111 {
112 .start_resource = 718,
113 .num_resource = 8,
114 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_CLEC,
115 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0),
116 .host_id = HOST_ID_C7X_1,
117 },
118 {
119 .start_resource = 960,
120 .num_resource = 16,
121 .type = RESASG_UTYPE (J721E_DEV_COMPUTE_CLUSTER0_GIC500SS,
122 RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
123 .host_id = HOST_ID_A72_2,
124 },
125
126 /* Main NAV INTA assignment */
127 /* Main NAV INTA VINT */
128 {
129 .start_resource = 38,
130 .num_resource = 100,
131 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
132 RESASG_SUBTYPE_IA_VINT),
133 .host_id = HOST_ID_A72_2,
134 },
135 {
136 .start_resource = 138,
137 .num_resource = 16,
138 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
139 RESASG_SUBTYPE_IA_VINT),
140 .host_id = HOST_ID_A72_3,
141 },
142 {
143 .start_resource = 154,
144 .num_resource = 4,
145 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
146 RESASG_SUBTYPE_IA_VINT),
147 .host_id = HOST_ID_MCU_0_R5_0,
148 },
149 {
150 .start_resource = 158,
151 .num_resource = 4,
152 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
153 RESASG_SUBTYPE_IA_VINT),
154 .host_id = HOST_ID_MCU_0_R5_2,
155 },
156 {
157 .start_resource = 162,
158 .num_resource = 20,
159 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
160 RESASG_SUBTYPE_IA_VINT),
161 .host_id = HOST_ID_MAIN_0_R5_0,
162 },
163 {
164 .start_resource = 182,
165 .num_resource = 18,
166 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
167 RESASG_SUBTYPE_IA_VINT),
168 .host_id = HOST_ID_MAIN_0_R5_2,
169 },
170 {
171 .start_resource = 200,
172 .num_resource = 16,
173 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
174 RESASG_SUBTYPE_IA_VINT),
175 .host_id = HOST_ID_MAIN_1_R5_0,
176 },
177 {
178 .start_resource = 216,
179 .num_resource = 16,
180 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
181 RESASG_SUBTYPE_IA_VINT),
182 .host_id = HOST_ID_MAIN_1_R5_2,
183 },
184 {
185 .start_resource = 232,
186 .num_resource = 8,
187 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
188 RESASG_SUBTYPE_IA_VINT),
189 .host_id = HOST_ID_C7X_1,
190 },
191 {
192 .start_resource = 240,
193 .num_resource = 8,
194 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
195 RESASG_SUBTYPE_IA_VINT),
196 .host_id = HOST_ID_C6X_0_1,
197 },
198 {
199 .start_resource = 248,
200 .num_resource = 8,
201 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
202 RESASG_SUBTYPE_IA_VINT),
203 .host_id = HOST_ID_C6X_1_1,
204 },
205
206 /* Main NAV INTA SEVT */
207 {
208 .start_resource = 38,
209 .num_resource = 1024,
210 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
211 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
212 .host_id = HOST_ID_A72_2,
213 },
214 {
215 .start_resource = 1062,
216 .num_resource = 512,
217 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
218 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
219 .host_id = HOST_ID_A72_3,
220 },
221 {
222 .start_resource = 1574,
223 .num_resource = 256,
224 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
225 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
226 .host_id = HOST_ID_MCU_0_R5_0,
227 },
228 {
229 .start_resource = 1830,
230 .num_resource = 256,
231 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
232 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
233 .host_id = HOST_ID_MCU_0_R5_2,
234 },
235 {
236 .start_resource = 2086,
237 .num_resource = 512,
238 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
239 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
240 .host_id = HOST_ID_MAIN_0_R5_0,
241 },
242 {
243 .start_resource = 2598,
244 .num_resource = 256,
245 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
246 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
247 .host_id = HOST_ID_MAIN_0_R5_2,
248 },
249 {
250 .start_resource = 2854,
251 .num_resource = 512,
252 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
253 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
254 .host_id = HOST_ID_MAIN_1_R5_0,
255 },
256 {
257 .start_resource = 3366,
258 .num_resource = 256,
259 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
260 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
261 .host_id = HOST_ID_MAIN_1_R5_2,
262 },
263 {
264 .start_resource = 3622,
265 .num_resource = 256,
266 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
267 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
268 .host_id = HOST_ID_C7X_1,
269 },
270 {
271 .start_resource = 3878,
272 .num_resource = 256,
273 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
274 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
275 .host_id = HOST_ID_C6X_0_1,
276 },
277 {
278 .start_resource = 4134,
279 .num_resource = 256,
280 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMASS_INTAGGR_0,
281 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
282 .host_id = HOST_ID_C6X_1_1,
283 },
284
285 /* Main UDMA */
286 /* Main UDMA UHC TX channel assignment */
287 {
288 .start_resource = 0,
289 .num_resource = 2,
290 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
291 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
292 .host_id = HOST_ID_A72_2,
293 },
294 {
295 .start_resource = 2,
296 .num_resource = 2,
297 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
298 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
299 .host_id = HOST_ID_MAIN_0_R5_2,
300 },
301
302 /* Main UDMA HC TX channel assignment */
303 {
304 .start_resource = 4,
305 .num_resource = 4,
306 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
307 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
308 .host_id = HOST_ID_A72_2,
309 },
310 {
311 .start_resource = 8,
312 .num_resource = 4,
313 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
314 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
315 .host_id = HOST_ID_MAIN_0_R5_0,
316 },
317 {
318 .start_resource = 12,
319 .num_resource = 4,
320 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
321 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
322 .host_id = HOST_ID_MAIN_0_R5_2,
323 },
324
325 /* Main UDMA normal TX channel assignment */
326 {
327 .start_resource = 16,
328 .num_resource = 2,
329 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
330 RESASG_SUBTYPE_UDMAP_TX_CHAN),
331 .host_id = HOST_ID_MCU_0_R5_0,
332 },
333 {
334 .start_resource = 18,
335 .num_resource = 2,
336 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
337 RESASG_SUBTYPE_UDMAP_TX_CHAN),
338 .host_id = HOST_ID_MCU_0_R5_2,
339 },
340 {
341 .start_resource = 20,
342 .num_resource = 6,
343 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
344 RESASG_SUBTYPE_UDMAP_TX_CHAN),
345 .host_id = HOST_ID_MAIN_1_R5_0,
346 },
347 {
348 .start_resource = 26,
349 .num_resource = 6,
350 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
351 RESASG_SUBTYPE_UDMAP_TX_CHAN),
352 .host_id = HOST_ID_MAIN_1_R5_2,
353 },
354 {
355 .start_resource = 32,
356 .num_resource = 6,
357 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
358 RESASG_SUBTYPE_UDMAP_TX_CHAN),
359 .host_id = HOST_ID_C7X_1,
360 },
361 {
362 .start_resource = 38,
363 .num_resource = 16,
364 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
365 RESASG_SUBTYPE_UDMAP_TX_CHAN),
366 .host_id = HOST_ID_C6X_0_1,
367 },
368 {
369 .start_resource = 54,
370 .num_resource = 8,
371 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
372 RESASG_SUBTYPE_UDMAP_TX_CHAN),
373 .host_id = HOST_ID_C6X_1_1,
374 },
375 {
376 .start_resource = 62,
377 .num_resource = 9,
378 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
379 RESASG_SUBTYPE_UDMAP_TX_CHAN),
380 .host_id = HOST_ID_MAIN_0_R5_0,
381 },
382 /* Block copy channels are 77-79 */
383 {
384 .start_resource = 71,
385 .num_resource = 9,
386 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
387 RESASG_SUBTYPE_UDMAP_TX_CHAN),
388 .host_id = HOST_ID_MAIN_0_R5_2,
389 },
390 {
391 .start_resource = 80,
392 .num_resource = 60,
393 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
394 RESASG_SUBTYPE_UDMAP_TX_CHAN),
395 .host_id = HOST_ID_A72_2,
396 },
397
398 /* Main UDMA UHC RX channel assignment */
399 {
400 .start_resource = 0,
401 .num_resource = 2,
402 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
403 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
404 .host_id = HOST_ID_A72_2,
405 },
406 {
407 .start_resource = 2,
408 .num_resource = 2,
409 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
410 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
411 .host_id = HOST_ID_MAIN_0_R5_2,
412 },
413
414 /* Main UDMA HC RX channel assignment */
415 {
416 .start_resource = 4,
417 .num_resource = 4,
418 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
419 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
420 .host_id = HOST_ID_A72_2,
421 },
422 {
423 .start_resource = 8,
424 .num_resource = 4,
425 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
426 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
427 .host_id = HOST_ID_MAIN_0_R5_0,
428 },
429 {
430 .start_resource = 12,
431 .num_resource = 4,
432 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
433 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
434 .host_id = HOST_ID_MAIN_0_R5_2,
435 },
436
437 /* Main UDMA normal RX channel assignment */
438 {
439 .start_resource = 16,
440 .num_resource = 2,
441 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
442 RESASG_SUBTYPE_UDMAP_RX_CHAN),
443 .host_id = HOST_ID_MCU_0_R5_0,
444 },
445 {
446 .start_resource = 18,
447 .num_resource = 2,
448 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
449 RESASG_SUBTYPE_UDMAP_RX_CHAN),
450 .host_id = HOST_ID_MCU_0_R5_2,
451 },
452 {
453 .start_resource = 20,
454 .num_resource = 6,
455 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
456 RESASG_SUBTYPE_UDMAP_RX_CHAN),
457 .host_id = HOST_ID_MAIN_1_R5_0,
458 },
459 {
460 .start_resource = 26,
461 .num_resource = 6,
462 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
463 RESASG_SUBTYPE_UDMAP_RX_CHAN),
464 .host_id = HOST_ID_MAIN_1_R5_2,
465 },
466 {
467 .start_resource = 32,
468 .num_resource = 6,
469 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
470 RESASG_SUBTYPE_UDMAP_RX_CHAN),
471 .host_id = HOST_ID_C7X_1,
472 },
473 {
474 .start_resource = 38,
475 .num_resource = 16,
476 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
477 RESASG_SUBTYPE_UDMAP_RX_CHAN),
478 .host_id = HOST_ID_C6X_0_1,
479 },
480 {
481 .start_resource = 54,
482 .num_resource = 8,
483 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
484 RESASG_SUBTYPE_UDMAP_RX_CHAN),
485 .host_id = HOST_ID_C6X_1_1,
486 },
487 {
488 .start_resource = 62,
489 .num_resource = 15,
490 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
491 RESASG_SUBTYPE_UDMAP_RX_CHAN),
492 .host_id = HOST_ID_MAIN_0_R5_0,
493 },
494 /* Block copy channels are 77-79 */
495 {
496 .start_resource = 77,
497 .num_resource = 15,
498 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
499 RESASG_SUBTYPE_UDMAP_RX_CHAN),
500 .host_id = HOST_ID_MAIN_0_R5_2,
501 },
502 {
503 .start_resource = 92,
504 .num_resource = 48,
505 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
506 RESASG_SUBTYPE_UDMAP_RX_CHAN),
507 .host_id = HOST_ID_A72_2,
508 },
509
510 /* Main UDMA RxFlow assignment */
511 {
512 .start_resource = 140,
513 .num_resource = 64,
514 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
515 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
516 .host_id = HOST_ID_A72_2,
517 },
518 {
519 .start_resource = 204,
520 .num_resource = 32,
521 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
522 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
523 .host_id = HOST_ID_A72_3,
524 },
525 {
526 .start_resource = 236,
527 .num_resource = 32,
528 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
529 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
530 .host_id = HOST_ID_MAIN_0_R5_0,
531 },
532 {
533 .start_resource = 268,
534 .num_resource = 32,
535 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
536 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
537 .host_id = HOST_ID_MAIN_0_R5_2,
538 },
539
540 /* Main Ringacc */
541 /* Main Ringacc UHC TX rings */
542 {
543 .start_resource = 0,
544 .num_resource = 2,
545 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
546 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
547 .host_id = HOST_ID_A72_2,
548 },
549 {
550 .start_resource = 2,
551 .num_resource = 2,
552 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
553 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
554 .host_id = HOST_ID_MAIN_0_R5_2,
555 },
556
557 /* Main Ringacc HC TX rings */
558 {
559 .start_resource = 4,
560 .num_resource = 4,
561 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
562 RESASG_SUBTYPE_RA_UDMAP_TX_H),
563 .host_id = HOST_ID_A72_2,
564 },
565 {
566 .start_resource = 8,
567 .num_resource = 4,
568 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
569 RESASG_SUBTYPE_RA_UDMAP_TX_H),
570 .host_id = HOST_ID_MAIN_0_R5_0,
571 },
572 {
573 .start_resource = 12,
574 .num_resource = 4,
575 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
576 RESASG_SUBTYPE_RA_UDMAP_TX_H),
577 .host_id = HOST_ID_MAIN_0_R5_2,
578 },
579
580 /* Main Ringacc TX rings */
581 {
582 .start_resource = 16,
583 .num_resource = 2,
584 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
585 RESASG_SUBTYPE_RA_UDMAP_TX),
586 .host_id = HOST_ID_MCU_0_R5_0,
587 },
588 {
589 .start_resource = 18,
590 .num_resource = 2,
591 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
592 RESASG_SUBTYPE_RA_UDMAP_TX),
593 .host_id = HOST_ID_MCU_0_R5_2,
594 },
595 {
596 .start_resource = 20,
597 .num_resource = 6,
598 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
599 RESASG_SUBTYPE_RA_UDMAP_TX),
600 .host_id = HOST_ID_MAIN_1_R5_0,
601 },
602 {
603 .start_resource = 26,
604 .num_resource = 6,
605 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
606 RESASG_SUBTYPE_RA_UDMAP_TX),
607 .host_id = HOST_ID_MAIN_1_R5_2,
608 },
609 {
610 .start_resource = 32,
611 .num_resource = 6,
612 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
613 RESASG_SUBTYPE_RA_UDMAP_TX),
614 .host_id = HOST_ID_C7X_1,
615 },
616 {
617 .start_resource = 38,
618 .num_resource = 16,
619 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
620 RESASG_SUBTYPE_RA_UDMAP_TX),
621 .host_id = HOST_ID_C6X_0_1,
622 },
623 {
624 .start_resource = 54,
625 .num_resource = 8,
626 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
627 RESASG_SUBTYPE_RA_UDMAP_TX),
628 .host_id = HOST_ID_C6X_1_1,
629 },
630 {
631 .start_resource = 62,
632 .num_resource = 9,
633 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
634 RESASG_SUBTYPE_RA_UDMAP_TX),
635 .host_id = HOST_ID_MAIN_0_R5_0,
636 },
637 {
638 .start_resource = 71,
639 .num_resource = 9,
640 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
641 RESASG_SUBTYPE_RA_UDMAP_TX),
642 .host_id = HOST_ID_MAIN_0_R5_2,
643 },
644 {
645 .start_resource = 80,
646 .num_resource = 60,
647 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
648 RESASG_SUBTYPE_RA_UDMAP_TX),
649 .host_id = HOST_ID_A72_2,
650 },
651
652 /* Main Ringacc TX_EXT rings - NOT_PARTITIONED */
653 {
654 .start_resource = 140,
655 .num_resource = 160,
656 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
657 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
658 .host_id = HOST_ID_A72_2,
659 },
660
661 /* Main Ringacc UHC RX rings */
662 {
663 .start_resource = 300,
664 .num_resource = 2,
665 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
666 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
667 .host_id = HOST_ID_A72_2,
668 },
669 {
670 .start_resource = 302,
671 .num_resource = 2,
672 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
673 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
674 .host_id = HOST_ID_MAIN_0_R5_2,
675 },
676
677 /* Main Ringacc HC RX rings */
678 {
679 .start_resource = 304,
680 .num_resource = 4,
681 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
682 RESASG_SUBTYPE_RA_UDMAP_RX_H),
683 .host_id = HOST_ID_A72_2,
684 },
685 {
686 .start_resource = 308,
687 .num_resource = 4,
688 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
689 RESASG_SUBTYPE_RA_UDMAP_RX_H),
690 .host_id = HOST_ID_MAIN_0_R5_0,
691 },
692 {
693 .start_resource = 312,
694 .num_resource = 4,
695 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
696 RESASG_SUBTYPE_RA_UDMAP_RX_H),
697 .host_id = HOST_ID_MAIN_0_R5_2,
698 },
699
700 /* Main Ringacc RX rings */
701 {
702 .start_resource = 316,
703 .num_resource = 2,
704 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
705 RESASG_SUBTYPE_RA_UDMAP_RX),
706 .host_id = HOST_ID_MCU_0_R5_0,
707 },
708 {
709 .start_resource = 318,
710 .num_resource = 2,
711 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
712 RESASG_SUBTYPE_RA_UDMAP_RX),
713 .host_id = HOST_ID_MCU_0_R5_2,
714 },
715 {
716 .start_resource = 320,
717 .num_resource = 6,
718 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
719 RESASG_SUBTYPE_RA_UDMAP_RX),
720 .host_id = HOST_ID_MAIN_1_R5_0,
721 },
722 {
723 .start_resource = 326,
724 .num_resource = 6,
725 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
726 RESASG_SUBTYPE_RA_UDMAP_RX),
727 .host_id = HOST_ID_MAIN_1_R5_2,
728 },
729 {
730 .start_resource = 332,
731 .num_resource = 6,
732 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
733 RESASG_SUBTYPE_RA_UDMAP_RX),
734 .host_id = HOST_ID_C7X_1,
735 },
736 {
737 .start_resource = 338,
738 .num_resource = 16,
739 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
740 RESASG_SUBTYPE_RA_UDMAP_RX),
741 .host_id = HOST_ID_C6X_0_1,
742 },
743 {
744 .start_resource = 354,
745 .num_resource = 8,
746 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
747 RESASG_SUBTYPE_RA_UDMAP_RX),
748 .host_id = HOST_ID_C6X_1_1,
749 },
750 {
751 .start_resource = 362,
752 .num_resource = 15,
753 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
754 RESASG_SUBTYPE_RA_UDMAP_RX),
755 .host_id = HOST_ID_MAIN_0_R5_0,
756 },
757 {
758 .start_resource = 377,
759 .num_resource = 15,
760 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
761 RESASG_SUBTYPE_RA_UDMAP_RX),
762 .host_id = HOST_ID_MAIN_0_R5_2,
763 },
764 {
765 .start_resource = 392,
766 .num_resource = 48,
767 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
768 RESASG_SUBTYPE_RA_UDMAP_RX),
769 .host_id = HOST_ID_A72_2,
770 },
771
772 /* Main Ringacc GP rings */
773 {
774 .start_resource = 440,
775 .num_resource = 200,
776 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
777 RESASG_SUBTYPE_RA_GP),
778 .host_id = HOST_ID_A72_2,
779 },
780 {
781 .start_resource = 640,
782 .num_resource = 64,
783 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
784 RESASG_SUBTYPE_RA_GP),
785 .host_id = HOST_ID_A72_3,
786 },
787 {
788 .start_resource = 704,
789 .num_resource = 16,
790 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
791 RESASG_SUBTYPE_RA_GP),
792 .host_id = HOST_ID_MCU_0_R5_0,
793 },
794 {
795 .start_resource = 720,
796 .num_resource = 16,
797 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
798 RESASG_SUBTYPE_RA_GP),
799 .host_id = HOST_ID_MCU_0_R5_2,
800 },
801 {
802 .start_resource = 736,
803 .num_resource = 64,
804 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
805 RESASG_SUBTYPE_RA_GP),
806 .host_id = HOST_ID_MAIN_0_R5_0,
807 },
808 {
809 .start_resource = 800,
810 .num_resource = 32,
811 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
812 RESASG_SUBTYPE_RA_GP),
813 .host_id = HOST_ID_MAIN_0_R5_2,
814 },
815 {
816 .start_resource = 832,
817 .num_resource = 16,
818 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
819 RESASG_SUBTYPE_RA_GP),
820 .host_id = HOST_ID_MAIN_1_R5_0,
821 },
822 {
823 .start_resource = 848,
824 .num_resource = 16,
825 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
826 RESASG_SUBTYPE_RA_GP),
827 .host_id = HOST_ID_MAIN_1_R5_2,
828 },
829 {
830 .start_resource = 864,
831 .num_resource = 16,
832 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
833 RESASG_SUBTYPE_RA_GP),
834 .host_id = HOST_ID_C7X_1,
835 },
836 {
837 .start_resource = 880,
838 .num_resource = 16,
839 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
840 RESASG_SUBTYPE_RA_GP),
841 .host_id = HOST_ID_C6X_0_1,
842 },
843 {
844 .start_resource = 896,
845 .num_resource = 16,
846 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
847 RESASG_SUBTYPE_RA_GP),
848 .host_id = HOST_ID_C6X_1_1,
849 },
850
851 /* MCU UDMA */
852 /* MCU UDMA HC TX channel assignment */
853 {
854 .start_resource = 0,
855 .num_resource = 2,
856 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
857 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
858 .host_id = HOST_ID_MCU_0_R5_0,
859 },
860
861 /* MCU UDMA normal TX channel assignment */
862 {
863 .start_resource = 2,
864 .num_resource = 12,
865 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
866 RESASG_SUBTYPE_UDMAP_TX_CHAN),
867 .host_id = HOST_ID_A72_2,
868 },
869 {
870 .start_resource = 14,
871 .num_resource = 6,
872 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
873 RESASG_SUBTYPE_UDMAP_TX_CHAN),
874 .host_id = HOST_ID_A72_3,
875 },
876 {
877 .start_resource = 20,
878 .num_resource = 5,
879 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
880 RESASG_SUBTYPE_UDMAP_TX_CHAN),
881 .host_id = HOST_ID_MCU_0_R5_0,
882 },
883 {
884 .start_resource = 25,
885 .num_resource = 3,
886 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
887 RESASG_SUBTYPE_UDMAP_TX_CHAN),
888 .host_id = HOST_ID_MCU_0_R5_2,
889 },
890 {
891 .start_resource = 28,
892 .num_resource = 3,
893 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
894 RESASG_SUBTYPE_UDMAP_TX_CHAN),
895 .host_id = HOST_ID_MAIN_0_R5_0,
896 },
897 {
898 .start_resource = 31,
899 .num_resource = 2,
900 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
901 RESASG_SUBTYPE_UDMAP_TX_CHAN),
902 .host_id = HOST_ID_MAIN_0_R5_2,
903 },
904 {
905 .start_resource = 33,
906 .num_resource = 3,
907 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
908 RESASG_SUBTYPE_UDMAP_TX_CHAN),
909 .host_id = HOST_ID_MAIN_1_R5_0,
910 },
911 {
912 .start_resource = 36,
913 .num_resource = 2,
914 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
915 RESASG_SUBTYPE_UDMAP_TX_CHAN),
916 .host_id = HOST_ID_MAIN_1_R5_2,
917 },
918 {
919 .start_resource = 38,
920 .num_resource = 3,
921 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
922 RESASG_SUBTYPE_UDMAP_TX_CHAN),
923 .host_id = HOST_ID_C7X_1,
924 },
925 {
926 .start_resource = 41,
927 .num_resource = 3,
928 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
929 RESASG_SUBTYPE_UDMAP_TX_CHAN),
930 .host_id = HOST_ID_C6X_0_1,
931 },
932 {
933 .start_resource = 44,
934 .num_resource = 2,
935 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
936 RESASG_SUBTYPE_UDMAP_TX_CHAN),
937 .host_id = HOST_ID_C6X_1_1,
938 },
939
940 /* MCU UDMA HC RX channel assignment */
941 {
942 .start_resource = 0,
943 .num_resource = 2,
944 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
945 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
946 .host_id = HOST_ID_MCU_0_R5_0,
947 },
948
949 /* MCU UDMA normal RX channel assignment */
950 {
951 .start_resource = 2,
952 .num_resource = 12,
953 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
954 RESASG_SUBTYPE_UDMAP_RX_CHAN),
955 .host_id = HOST_ID_A72_2,
956 },
957 {
958 .start_resource = 14,
959 .num_resource = 6,
960 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
961 RESASG_SUBTYPE_UDMAP_RX_CHAN),
962 .host_id = HOST_ID_A72_3,
963 },
964 {
965 .start_resource = 20,
966 .num_resource = 5,
967 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
968 RESASG_SUBTYPE_UDMAP_RX_CHAN),
969 .host_id = HOST_ID_MCU_0_R5_0,
970 },
971 {
972 .start_resource = 25,
973 .num_resource = 3,
974 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
975 RESASG_SUBTYPE_UDMAP_RX_CHAN),
976 .host_id = HOST_ID_MCU_0_R5_2,
977 },
978 {
979 .start_resource = 28,
980 .num_resource = 3,
981 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
982 RESASG_SUBTYPE_UDMAP_RX_CHAN),
983 .host_id = HOST_ID_MAIN_0_R5_0,
984 },
985 {
986 .start_resource = 31,
987 .num_resource = 2,
988 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
989 RESASG_SUBTYPE_UDMAP_RX_CHAN),
990 .host_id = HOST_ID_MAIN_0_R5_2,
991 },
992 {
993 .start_resource = 33,
994 .num_resource = 3,
995 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
996 RESASG_SUBTYPE_UDMAP_RX_CHAN),
997 .host_id = HOST_ID_MAIN_1_R5_0,
998 },
999 {
1000 .start_resource = 36,
1001 .num_resource = 2,
1002 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1003 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1004 .host_id = HOST_ID_MAIN_1_R5_2,
1005 },
1006 {
1007 .start_resource = 38,
1008 .num_resource = 3,
1009 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1010 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1011 .host_id = HOST_ID_C7X_1,
1012 },
1013 {
1014 .start_resource = 41,
1015 .num_resource = 2,
1016 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1017 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1018 .host_id = HOST_ID_C6X_0_1,
1019 },
1020 {
1021 .start_resource = 43,
1022 .num_resource = 2,
1023 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1024 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1025 .host_id = HOST_ID_C6X_1_1,
1026 },
1027
1028 /* MCU UDMA RxFlow assignment */
1029 {
1030 .start_resource = 48,
1031 .num_resource = 8,
1032 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1033 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1034 .host_id = HOST_ID_A72_2,
1035 },
1036 {
1037 .start_resource = 56,
1038 .num_resource = 4,
1039 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1040 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1041 .host_id = HOST_ID_A72_3,
1042 },
1043 {
1044 .start_resource = 60,
1045 .num_resource = 8,
1046 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1047 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1048 .host_id = HOST_ID_MCU_0_R5_0,
1049 },
1050 {
1051 .start_resource = 68,
1052 .num_resource = 8,
1053 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1054 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1055 .host_id = HOST_ID_MCU_0_R5_2,
1056 },
1057 {
1058 .start_resource = 76,
1059 .num_resource = 8,
1060 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1061 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1062 .host_id = HOST_ID_MAIN_0_R5_0,
1063 },
1064 {
1065 .start_resource = 84,
1066 .num_resource = 8,
1067 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_UDMAP_0,
1068 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1069 .host_id = HOST_ID_MAIN_0_R5_2,
1070 },
1071
1072 /* MCU Ringacc */
1073 /* MCU Ringacc HC TX rings */
1074 {
1075 .start_resource = 0,
1076 .num_resource = 2,
1077 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1078 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1079 .host_id = HOST_ID_MCU_0_R5_0,
1080 },
1081
1082 /* MCU Ringacc TX rings */
1083 {
1084 .start_resource = 2,
1085 .num_resource = 12,
1086 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1087 RESASG_SUBTYPE_RA_UDMAP_TX),
1088 .host_id = HOST_ID_A72_2,
1089 },
1090 {
1091 .start_resource = 14,
1092 .num_resource = 6,
1093 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1094 RESASG_SUBTYPE_RA_UDMAP_TX),
1095 .host_id = HOST_ID_A72_3,
1096 },
1097 {
1098 .start_resource = 20,
1099 .num_resource = 5,
1100 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1101 RESASG_SUBTYPE_RA_UDMAP_TX),
1102 .host_id = HOST_ID_MCU_0_R5_0,
1103 },
1104 {
1105 .start_resource = 25,
1106 .num_resource = 3,
1107 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1108 RESASG_SUBTYPE_RA_UDMAP_TX),
1109 .host_id = HOST_ID_MCU_0_R5_2,
1110 },
1111 {
1112 .start_resource = 28,
1113 .num_resource = 3,
1114 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1115 RESASG_SUBTYPE_RA_UDMAP_TX),
1116 .host_id = HOST_ID_MAIN_0_R5_0,
1117 },
1118 {
1119 .start_resource = 31,
1120 .num_resource = 2,
1121 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1122 RESASG_SUBTYPE_RA_UDMAP_TX),
1123 .host_id = HOST_ID_MAIN_0_R5_2,
1124 },
1125 {
1126 .start_resource = 33,
1127 .num_resource = 3,
1128 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1129 RESASG_SUBTYPE_RA_UDMAP_TX),
1130 .host_id = HOST_ID_MAIN_1_R5_0,
1131 },
1132 {
1133 .start_resource = 36,
1134 .num_resource = 2,
1135 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1136 RESASG_SUBTYPE_RA_UDMAP_TX),
1137 .host_id = HOST_ID_MAIN_1_R5_2,
1138 },
1139 {
1140 .start_resource = 38,
1141 .num_resource = 3,
1142 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1143 RESASG_SUBTYPE_RA_UDMAP_TX),
1144 .host_id = HOST_ID_C7X_1,
1145 },
1146 {
1147 .start_resource = 41,
1148 .num_resource = 3,
1149 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1150 RESASG_SUBTYPE_RA_UDMAP_TX),
1151 .host_id = HOST_ID_C6X_0_1,
1152 },
1153 {
1154 .start_resource = 44,
1155 .num_resource = 2,
1156 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1157 RESASG_SUBTYPE_RA_UDMAP_TX),
1158 .host_id = HOST_ID_C6X_1_1,
1159 },
1160
1161 /* MCU Ringacc HC RX rings */
1162 {
1163 .start_resource = 48,
1164 .num_resource = 2,
1165 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1166 RESASG_SUBTYPE_RA_UDMAP_RX_H),
1167 .host_id = HOST_ID_MCU_0_R5_0,
1168 },
1169
1170 /* MCU Ringacc RX rings */
1171 {
1172 .start_resource = 50,
1173 .num_resource = 12,
1174 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1175 RESASG_SUBTYPE_RA_UDMAP_RX),
1176 .host_id = HOST_ID_A72_2,
1177 },
1178 {
1179 .start_resource = 62,
1180 .num_resource = 6,
1181 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1182 RESASG_SUBTYPE_RA_UDMAP_RX),
1183 .host_id = HOST_ID_A72_3,
1184 },
1185 {
1186 .start_resource = 68,
1187 .num_resource = 5,
1188 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1189 RESASG_SUBTYPE_RA_UDMAP_RX),
1190 .host_id = HOST_ID_MCU_0_R5_0,
1191 },
1192 {
1193 .start_resource = 73,
1194 .num_resource = 3,
1195 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1196 RESASG_SUBTYPE_RA_UDMAP_RX),
1197 .host_id = HOST_ID_MCU_0_R5_2,
1198 },
1199 {
1200 .start_resource = 76,
1201 .num_resource = 3,
1202 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1203 RESASG_SUBTYPE_RA_UDMAP_RX),
1204 .host_id = HOST_ID_MAIN_0_R5_0,
1205 },
1206 {
1207 .start_resource = 79,
1208 .num_resource = 2,
1209 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1210 RESASG_SUBTYPE_RA_UDMAP_RX),
1211 .host_id = HOST_ID_MAIN_0_R5_2,
1212 },
1213 {
1214 .start_resource = 81,
1215 .num_resource = 3,
1216 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1217 RESASG_SUBTYPE_RA_UDMAP_RX),
1218 .host_id = HOST_ID_MAIN_1_R5_0,
1219 },
1220 {
1221 .start_resource = 84,
1222 .num_resource = 2,
1223 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1224 RESASG_SUBTYPE_RA_UDMAP_RX),
1225 .host_id = HOST_ID_MAIN_1_R5_2,
1226 },
1227 {
1228 .start_resource = 86,
1229 .num_resource = 3,
1230 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1231 RESASG_SUBTYPE_RA_UDMAP_RX),
1232 .host_id = HOST_ID_C7X_1,
1233 },
1234 {
1235 .start_resource = 89,
1236 .num_resource = 2,
1237 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1238 RESASG_SUBTYPE_RA_UDMAP_RX),
1239 .host_id = HOST_ID_C6X_0_1,
1240 },
1241 {
1242 .start_resource = 91,
1243 .num_resource = 2,
1244 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1245 RESASG_SUBTYPE_RA_UDMAP_RX),
1246 .host_id = HOST_ID_C6X_1_1,
1247 },
1248
1249 /* MCU Ringacc GP rings */
1250 {
1251 .start_resource = 96,
1252 .num_resource = 20,
1253 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1254 RESASG_SUBTYPE_RA_GP),
1255 .host_id = HOST_ID_A72_2,
1256 },
1257 {
1258 .start_resource = 116,
1259 .num_resource = 8,
1260 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1261 RESASG_SUBTYPE_RA_GP),
1262 .host_id = HOST_ID_A72_3,
1263 },
1264 {
1265 .start_resource = 124,
1266 .num_resource = 32,
1267 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1268 RESASG_SUBTYPE_RA_GP),
1269 .host_id = HOST_ID_MCU_0_R5_0,
1270 },
1271 {
1272 .start_resource = 156,
1273 .num_resource = 16,
1274 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1275 RESASG_SUBTYPE_RA_GP),
1276 .host_id = HOST_ID_MCU_0_R5_2,
1277 },
1278 {
1279 .start_resource = 172,
1280 .num_resource = 16,
1281 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1282 RESASG_SUBTYPE_RA_GP),
1283 .host_id = HOST_ID_MAIN_0_R5_0,
1284 },
1285 {
1286 .start_resource = 188,
1287 .num_resource = 8,
1288 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1289 RESASG_SUBTYPE_RA_GP),
1290 .host_id = HOST_ID_MAIN_0_R5_2,
1291 },
1292 {
1293 .start_resource = 196,
1294 .num_resource = 16,
1295 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1296 RESASG_SUBTYPE_RA_GP),
1297 .host_id = HOST_ID_MAIN_1_R5_0,
1298 },
1299 {
1300 .start_resource = 212,
1301 .num_resource = 8,
1302 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1303 RESASG_SUBTYPE_RA_GP),
1304 .host_id = HOST_ID_MAIN_1_R5_2,
1305 },
1306 {
1307 .start_resource = 220,
1308 .num_resource = 8,
1309 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1310 RESASG_SUBTYPE_RA_GP),
1311 .host_id = HOST_ID_C7X_1,
1312 },
1313 {
1314 .start_resource = 228,
1315 .num_resource = 8,
1316 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1317 RESASG_SUBTYPE_RA_GP),
1318 .host_id = HOST_ID_C6X_0_1,
1319 },
1320 {
1321 .start_resource = 236,
1322 .num_resource = 8,
1323 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
1324 RESASG_SUBTYPE_RA_GP),
1325 .host_id = HOST_ID_C6X_1_1,
1326 },
1327
1328 /* MCU NAV INTA assignment */
1329 /* MCU NAV INTA VINT */
1330 {
1331 .start_resource = 8,
1332 .num_resource = 32,
1333 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1334 RESASG_SUBTYPE_IA_VINT),
1335 .host_id = HOST_ID_A72_2,
1336 },
1337 {
1338 .start_resource = 40,
1339 .num_resource = 16,
1340 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1341 RESASG_SUBTYPE_IA_VINT),
1342 .host_id = HOST_ID_A72_3,
1343 },
1344 {
1345 .start_resource = 56,
1346 .num_resource = 64,
1347 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1348 RESASG_SUBTYPE_IA_VINT),
1349 .host_id = HOST_ID_MCU_0_R5_0,
1350 },
1351 {
1352 .start_resource = 120,
1353 .num_resource = 32,
1354 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1355 RESASG_SUBTYPE_IA_VINT),
1356 .host_id = HOST_ID_MCU_0_R5_2,
1357 },
1358 {
1359 .start_resource = 152,
1360 .num_resource = 16,
1361 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1362 RESASG_SUBTYPE_IA_VINT),
1363 .host_id = HOST_ID_MAIN_0_R5_0,
1364 },
1365 {
1366 .start_resource = 168,
1367 .num_resource = 16,
1368 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1369 RESASG_SUBTYPE_IA_VINT),
1370 .host_id = HOST_ID_MAIN_0_R5_2,
1371 },
1372 {
1373 .start_resource = 184,
1374 .num_resource = 16,
1375 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1376 RESASG_SUBTYPE_IA_VINT),
1377 .host_id = HOST_ID_MAIN_1_R5_0,
1378 },
1379 {
1380 .start_resource = 200,
1381 .num_resource = 16,
1382 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1383 RESASG_SUBTYPE_IA_VINT),
1384 .host_id = HOST_ID_MAIN_1_R5_2,
1385 },
1386 {
1387 .start_resource = 216,
1388 .num_resource = 8,
1389 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1390 RESASG_SUBTYPE_IA_VINT),
1391 .host_id = HOST_ID_C7X_1,
1392 },
1393 {
1394 .start_resource = 224,
1395 .num_resource = 16,
1396 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1397 RESASG_SUBTYPE_IA_VINT),
1398 .host_id = HOST_ID_C6X_0_1,
1399 },
1400 {
1401 .start_resource = 240,
1402 .num_resource = 16,
1403 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1404 RESASG_SUBTYPE_IA_VINT),
1405 .host_id = HOST_ID_C6X_1_1,
1406 },
1407
1408 /* MCU NAV INTA SEVT */
1409 {
1410 .start_resource = 16392,
1411 .num_resource = 128,
1412 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1413 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1414 .host_id = HOST_ID_A72_2,
1415 },
1416 {
1417 .start_resource = 16520,
1418 .num_resource = 128,
1419 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1420 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1421 .host_id = HOST_ID_A72_3,
1422 },
1423 {
1424 .start_resource = 16648,
1425 .num_resource = 256,
1426 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1427 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1428 .host_id = HOST_ID_MCU_0_R5_0,
1429 },
1430 {
1431 .start_resource = 16904,
1432 .num_resource = 256,
1433 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1434 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1435 .host_id = HOST_ID_MCU_0_R5_2,
1436 },
1437 {
1438 .start_resource = 17160,
1439 .num_resource = 128,
1440 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1441 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1442 .host_id = HOST_ID_MAIN_0_R5_0,
1443 },
1444 {
1445 .start_resource = 17288,
1446 .num_resource = 128,
1447 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1448 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1449 .host_id = HOST_ID_MAIN_0_R5_2,
1450 },
1451 {
1452 .start_resource = 17416,
1453 .num_resource = 128,
1454 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1455 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1456 .host_id = HOST_ID_MAIN_1_R5_0,
1457 },
1458 {
1459 .start_resource = 17544,
1460 .num_resource = 128,
1461 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1462 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1463 .host_id = HOST_ID_MAIN_1_R5_2,
1464 },
1465 {
1466 .start_resource = 17672,
1467 .num_resource = 64,
1468 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1469 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1470 .host_id = HOST_ID_C7X_1,
1471 },
1472 {
1473 .start_resource = 17736,
1474 .num_resource = 64,
1475 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1476 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1477 .host_id = HOST_ID_C6X_0_1,
1478 },
1479 {
1480 .start_resource = 17800,
1481 .num_resource = 64,
1482 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_INTAGGR_0,
1483 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1484 .host_id = HOST_ID_C6X_1_1,
1485 },
1486
1487 /* CPU specific interrupt routers */
1488 /* MCU R5_0_0 CPU INTR */
1489 {
1490 .start_resource = 68U,
1491 .num_resource = 28U,
1492 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
1493 RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
1494 .host_id = HOST_ID_MCU_0_R5_0,
1495 },
1496 {
1497 .start_resource = 124U,
1498 .num_resource = 16U,
1499 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
1500 RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
1501 .host_id = HOST_ID_MCU_0_R5_0,
1502 },
1503 {
1504 .start_resource = 160U,
1505 .num_resource = 64U,
1506 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
1507 RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
1508 .host_id = HOST_ID_MCU_0_R5_0,
1509 },
1510 {
1511 .start_resource = 224U,
1512 .num_resource = 48U,
1513 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
1514 RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
1515 .host_id = HOST_ID_MCU_0_R5_0,
1516 },
1517 {
1518 .start_resource = 376U,
1519 .num_resource = 8U,
1520 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
1521 RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1522 .host_id = HOST_ID_MCU_0_R5_0,
1523 },
1524
1525 /* MCU R5_0_1 CPU INTR */
1526 {
1527 .start_resource = 68U,
1528 .num_resource = 28U,
1529 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
1530 RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
1531 .host_id = HOST_ID_MCU_0_R5_2,
1532 },
1533 {
1534 .start_resource = 124U,
1535 .num_resource = 16U,
1536 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
1537 RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
1538 .host_id = HOST_ID_MCU_0_R5_2,
1539 },
1540 {
1541 .start_resource = 160U,
1542 .num_resource = 64U,
1543 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
1544 RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
1545 .host_id = HOST_ID_MCU_0_R5_2,
1546 },
1547 {
1548 .start_resource = 224U,
1549 .num_resource = 48U,
1550 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
1551 RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
1552 .host_id = HOST_ID_MCU_0_R5_2,
1553 },
1554 {
1555 .start_resource = 376U,
1556 .num_resource = 8U,
1557 .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
1558 RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1559 .host_id = HOST_ID_MCU_0_R5_2,
1560 },
1561
1562 /* Main R5_0_0 CPU INTR */
1563 {
1564 .start_resource = 176U,
1565 .num_resource = 16U,
1566 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE0,
1567 RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
1568 .host_id = HOST_ID_MAIN_0_R5_0,
1569 },
1570 {
1571 .start_resource = 228U,
1572 .num_resource = 28U,
1573 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE0,
1574 RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1575 .host_id = HOST_ID_MAIN_0_R5_0,
1576 },
1577 {
1578 .start_resource = 256U,
1579 .num_resource = 256U,
1580 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE0,
1581 RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0),
1582 .host_id = HOST_ID_MAIN_0_R5_0,
1583 },
1584
1585 /* Main R5_0_1 CPU INTR */
1586 {
1587 .start_resource = 176U,
1588 .num_resource = 16U,
1589 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE1,
1590 RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
1591 .host_id = HOST_ID_MAIN_0_R5_2,
1592 },
1593 {
1594 .start_resource = 228U,
1595 .num_resource = 28U,
1596 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE1,
1597 RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1598 .host_id = HOST_ID_MAIN_0_R5_2,
1599 },
1600 {
1601 .start_resource = 256U,
1602 .num_resource = 256U,
1603 .type = RESASG_UTYPE(J721E_DEV_R5FSS0_CORE1,
1604 RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0),
1605 .host_id = HOST_ID_MAIN_0_R5_2,
1606 },
1607
1608 /* Main R5_1_0 CPU INTR */
1609 {
1610 .start_resource = 176U,
1611 .num_resource = 16U,
1612 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE0,
1613 RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
1614 .host_id = HOST_ID_MAIN_1_R5_0,
1615 },
1616 {
1617 .start_resource = 228U,
1618 .num_resource = 28U,
1619 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE0,
1620 RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1621 .host_id = HOST_ID_MAIN_1_R5_0,
1622 },
1623 {
1624 .start_resource = 256U,
1625 .num_resource = 256U,
1626 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE0,
1627 RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0),
1628 .host_id = HOST_ID_MAIN_1_R5_0,
1629 },
1630
1631 /* Main R5_1_1 CPU INTR */
1632 {
1633 .start_resource = 176U,
1634 .num_resource = 16U,
1635 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE1,
1636 RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
1637 .host_id = HOST_ID_MAIN_1_R5_2,
1638 },
1639 {
1640 .start_resource = 228U,
1641 .num_resource = 28U,
1642 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE1,
1643 RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
1644 .host_id = HOST_ID_MAIN_1_R5_2,
1645 },
1646 {
1647 .start_resource = 256U,
1648 .num_resource = 256U,
1649 .type = RESASG_UTYPE(J721E_DEV_R5FSS1_CORE1,
1650 RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0),
1651 .host_id = HOST_ID_MAIN_1_R5_2,
1652 },
1653
1654 /* C6X_0 CPU INTR */
1655 {
1656 .start_resource = 8U,
1657 .num_resource = 1U,
1658 .type = RESASG_UTYPE(J721E_DEV_C66SS0_CORE0,
1659 RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS0_INTROUTER0),
1660 .host_id = HOST_ID_C6X_0_1,
1661 },
1662 {
1663 .start_resource = 15U,
1664 .num_resource = 81U,
1665 .type = RESASG_UTYPE(J721E_DEV_C66SS0_CORE0,
1666 RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS0_INTROUTER0),
1667 .host_id = HOST_ID_C6X_0_1,
1668 },
1669 {
1670 .start_resource = 99U,
1671 .num_resource = 1U,
1672 .type = RESASG_UTYPE(J721E_DEV_C66SS0_CORE0,
1673 RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS0_INTROUTER0),
1674 .host_id = HOST_ID_C6X_0_1,
1675 },
1676 {
1677 .start_resource = 102U,
1678 .num_resource = 8U,
1679 .type = RESASG_UTYPE(J721E_DEV_C66SS0_CORE0,
1680 RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS0_INTROUTER0),
1681 .host_id = HOST_ID_C6X_0_1,
1682 },
1683 {
1684 .start_resource = 114U,
1685 .num_resource = 2U,
1686 .type = RESASG_UTYPE(J721E_DEV_C66SS0_CORE0,
1687 RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS0_INTROUTER0),
1688 .host_id = HOST_ID_C6X_0_1,
1689 },
1690
1691 /* C6X_1 CPU INTR */
1692 {
1693 .start_resource = 8U,
1694 .num_resource = 1U,
1695 .type = RESASG_UTYPE(J721E_DEV_C66SS1_CORE0,
1696 RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS1_INTROUTER0),
1697 .host_id = HOST_ID_C6X_1_1,
1698 },
1699 {
1700 .start_resource = 15U,
1701 .num_resource = 81U,
1702 .type = RESASG_UTYPE(J721E_DEV_C66SS1_CORE0,
1703 RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS1_INTROUTER0),
1704 .host_id = HOST_ID_C6X_1_1,
1705 },
1706 {
1707 .start_resource = 99U,
1708 .num_resource = 1U,
1709 .type = RESASG_UTYPE(J721E_DEV_C66SS1_CORE0,
1710 RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS1_INTROUTER0),
1711 .host_id = HOST_ID_C6X_1_1,
1712 },
1713 {
1714 .start_resource = 102U,
1715 .num_resource = 8U,
1716 .type = RESASG_UTYPE(J721E_DEV_C66SS1_CORE0,
1717 RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS1_INTROUTER0),
1718 .host_id = HOST_ID_C6X_1_1,
1719 },
1720 {
1721 .start_resource = 114U,
1722 .num_resource = 2U,
1723 .type = RESASG_UTYPE(J721E_DEV_C66SS1_CORE0,
1724 RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS1_INTROUTER0),
1725 .host_id = HOST_ID_C6X_1_1,
1726 },
1727 },
1728};
diff --git a/soc/j721e/evm/sec-cfg.c b/soc/j721e/evm/sec-cfg.c
new file mode 100644
index 000000000..b628d8b34
--- /dev/null
+++ b/soc/j721e/evm/sec-cfg.c
@@ -0,0 +1,62 @@
1/*
2 * K3 System Firmware Security Configuration Data
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37
38const struct boardcfg_security j721e_boardcfg_security_data = {
39 /* boardcfg_abi_rev */
40 .rev = {
41 .boardcfg_abi_maj = 0x0,
42 .boardcfg_abi_min = 0x1,
43 },
44
45 /* boardcfg_proc_acl */
46 .processor_acl_list = {
47 .subhdr = {
48 .magic = BOARDCFG_PROC_ACL_MAGIC_NUM,
49 .size = sizeof(struct boardcfg_proc_acl),
50 },
51 .proc_acl_entries = {{ 0 } },
52 },
53
54 /* boardcfg_host_hierarchy */
55 .host_hierarchy = {
56 .subhdr = {
57 .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_host_hierarchy),
59 },
60 .host_hierarchy_entries = {{ 0 } },
61 },
62};
diff --git a/soc/j721e/evm/sysfw_img_cfg.h b/soc/j721e/evm/sysfw_img_cfg.h
new file mode 100644
index 000000000..45dcd7483
--- /dev/null
+++ b/soc/j721e/evm/sysfw_img_cfg.h
@@ -0,0 +1,40 @@
1/*
2 * K3 System Firmware Configuration Data
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H
37
38#define BOARDCFG_RM_RESASG_ENTRIES 224
39
40#endif /* SYSFW_IMG_CFG_H */
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