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authorSuman Anna2020-05-04 16:08:42 -0500
committerDave Gerlach2020-05-05 13:15:15 -0500
commit88220262fd84fcedfec1d906aa1f1e580e0bf5fc (patch)
treec3063465b7bf02aa13c2a6b89d9d0297b8630549 /soc
parent6408ecb8c790cbec0aa41e93565d5e3d4cbe5776 (diff)
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am65x,am65x_sr2: Fix MAIN2MCU interrupt routers for both R5F cores
Each of the MCU R5F cores are represented by different HOST_IDs, and the ABI 3.0 RM changes have reassigned all the MAIN2MCU interrupt router outputs back to only the MCU R5F Core0. This breaks the IPC use-cases when the MCU R5FSS cluster is configured for Split-mode. Partition both the MAIN2MCU_LVL and MAIN2MCU_PLS Interrupt Router outputs equally between the non-secure contexts of both the MCU R5F cores. Signed-off-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'soc')
-rw-r--r--soc/am65x/evm/rm-cfg.c18
-rw-r--r--soc/am65x/evm/sysfw_img_cfg.h2
-rw-r--r--soc/am65x_sr2/evm/rm-cfg.c18
-rw-r--r--soc/am65x_sr2/evm/sysfw_img_cfg.h2
4 files changed, 34 insertions, 6 deletions
diff --git a/soc/am65x/evm/rm-cfg.c b/soc/am65x/evm/rm-cfg.c
index 5abb3c31c..f14e969d8 100644
--- a/soc/am65x/evm/rm-cfg.c
+++ b/soc/am65x/evm/rm-cfg.c
@@ -367,19 +367,33 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = {
367 .num_resource = 32, 367 .num_resource = 32,
368 .host_id = HOST_ID_A53_2, 368 .host_id = HOST_ID_A53_2,
369 }, 369 },
370 /* Main 2 MCU level IRQ IR */
370 { 371 {
371 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 372 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
372 .start_resource = 0, 373 .start_resource = 0,
373 .num_resource = 64, 374 .num_resource = 32,
374 .host_id = HOST_ID_R5_0, 375 .host_id = HOST_ID_R5_0,
375 }, 376 },
376 { 377 {
378 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
379 .start_resource = 32,
380 .num_resource = 32,
381 .host_id = HOST_ID_R5_2,
382 },
383 /* Main 2 MCU Pulse IRQ IR */
384 {
377 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 385 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
378 .start_resource = 0, 386 .start_resource = 0,
379 .num_resource = 48, 387 .num_resource = 24,
380 .host_id = HOST_ID_R5_0, 388 .host_id = HOST_ID_R5_0,
381 }, 389 },
382 { 390 {
391 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
392 .start_resource = 24,
393 .num_resource = 24,
394 .host_id = HOST_ID_R5_2,
395 },
396 {
383 .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 397 .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
384 .start_resource = 0, 398 .start_resource = 0,
385 .num_resource = 32, 399 .num_resource = 32,
diff --git a/soc/am65x/evm/sysfw_img_cfg.h b/soc/am65x/evm/sysfw_img_cfg.h
index 4dfd85879..c651fcecd 100644
--- a/soc/am65x/evm/sysfw_img_cfg.h
+++ b/soc/am65x/evm/sysfw_img_cfg.h
@@ -35,6 +35,6 @@
35#ifndef SYSFW_IMG_CFG_H 35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 36#define SYSFW_IMG_CFG_H
37 37
38#define BOARDCFG_RM_RESASG_ENTRIES 55 38#define BOARDCFG_RM_RESASG_ENTRIES 57
39 39
40#endif /* SYSFW_IMG_CFG_H */ 40#endif /* SYSFW_IMG_CFG_H */
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c
index 5abb3c31c..f14e969d8 100644
--- a/soc/am65x_sr2/evm/rm-cfg.c
+++ b/soc/am65x_sr2/evm/rm-cfg.c
@@ -367,19 +367,33 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = {
367 .num_resource = 32, 367 .num_resource = 32,
368 .host_id = HOST_ID_A53_2, 368 .host_id = HOST_ID_A53_2,
369 }, 369 },
370 /* Main 2 MCU level IRQ IR */
370 { 371 {
371 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 372 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
372 .start_resource = 0, 373 .start_resource = 0,
373 .num_resource = 64, 374 .num_resource = 32,
374 .host_id = HOST_ID_R5_0, 375 .host_id = HOST_ID_R5_0,
375 }, 376 },
376 { 377 {
378 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
379 .start_resource = 32,
380 .num_resource = 32,
381 .host_id = HOST_ID_R5_2,
382 },
383 /* Main 2 MCU Pulse IRQ IR */
384 {
377 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 385 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
378 .start_resource = 0, 386 .start_resource = 0,
379 .num_resource = 48, 387 .num_resource = 24,
380 .host_id = HOST_ID_R5_0, 388 .host_id = HOST_ID_R5_0,
381 }, 389 },
382 { 390 {
391 .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
392 .start_resource = 24,
393 .num_resource = 24,
394 .host_id = HOST_ID_R5_2,
395 },
396 {
383 .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), 397 .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
384 .start_resource = 0, 398 .start_resource = 0,
385 .num_resource = 32, 399 .num_resource = 32,
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h
index f1a01f8ea..2f8203fad 100644
--- a/soc/am65x_sr2/evm/sysfw_img_cfg.h
+++ b/soc/am65x_sr2/evm/sysfw_img_cfg.h
@@ -35,6 +35,6 @@
35#ifndef SYSFW_IMG_CFG_H 35#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 36#define SYSFW_IMG_CFG_H
37 37
38#define BOARDCFG_RM_RESASG_ENTRIES 55 38#define BOARDCFG_RM_RESASG_ENTRIES 57
39 39
40#endif /* SYSFW_IMG_CFG_H */ 40#endif /* SYSFW_IMG_CFG_H */