diff options
author | Aswath Govindraju | 2022-01-27 05:28:13 -0600 |
---|---|---|
committer | Vignesh Raghavendra | 2022-01-30 23:47:25 -0600 |
commit | 9abbe130d47a7fa6f8e02b740ad3ad27bc81d327 (patch) | |
tree | 8a9098c82d3f7bc05b96830d7005c7723fe9fd86 /soc | |
parent | 2173164dfc6e46eff6a8a0901722facd9771421d (diff) | |
download | k3-image-gen-9abbe130d47a7fa6f8e02b740ad3ad27bc81d327.tar.gz k3-image-gen-9abbe130d47a7fa6f8e02b740ad3ad27bc81d327.tar.xz k3-image-gen-9abbe130d47a7fa6f8e02b740ad3ad27bc81d327.zip |
soc: j721s2: Introduce support for EVM
Add support for j721s2 SoC. Use the baseport, PM and security board configs
from sysfw test repo and, generated RM config provided by the sysconfig
tool.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'soc')
-rw-r--r-- | soc/j721s2/Makefile | 44 | ||||
-rw-r--r-- | soc/j721s2/evm/board-cfg.c | 92 | ||||
-rw-r--r-- | soc/j721s2/evm/pm-cfg.c | 43 | ||||
-rw-r--r-- | soc/j721s2/evm/rm-cfg.c | 3058 | ||||
-rw-r--r-- | soc/j721s2/evm/sec-cfg.c | 117 | ||||
-rw-r--r-- | soc/j721s2/evm/sysfw_img_cfg.h | 42 |
6 files changed, 3396 insertions, 0 deletions
diff --git a/soc/j721s2/Makefile b/soc/j721s2/Makefile new file mode 100644 index 000000000..7301a593d --- /dev/null +++ b/soc/j721s2/Makefile | |||
@@ -0,0 +1,44 @@ | |||
1 | # | ||
2 | # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
3 | # | ||
4 | # Redistribution and use in source and binary forms, with or without | ||
5 | # modification, are permitted provided that the following conditions | ||
6 | # are met: | ||
7 | # | ||
8 | # Redistributions of source code must retain the above copyright | ||
9 | # notice, this list of conditions and the following disclaimer. | ||
10 | # | ||
11 | # Redistributions in binary form must reproduce the above copyright | ||
12 | # notice, this list of conditions and the following disclaimer in the | ||
13 | # documentation and/or other materials provided with the | ||
14 | # distribution. | ||
15 | # | ||
16 | # Neither the name of Texas Instruments Incorporated nor the names of | ||
17 | # its contributors may be used to endorse or promote products derived | ||
18 | # from this software without specific prior written permission. | ||
19 | # | ||
20 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
21 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
22 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
23 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
24 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
25 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
26 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
27 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
28 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
29 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
30 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
31 | # | ||
32 | |||
33 | SBL_LOADADDDR ?= 0x41c00000 | ||
34 | COMBINED_TIFS_BRDCFG_LOADADDR ?= 0x67000 | ||
35 | COMBINED_DM_BRDCFG_LOADADDR ?= 0x41c80000 | ||
36 | LOADADDR ?= 0x40000 | ||
37 | SCIFS = fs | ||
38 | |||
39 | .PHONY: all | ||
40 | ifeq (,$(SBL)) | ||
41 | all: _objtree_build $(ITB) sysfw.itb | ||
42 | else | ||
43 | all: _objtree_build $(ITB) sysfw.itb tiboot3.bin | ||
44 | endif | ||
diff --git a/soc/j721s2/evm/board-cfg.c b/soc/j721s2/evm/board-cfg.c new file mode 100644 index 000000000..5b59632c0 --- /dev/null +++ b/soc/j721s2/evm/board-cfg.c | |||
@@ -0,0 +1,92 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Board Configuration Data | ||
3 | * | ||
4 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #include "common.h" | ||
36 | |||
37 | const struct boardcfg j721s2_boardcfg_data = { | ||
38 | /* boardcfg_abi_rev */ | ||
39 | .rev = { | ||
40 | .boardcfg_abi_maj = 0x0, | ||
41 | .boardcfg_abi_min = 0x1, | ||
42 | }, | ||
43 | |||
44 | /* boardcfg_control */ | ||
45 | .control = { | ||
46 | .subhdr = { | ||
47 | .magic = BOARDCFG_CONTROL_MAGIC_NUM, | ||
48 | .size = sizeof(struct boardcfg_control), | ||
49 | }, | ||
50 | .main_isolation_enable = 0x5A, | ||
51 | .main_isolation_hostid = 0x2, | ||
52 | }, | ||
53 | |||
54 | /* boardcfg sec_proxy */ | ||
55 | .secproxy = { | ||
56 | .subhdr = { | ||
57 | .magic = BOARDCFG_SECPROXY_MAGIC_NUM, | ||
58 | .size = sizeof(struct boardcfg_secproxy), | ||
59 | }, | ||
60 | .scaling_factor = 0x1, | ||
61 | .scaling_profile = 0x1, | ||
62 | .disable_main_nav_secure_proxy = 0, | ||
63 | }, | ||
64 | |||
65 | /* boardcfg_msmc */ | ||
66 | .msmc = { | ||
67 | .subhdr = { | ||
68 | .magic = BOARDCFG_MSMC_MAGIC_NUM, | ||
69 | .size = sizeof(struct boardcfg_msmc), | ||
70 | }, | ||
71 | .msmc_cache_size = 0x10, | ||
72 | }, | ||
73 | |||
74 | /* boardcfg_dbg_cfg */ | ||
75 | .debug_cfg = { | ||
76 | .subhdr = { | ||
77 | .magic = BOARDCFG_DBG_CFG_MAGIC_NUM, | ||
78 | .size = sizeof(struct boardcfg_dbg_cfg), | ||
79 | }, | ||
80 | #ifdef ENABLE_TRACE | ||
81 | .trace_dst_enables = BOARDCFG_TRACE_DST_UART0 | | ||
82 | BOARDCFG_TRACE_DST_ITM | | ||
83 | BOARDCFG_TRACE_DST_MEM, | ||
84 | .trace_src_enables = BOARDCFG_TRACE_SRC_PM | | ||
85 | BOARDCFG_TRACE_SRC_RM | | ||
86 | BOARDCFG_TRACE_SRC_SEC | | ||
87 | BOARDCFG_TRACE_SRC_BASE | | ||
88 | BOARDCFG_TRACE_SRC_USER | | ||
89 | BOARDCFG_TRACE_SRC_SUPR, | ||
90 | #endif | ||
91 | }, | ||
92 | }; | ||
diff --git a/soc/j721s2/evm/pm-cfg.c b/soc/j721s2/evm/pm-cfg.c new file mode 100644 index 000000000..2bae46ef9 --- /dev/null +++ b/soc/j721s2/evm/pm-cfg.c | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Power Management Configuration Data | ||
3 | * | ||
4 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #include "common.h" | ||
36 | |||
37 | const struct boardcfg_pm j721s2_boardcfg_pm_data = { | ||
38 | /* boardcfg_abi_rev */ | ||
39 | .rev = { | ||
40 | .boardcfg_abi_maj = 0x0, | ||
41 | .boardcfg_abi_min = 0x1, | ||
42 | }, | ||
43 | }; | ||
diff --git a/soc/j721s2/evm/rm-cfg.c b/soc/j721s2/evm/rm-cfg.c new file mode 100644 index 000000000..ca1476b95 --- /dev/null +++ b/soc/j721s2/evm/rm-cfg.c | |||
@@ -0,0 +1,3058 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Resource Management Configuration Data | ||
3 | * Auto generated from K3 Resource Partitioning tool | ||
4 | * | ||
5 | * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
6 | * | ||
7 | * Redistribution and use in source and binary forms, with or without | ||
8 | * modification, are permitted provided that the following conditions | ||
9 | * are met: | ||
10 | * | ||
11 | * Redistributions of source code must retain the above copyright | ||
12 | * notice, this list of conditions and the following disclaimer. | ||
13 | * | ||
14 | * Redistributions in binary form must reproduce the above copyright | ||
15 | * notice, this list of conditions and the following disclaimer in the | ||
16 | * documentation and/or other materials provided with the | ||
17 | * distribution. | ||
18 | * | ||
19 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
20 | * its contributors may be used to endorse or promote products derived | ||
21 | * from this software without specific prior written permission. | ||
22 | * | ||
23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
24 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
25 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
26 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
27 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
28 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
29 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
30 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
31 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
34 | */ | ||
35 | |||
36 | #include "common.h" | ||
37 | #include <hosts.h> | ||
38 | #include <devices.h> | ||
39 | #include <resasg_types.h> | ||
40 | |||
41 | const struct boardcfg_rm_local j721s2_boardcfg_rm_data = { | ||
42 | .rm_boardcfg = { | ||
43 | /* boardcfg_abi_rev */ | ||
44 | .rev = { | ||
45 | .boardcfg_abi_maj = 0x0, | ||
46 | .boardcfg_abi_min = 0x1, | ||
47 | }, | ||
48 | |||
49 | /* boardcfg_rm_host_cfg */ | ||
50 | .host_cfg = { | ||
51 | .subhdr = { | ||
52 | .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM, | ||
53 | .size = sizeof (struct boardcfg_rm_host_cfg), | ||
54 | }, | ||
55 | .host_cfg_entries = { | ||
56 | { | ||
57 | .host_id = HOST_ID_MCU_0_R5_0, | ||
58 | .allowed_atype = 0b101010, | ||
59 | .allowed_qos = 0xAAAA, | ||
60 | .allowed_orderid = 0xAAAAAAAA, | ||
61 | .allowed_priority = 0xAAAA, | ||
62 | .allowed_sched_priority = 0xAA, | ||
63 | }, | ||
64 | { | ||
65 | .host_id = HOST_ID_MCU_0_R5_2, | ||
66 | .allowed_atype = 0b101010, | ||
67 | .allowed_qos = 0xAAAA, | ||
68 | .allowed_orderid = 0xAAAAAAAA, | ||
69 | .allowed_priority = 0xAAAA, | ||
70 | .allowed_sched_priority = 0xAA, | ||
71 | }, | ||
72 | { | ||
73 | .host_id = HOST_ID_A72_2, | ||
74 | .allowed_atype = 0b101010, | ||
75 | .allowed_qos = 0xAAAA, | ||
76 | .allowed_orderid = 0xAAAAAAAA, | ||
77 | .allowed_priority = 0xAAAA, | ||
78 | .allowed_sched_priority = 0xAA, | ||
79 | }, | ||
80 | { | ||
81 | .host_id = HOST_ID_A72_3, | ||
82 | .allowed_atype = 0b101010, | ||
83 | .allowed_qos = 0xAAAA, | ||
84 | .allowed_orderid = 0xAAAAAAAA, | ||
85 | .allowed_priority = 0xAAAA, | ||
86 | .allowed_sched_priority = 0xAA, | ||
87 | }, | ||
88 | { | ||
89 | .host_id = HOST_ID_C7X_0_1, | ||
90 | .allowed_atype = 0b101010, | ||
91 | .allowed_qos = 0xAAAA, | ||
92 | .allowed_orderid = 0xAAAAAAAA, | ||
93 | .allowed_priority = 0xAAAA, | ||
94 | .allowed_sched_priority = 0xAA, | ||
95 | }, | ||
96 | { | ||
97 | .host_id = HOST_ID_C7X_1_1, | ||
98 | .allowed_atype = 0b101010, | ||
99 | .allowed_qos = 0xAAAA, | ||
100 | .allowed_orderid = 0xAAAAAAAA, | ||
101 | .allowed_priority = 0xAAAA, | ||
102 | .allowed_sched_priority = 0xAA, | ||
103 | }, | ||
104 | { | ||
105 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
106 | .allowed_atype = 0b101010, | ||
107 | .allowed_qos = 0xAAAA, | ||
108 | .allowed_orderid = 0xAAAAAAAA, | ||
109 | .allowed_priority = 0xAAAA, | ||
110 | .allowed_sched_priority = 0xAA, | ||
111 | }, | ||
112 | { | ||
113 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
114 | .allowed_atype = 0b101010, | ||
115 | .allowed_qos = 0xAAAA, | ||
116 | .allowed_orderid = 0xAAAAAAAA, | ||
117 | .allowed_priority = 0xAAAA, | ||
118 | .allowed_sched_priority = 0xAA, | ||
119 | }, | ||
120 | { | ||
121 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
122 | .allowed_atype = 0b101010, | ||
123 | .allowed_qos = 0xAAAA, | ||
124 | .allowed_orderid = 0xAAAAAAAA, | ||
125 | .allowed_priority = 0xAAAA, | ||
126 | .allowed_sched_priority = 0xAA, | ||
127 | }, | ||
128 | { | ||
129 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
130 | .allowed_atype = 0b101010, | ||
131 | .allowed_qos = 0xAAAA, | ||
132 | .allowed_orderid = 0xAAAAAAAA, | ||
133 | .allowed_priority = 0xAAAA, | ||
134 | .allowed_sched_priority = 0xAA, | ||
135 | }, | ||
136 | } | ||
137 | }, | ||
138 | |||
139 | /* boardcfg_rm_resasg */ | ||
140 | .resasg = { | ||
141 | .subhdr = { | ||
142 | .magic = BOARDCFG_RM_RESASG_MAGIC_NUM, | ||
143 | .size = sizeof (struct boardcfg_rm_resasg), | ||
144 | }, | ||
145 | .resasg_entries_size = | ||
146 | BOARDCFG_RM_RESASG_ENTRIES * | ||
147 | sizeof (struct boardcfg_rm_resasg_entry), | ||
148 | .reserved = 0, | ||
149 | /* .resasg_entries is set via boardcfg_rm_local */ | ||
150 | }, | ||
151 | }, | ||
152 | |||
153 | /* This is actually part of .resasg */ | ||
154 | .resasg_entries = { | ||
155 | /* Main 2 MCU Level Interrupt router */ | ||
156 | { | ||
157 | .start_resource = 0, | ||
158 | .num_resource = 32, | ||
159 | .type = RESASG_UTYPE (J721S2_DEV_MAIN2MCU_LVL_INTRTR0, | ||
160 | RESASG_SUBTYPE_IR_OUTPUT), | ||
161 | .host_id = HOST_ID_MCU_0_R5_0, | ||
162 | }, | ||
163 | { | ||
164 | .start_resource = 32, | ||
165 | .num_resource = 24, | ||
166 | .type = RESASG_UTYPE (J721S2_DEV_MAIN2MCU_LVL_INTRTR0, | ||
167 | RESASG_SUBTYPE_IR_OUTPUT), | ||
168 | .host_id = HOST_ID_MCU_0_R5_2, | ||
169 | }, | ||
170 | /* Main 2 MCU Pulse Interrupt router */ | ||
171 | { | ||
172 | .start_resource = 0, | ||
173 | .num_resource = 24, | ||
174 | .type = RESASG_UTYPE (J721S2_DEV_MAIN2MCU_PLS_INTRTR0, | ||
175 | RESASG_SUBTYPE_IR_OUTPUT), | ||
176 | .host_id = HOST_ID_MCU_0_R5_0, | ||
177 | }, | ||
178 | { | ||
179 | .start_resource = 24, | ||
180 | .num_resource = 16, | ||
181 | .type = RESASG_UTYPE (J721S2_DEV_MAIN2MCU_PLS_INTRTR0, | ||
182 | RESASG_SUBTYPE_IR_OUTPUT), | ||
183 | .host_id = HOST_ID_MCU_0_R5_2, | ||
184 | }, | ||
185 | /* Timesync Interrupt router */ | ||
186 | { | ||
187 | .start_resource = 0, | ||
188 | .num_resource = 48, | ||
189 | .type = RESASG_UTYPE (J721S2_DEV_TIMESYNC_INTRTR0, | ||
190 | RESASG_SUBTYPE_IR_OUTPUT), | ||
191 | .host_id = HOST_ID_ALL, | ||
192 | }, | ||
193 | /* Wakeup GPIO Interrupt router */ | ||
194 | { | ||
195 | .start_resource = 0, | ||
196 | .num_resource = 8, | ||
197 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
198 | RESASG_SUBTYPE_IR_OUTPUT), | ||
199 | .host_id = HOST_ID_MCU_0_R5_0, | ||
200 | }, | ||
201 | { | ||
202 | .start_resource = 8, | ||
203 | .num_resource = 8, | ||
204 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
205 | RESASG_SUBTYPE_IR_OUTPUT), | ||
206 | .host_id = HOST_ID_MCU_0_R5_2, | ||
207 | }, | ||
208 | { | ||
209 | .start_resource = 16, | ||
210 | .num_resource = 6, | ||
211 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
212 | RESASG_SUBTYPE_IR_OUTPUT), | ||
213 | .host_id = HOST_ID_A72_2, | ||
214 | }, | ||
215 | { | ||
216 | .start_resource = 22, | ||
217 | .num_resource = 6, | ||
218 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
219 | RESASG_SUBTYPE_IR_OUTPUT), | ||
220 | .host_id = HOST_ID_A72_3, | ||
221 | }, | ||
222 | { | ||
223 | .start_resource = 28, | ||
224 | .num_resource = 2, | ||
225 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
226 | RESASG_SUBTYPE_IR_OUTPUT), | ||
227 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
228 | }, | ||
229 | { | ||
230 | .start_resource = 30, | ||
231 | .num_resource = 2, | ||
232 | .type = RESASG_UTYPE (J721S2_DEV_WKUP_GPIOMUX_INTRTR0, | ||
233 | RESASG_SUBTYPE_IR_OUTPUT), | ||
234 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
235 | }, | ||
236 | /* Main GPIO Interrupt router */ | ||
237 | { | ||
238 | .start_resource = 0, | ||
239 | .num_resource = 4, | ||
240 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
241 | RESASG_SUBTYPE_IR_OUTPUT), | ||
242 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
243 | }, | ||
244 | { | ||
245 | .start_resource = 4, | ||
246 | .num_resource = 4, | ||
247 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
248 | RESASG_SUBTYPE_IR_OUTPUT), | ||
249 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
250 | }, | ||
251 | { | ||
252 | .start_resource = 8, | ||
253 | .num_resource = 4, | ||
254 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
255 | RESASG_SUBTYPE_IR_OUTPUT), | ||
256 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
257 | }, | ||
258 | { | ||
259 | .start_resource = 12, | ||
260 | .num_resource = 4, | ||
261 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
262 | RESASG_SUBTYPE_IR_OUTPUT), | ||
263 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
264 | }, | ||
265 | { | ||
266 | .start_resource = 16, | ||
267 | .num_resource = 8, | ||
268 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
269 | RESASG_SUBTYPE_IR_OUTPUT), | ||
270 | .host_id = HOST_ID_MCU_0_R5_0, | ||
271 | }, | ||
272 | { | ||
273 | .start_resource = 24, | ||
274 | .num_resource = 8, | ||
275 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
276 | RESASG_SUBTYPE_IR_OUTPUT), | ||
277 | .host_id = HOST_ID_MCU_0_R5_2, | ||
278 | }, | ||
279 | { | ||
280 | .start_resource = 32, | ||
281 | .num_resource = 12, | ||
282 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
283 | RESASG_SUBTYPE_IR_OUTPUT), | ||
284 | .host_id = HOST_ID_A72_2, | ||
285 | }, | ||
286 | { | ||
287 | .start_resource = 44, | ||
288 | .num_resource = 12, | ||
289 | .type = RESASG_UTYPE (J721S2_DEV_GPIOMUX_INTRTR0, | ||
290 | RESASG_SUBTYPE_IR_OUTPUT), | ||
291 | .host_id = HOST_ID_A72_3, | ||
292 | }, | ||
293 | /* Compare event Interrupt router */ | ||
294 | { | ||
295 | .start_resource = 0, | ||
296 | .num_resource = 16, | ||
297 | .type = RESASG_UTYPE (J721S2_DEV_CMPEVENT_INTRTR0, | ||
298 | RESASG_SUBTYPE_IR_OUTPUT), | ||
299 | .host_id = HOST_ID_ALL, | ||
300 | }, | ||
301 | /* Main NAVSS Block Copy DMA Global event trigger */ | ||
302 | { | ||
303 | .start_resource = 50176, | ||
304 | .num_resource = 96, | ||
305 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
306 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
307 | .host_id = HOST_ID_ALL, | ||
308 | }, | ||
309 | /* Main NAVSS Block Copy DMA Global config */ | ||
310 | { | ||
311 | .start_resource = 0, | ||
312 | .num_resource = 1, | ||
313 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
314 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), | ||
315 | .host_id = HOST_ID_ALL, | ||
316 | }, | ||
317 | /* Main NAVSS Block Copy DMA Rings for Split TR RX channels */ | ||
318 | { | ||
319 | .start_resource = 16, | ||
320 | .num_resource = 16, | ||
321 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
322 | RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN), | ||
323 | .host_id = HOST_ID_A72_2, | ||
324 | }, | ||
325 | { | ||
326 | .start_resource = 32, | ||
327 | .num_resource = 16, | ||
328 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
329 | RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN), | ||
330 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
331 | }, | ||
332 | /* Main NAVSS Block Copy DMA Rings for Split TR TX channels */ | ||
333 | { | ||
334 | .start_resource = 0, | ||
335 | .num_resource = 8, | ||
336 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
337 | RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN), | ||
338 | .host_id = HOST_ID_A72_2, | ||
339 | }, | ||
340 | { | ||
341 | .start_resource = 8, | ||
342 | .num_resource = 8, | ||
343 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
344 | RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN), | ||
345 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
346 | }, | ||
347 | /* Main NAVSS Block Copy DMA Split TR Rx channels */ | ||
348 | { | ||
349 | .start_resource = 0, | ||
350 | .num_resource = 16, | ||
351 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
352 | RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN), | ||
353 | .host_id = HOST_ID_A72_2, | ||
354 | }, | ||
355 | { | ||
356 | .start_resource = 16, | ||
357 | .num_resource = 16, | ||
358 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
359 | RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN), | ||
360 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
361 | }, | ||
362 | /* Main NAVSS Block Copy DMA Split TR Tx channels */ | ||
363 | { | ||
364 | .start_resource = 0, | ||
365 | .num_resource = 8, | ||
366 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
367 | RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN), | ||
368 | .host_id = HOST_ID_A72_2, | ||
369 | }, | ||
370 | { | ||
371 | .start_resource = 8, | ||
372 | .num_resource = 8, | ||
373 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_BCDMA_0, | ||
374 | RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN), | ||
375 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
376 | }, | ||
377 | /* Main NAVSS Interrupt router */ | ||
378 | { | ||
379 | .start_resource = 10, | ||
380 | .num_resource = 100, | ||
381 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
382 | RESASG_SUBTYPE_IR_OUTPUT), | ||
383 | .host_id = HOST_ID_A72_2, | ||
384 | }, | ||
385 | { | ||
386 | .start_resource = 110, | ||
387 | .num_resource = 32, | ||
388 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
389 | RESASG_SUBTYPE_IR_OUTPUT), | ||
390 | .host_id = HOST_ID_A72_3, | ||
391 | }, | ||
392 | { | ||
393 | .start_resource = 142, | ||
394 | .num_resource = 21, | ||
395 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
396 | RESASG_SUBTYPE_IR_OUTPUT), | ||
397 | .host_id = HOST_ID_C7X_0_1, | ||
398 | }, | ||
399 | { | ||
400 | .start_resource = 163, | ||
401 | .num_resource = 21, | ||
402 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
403 | RESASG_SUBTYPE_IR_OUTPUT), | ||
404 | .host_id = HOST_ID_C7X_1_1, | ||
405 | }, | ||
406 | { | ||
407 | .start_resource = 196, | ||
408 | .num_resource = 28, | ||
409 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
410 | RESASG_SUBTYPE_IR_OUTPUT), | ||
411 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
412 | }, | ||
413 | { | ||
414 | .start_resource = 228, | ||
415 | .num_resource = 28, | ||
416 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
417 | RESASG_SUBTYPE_IR_OUTPUT), | ||
418 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
419 | }, | ||
420 | { | ||
421 | .start_resource = 260, | ||
422 | .num_resource = 28, | ||
423 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
424 | RESASG_SUBTYPE_IR_OUTPUT), | ||
425 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
426 | }, | ||
427 | { | ||
428 | .start_resource = 292, | ||
429 | .num_resource = 28, | ||
430 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
431 | RESASG_SUBTYPE_IR_OUTPUT), | ||
432 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
433 | }, | ||
434 | { | ||
435 | .start_resource = 400, | ||
436 | .num_resource = 4, | ||
437 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
438 | RESASG_SUBTYPE_IR_OUTPUT), | ||
439 | .host_id = HOST_ID_MCU_0_R5_0, | ||
440 | }, | ||
441 | { | ||
442 | .start_resource = 404, | ||
443 | .num_resource = 4, | ||
444 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_INTR_0, | ||
445 | RESASG_SUBTYPE_IR_OUTPUT), | ||
446 | .host_id = HOST_ID_MCU_0_R5_2, | ||
447 | }, | ||
448 | /* MODSS Interrupt aggregator0 Virtual interrupts */ | ||
449 | { | ||
450 | .start_resource = 0, | ||
451 | .num_resource = 64, | ||
452 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_MODSS_INTA_0, | ||
453 | RESASG_SUBTYPE_IA_VINT), | ||
454 | .host_id = HOST_ID_ALL, | ||
455 | }, | ||
456 | /* MODSS Interrupt aggregator0 Global events */ | ||
457 | { | ||
458 | .start_resource = 20480, | ||
459 | .num_resource = 1024, | ||
460 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_MODSS_INTA_0, | ||
461 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
462 | .host_id = HOST_ID_ALL, | ||
463 | }, | ||
464 | /* MODSS Interrupt aggregator1 Virtual interrupts */ | ||
465 | { | ||
466 | .start_resource = 0, | ||
467 | .num_resource = 64, | ||
468 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_MODSS_INTA_1, | ||
469 | RESASG_SUBTYPE_IA_VINT), | ||
470 | .host_id = HOST_ID_ALL, | ||
471 | }, | ||
472 | /* MODSS Interrupt aggregator1 Global events */ | ||
473 | { | ||
474 | .start_resource = 22528, | ||
475 | .num_resource = 1024, | ||
476 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_MODSS_INTA_1, | ||
477 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
478 | .host_id = HOST_ID_ALL, | ||
479 | }, | ||
480 | /* Main NAVSS Non secure proxies */ | ||
481 | { | ||
482 | .start_resource = 0, | ||
483 | .num_resource = 4, | ||
484 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
485 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
486 | .host_id = HOST_ID_A72_2, | ||
487 | }, | ||
488 | { | ||
489 | .start_resource = 4, | ||
490 | .num_resource = 4, | ||
491 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
492 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
493 | .host_id = HOST_ID_A72_3, | ||
494 | }, | ||
495 | { | ||
496 | .start_resource = 8, | ||
497 | .num_resource = 4, | ||
498 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
499 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
500 | .host_id = HOST_ID_C7X_0_1, | ||
501 | }, | ||
502 | { | ||
503 | .start_resource = 12, | ||
504 | .num_resource = 4, | ||
505 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
506 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
507 | .host_id = HOST_ID_C7X_1_1, | ||
508 | }, | ||
509 | { | ||
510 | .start_resource = 16, | ||
511 | .num_resource = 12, | ||
512 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
513 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
514 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
515 | }, | ||
516 | { | ||
517 | .start_resource = 28, | ||
518 | .num_resource = 4, | ||
519 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
520 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
521 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
522 | }, | ||
523 | { | ||
524 | .start_resource = 32, | ||
525 | .num_resource = 4, | ||
526 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
527 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
528 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
529 | }, | ||
530 | { | ||
531 | .start_resource = 36, | ||
532 | .num_resource = 4, | ||
533 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
534 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
535 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
536 | }, | ||
537 | { | ||
538 | .start_resource = 40, | ||
539 | .num_resource = 4, | ||
540 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
541 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
542 | .host_id = HOST_ID_MCU_0_R5_0, | ||
543 | }, | ||
544 | { | ||
545 | .start_resource = 44, | ||
546 | .num_resource = 4, | ||
547 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
548 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
549 | .host_id = HOST_ID_MCU_0_R5_2, | ||
550 | }, | ||
551 | { | ||
552 | .start_resource = 48, | ||
553 | .num_resource = 16, | ||
554 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_PROXY_0, | ||
555 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
556 | .host_id = HOST_ID_ALL, | ||
557 | }, | ||
558 | /* Main NAVSS Ring accelerator error event config */ | ||
559 | { | ||
560 | .start_resource = 0, | ||
561 | .num_resource = 1, | ||
562 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
563 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
564 | .host_id = HOST_ID_ALL, | ||
565 | }, | ||
566 | /* Main NAVSS Ring accelerator Free rings */ | ||
567 | { | ||
568 | .start_resource = 423, | ||
569 | .num_resource = 150, | ||
570 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
571 | RESASG_SUBTYPE_RA_GP), | ||
572 | .host_id = HOST_ID_A72_2, | ||
573 | }, | ||
574 | { | ||
575 | .start_resource = 573, | ||
576 | .num_resource = 40, | ||
577 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
578 | RESASG_SUBTYPE_RA_GP), | ||
579 | .host_id = HOST_ID_A72_3, | ||
580 | }, | ||
581 | { | ||
582 | .start_resource = 613, | ||
583 | .num_resource = 32, | ||
584 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
585 | RESASG_SUBTYPE_RA_GP), | ||
586 | .host_id = HOST_ID_C7X_0_1, | ||
587 | }, | ||
588 | { | ||
589 | .start_resource = 645, | ||
590 | .num_resource = 32, | ||
591 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
592 | RESASG_SUBTYPE_RA_GP), | ||
593 | .host_id = HOST_ID_C7X_1_1, | ||
594 | }, | ||
595 | { | ||
596 | .start_resource = 677, | ||
597 | .num_resource = 182, | ||
598 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
599 | RESASG_SUBTYPE_RA_GP), | ||
600 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
601 | }, | ||
602 | { | ||
603 | .start_resource = 859, | ||
604 | .num_resource = 40, | ||
605 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
606 | RESASG_SUBTYPE_RA_GP), | ||
607 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
608 | }, | ||
609 | { | ||
610 | .start_resource = 899, | ||
611 | .num_resource = 10, | ||
612 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
613 | RESASG_SUBTYPE_RA_GP), | ||
614 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
615 | }, | ||
616 | { | ||
617 | .start_resource = 909, | ||
618 | .num_resource = 10, | ||
619 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
620 | RESASG_SUBTYPE_RA_GP), | ||
621 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
622 | }, | ||
623 | { | ||
624 | .start_resource = 919, | ||
625 | .num_resource = 6, | ||
626 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
627 | RESASG_SUBTYPE_RA_GP), | ||
628 | .host_id = HOST_ID_MCU_0_R5_0, | ||
629 | }, | ||
630 | { | ||
631 | .start_resource = 925, | ||
632 | .num_resource = 6, | ||
633 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
634 | RESASG_SUBTYPE_RA_GP), | ||
635 | .host_id = HOST_ID_MCU_0_R5_2, | ||
636 | }, | ||
637 | { | ||
638 | .start_resource = 931, | ||
639 | .num_resource = 43, | ||
640 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
641 | RESASG_SUBTYPE_RA_GP), | ||
642 | .host_id = HOST_ID_ALL, | ||
643 | }, | ||
644 | /* Main NAVSS Rings for Normal capacity Rx channels */ | ||
645 | { | ||
646 | .start_resource = 347, | ||
647 | .num_resource = 6, | ||
648 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
649 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
650 | .host_id = HOST_ID_A72_2, | ||
651 | }, | ||
652 | { | ||
653 | .start_resource = 353, | ||
654 | .num_resource = 0, | ||
655 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
656 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
657 | .host_id = HOST_ID_A72_3, | ||
658 | }, | ||
659 | { | ||
660 | .start_resource = 353, | ||
661 | .num_resource = 2, | ||
662 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
663 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
664 | .host_id = HOST_ID_C7X_0_1, | ||
665 | }, | ||
666 | { | ||
667 | .start_resource = 355, | ||
668 | .num_resource = 2, | ||
669 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
670 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
671 | .host_id = HOST_ID_C7X_1_1, | ||
672 | }, | ||
673 | { | ||
674 | .start_resource = 357, | ||
675 | .num_resource = 6, | ||
676 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
677 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
678 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
679 | }, | ||
680 | { | ||
681 | .start_resource = 363, | ||
682 | .num_resource = 1, | ||
683 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
684 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
685 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
686 | }, | ||
687 | { | ||
688 | .start_resource = 364, | ||
689 | .num_resource = 1, | ||
690 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
691 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
692 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
693 | }, | ||
694 | { | ||
695 | .start_resource = 365, | ||
696 | .num_resource = 1, | ||
697 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
698 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
699 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
700 | }, | ||
701 | { | ||
702 | .start_resource = 366, | ||
703 | .num_resource = 2, | ||
704 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
705 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
706 | .host_id = HOST_ID_MCU_0_R5_0, | ||
707 | }, | ||
708 | { | ||
709 | .start_resource = 368, | ||
710 | .num_resource = 2, | ||
711 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
712 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
713 | .host_id = HOST_ID_MCU_0_R5_2, | ||
714 | }, | ||
715 | { | ||
716 | .start_resource = 370, | ||
717 | .num_resource = 16, | ||
718 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
719 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
720 | .host_id = HOST_ID_A72_2, | ||
721 | }, | ||
722 | { | ||
723 | .start_resource = 386, | ||
724 | .num_resource = 12, | ||
725 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
726 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
727 | .host_id = HOST_ID_A72_3, | ||
728 | }, | ||
729 | { | ||
730 | .start_resource = 398, | ||
731 | .num_resource = 4, | ||
732 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
733 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
734 | .host_id = HOST_ID_C7X_0_1, | ||
735 | }, | ||
736 | { | ||
737 | .start_resource = 402, | ||
738 | .num_resource = 4, | ||
739 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
740 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
741 | .host_id = HOST_ID_C7X_1_1, | ||
742 | }, | ||
743 | { | ||
744 | .start_resource = 406, | ||
745 | .num_resource = 12, | ||
746 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
747 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
748 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
749 | }, | ||
750 | { | ||
751 | .start_resource = 418, | ||
752 | .num_resource = 1, | ||
753 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
754 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
755 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
756 | }, | ||
757 | { | ||
758 | .start_resource = 419, | ||
759 | .num_resource = 2, | ||
760 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
761 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
762 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
763 | }, | ||
764 | { | ||
765 | .start_resource = 421, | ||
766 | .num_resource = 2, | ||
767 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
768 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
769 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
770 | }, | ||
771 | /* Main NAVSS Rings for Normal capacity Tx channels */ | ||
772 | { | ||
773 | .start_resource = 6, | ||
774 | .num_resource = 6, | ||
775 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
776 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
777 | .host_id = HOST_ID_A72_2, | ||
778 | }, | ||
779 | { | ||
780 | .start_resource = 12, | ||
781 | .num_resource = 0, | ||
782 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
783 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
784 | .host_id = HOST_ID_A72_3, | ||
785 | }, | ||
786 | { | ||
787 | .start_resource = 12, | ||
788 | .num_resource = 2, | ||
789 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
790 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
791 | .host_id = HOST_ID_C7X_0_1, | ||
792 | }, | ||
793 | { | ||
794 | .start_resource = 14, | ||
795 | .num_resource = 2, | ||
796 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
797 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
798 | .host_id = HOST_ID_C7X_1_1, | ||
799 | }, | ||
800 | { | ||
801 | .start_resource = 16, | ||
802 | .num_resource = 6, | ||
803 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
804 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
805 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
806 | }, | ||
807 | { | ||
808 | .start_resource = 22, | ||
809 | .num_resource = 1, | ||
810 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
811 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
812 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
813 | }, | ||
814 | { | ||
815 | .start_resource = 23, | ||
816 | .num_resource = 1, | ||
817 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
818 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
819 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
820 | }, | ||
821 | { | ||
822 | .start_resource = 24, | ||
823 | .num_resource = 1, | ||
824 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
825 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
826 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
827 | }, | ||
828 | { | ||
829 | .start_resource = 25, | ||
830 | .num_resource = 2, | ||
831 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
832 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
833 | .host_id = HOST_ID_MCU_0_R5_0, | ||
834 | }, | ||
835 | { | ||
836 | .start_resource = 27, | ||
837 | .num_resource = 2, | ||
838 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
839 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
840 | .host_id = HOST_ID_MCU_0_R5_2, | ||
841 | }, | ||
842 | { | ||
843 | .start_resource = 29, | ||
844 | .num_resource = 16, | ||
845 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
846 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
847 | .host_id = HOST_ID_A72_2, | ||
848 | }, | ||
849 | { | ||
850 | .start_resource = 45, | ||
851 | .num_resource = 12, | ||
852 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
853 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
854 | .host_id = HOST_ID_A72_3, | ||
855 | }, | ||
856 | { | ||
857 | .start_resource = 57, | ||
858 | .num_resource = 4, | ||
859 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
860 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
861 | .host_id = HOST_ID_C7X_0_1, | ||
862 | }, | ||
863 | { | ||
864 | .start_resource = 61, | ||
865 | .num_resource = 4, | ||
866 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
867 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
868 | .host_id = HOST_ID_C7X_1_1, | ||
869 | }, | ||
870 | { | ||
871 | .start_resource = 65, | ||
872 | .num_resource = 12, | ||
873 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
874 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
875 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
876 | }, | ||
877 | { | ||
878 | .start_resource = 77, | ||
879 | .num_resource = 4, | ||
880 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
881 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
882 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
883 | }, | ||
884 | { | ||
885 | .start_resource = 81, | ||
886 | .num_resource = 2, | ||
887 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
888 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
889 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
890 | }, | ||
891 | { | ||
892 | .start_resource = 83, | ||
893 | .num_resource = 2, | ||
894 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
895 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
896 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
897 | }, | ||
898 | /* Main NAVSS Rings for extended Tx channels for DRU */ | ||
899 | { | ||
900 | .start_resource = 85, | ||
901 | .num_resource = 16, | ||
902 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
903 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
904 | .host_id = HOST_ID_C7X_0_1, | ||
905 | }, | ||
906 | { | ||
907 | .start_resource = 101, | ||
908 | .num_resource = 12, | ||
909 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
910 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
911 | .host_id = HOST_ID_C7X_1_1, | ||
912 | }, | ||
913 | { | ||
914 | .start_resource = 113, | ||
915 | .num_resource = 2, | ||
916 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
917 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
918 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
919 | }, | ||
920 | { | ||
921 | .start_resource = 115, | ||
922 | .num_resource = 2, | ||
923 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
924 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
925 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
926 | }, | ||
927 | /* Main NAVSS Rings for extended Tx channels for HWA */ | ||
928 | { | ||
929 | .start_resource = 117, | ||
930 | .num_resource = 192, | ||
931 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
932 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
933 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
934 | }, | ||
935 | { | ||
936 | .start_resource = 309, | ||
937 | .num_resource = 32, | ||
938 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
939 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
940 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
941 | }, | ||
942 | /* Main NAVSS Rings for High capacity Rx channels */ | ||
943 | { | ||
944 | .start_resource = 343, | ||
945 | .num_resource = 0, | ||
946 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
947 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
948 | .host_id = HOST_ID_A72_2, | ||
949 | }, | ||
950 | { | ||
951 | .start_resource = 343, | ||
952 | .num_resource = 2, | ||
953 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
954 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
955 | .host_id = HOST_ID_A72_2, | ||
956 | }, | ||
957 | { | ||
958 | .start_resource = 343, | ||
959 | .num_resource = 0, | ||
960 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
961 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
962 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
963 | }, | ||
964 | { | ||
965 | .start_resource = 345, | ||
966 | .num_resource = 2, | ||
967 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
968 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
969 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
970 | }, | ||
971 | /* Main NAVSS Rings for Ultra High capacity Rx channels */ | ||
972 | { | ||
973 | .start_resource = 341, | ||
974 | .num_resource = 0, | ||
975 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
976 | RESASG_SUBTYPE_RA_UDMAP_RX_UH), | ||
977 | .host_id = HOST_ID_A72_2, | ||
978 | }, | ||
979 | { | ||
980 | .start_resource = 341, | ||
981 | .num_resource = 1, | ||
982 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
983 | RESASG_SUBTYPE_RA_UDMAP_RX_UH), | ||
984 | .host_id = HOST_ID_A72_2, | ||
985 | }, | ||
986 | { | ||
987 | .start_resource = 341, | ||
988 | .num_resource = 0, | ||
989 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
990 | RESASG_SUBTYPE_RA_UDMAP_RX_UH), | ||
991 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
992 | }, | ||
993 | { | ||
994 | .start_resource = 342, | ||
995 | .num_resource = 1, | ||
996 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
997 | RESASG_SUBTYPE_RA_UDMAP_RX_UH), | ||
998 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
999 | }, | ||
1000 | /* Main NAVSS Rings for High capacity Tx channels */ | ||
1001 | { | ||
1002 | .start_resource = 2, | ||
1003 | .num_resource = 0, | ||
1004 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1005 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1006 | .host_id = HOST_ID_A72_2, | ||
1007 | }, | ||
1008 | { | ||
1009 | .start_resource = 2, | ||
1010 | .num_resource = 2, | ||
1011 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1012 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1013 | .host_id = HOST_ID_A72_2, | ||
1014 | }, | ||
1015 | { | ||
1016 | .start_resource = 2, | ||
1017 | .num_resource = 0, | ||
1018 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1019 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1020 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1021 | }, | ||
1022 | { | ||
1023 | .start_resource = 4, | ||
1024 | .num_resource = 2, | ||
1025 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1026 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1027 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1028 | }, | ||
1029 | /* Main NAVSS Rings for Ultra High capacity Tx channels */ | ||
1030 | { | ||
1031 | .start_resource = 0, | ||
1032 | .num_resource = 0, | ||
1033 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1034 | RESASG_SUBTYPE_RA_UDMAP_TX_UH), | ||
1035 | .host_id = HOST_ID_A72_2, | ||
1036 | }, | ||
1037 | { | ||
1038 | .start_resource = 0, | ||
1039 | .num_resource = 1, | ||
1040 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1041 | RESASG_SUBTYPE_RA_UDMAP_TX_UH), | ||
1042 | .host_id = HOST_ID_A72_2, | ||
1043 | }, | ||
1044 | { | ||
1045 | .start_resource = 0, | ||
1046 | .num_resource = 0, | ||
1047 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1048 | RESASG_SUBTYPE_RA_UDMAP_TX_UH), | ||
1049 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1050 | }, | ||
1051 | { | ||
1052 | .start_resource = 1, | ||
1053 | .num_resource = 1, | ||
1054 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1055 | RESASG_SUBTYPE_RA_UDMAP_TX_UH), | ||
1056 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1057 | }, | ||
1058 | /* Main NAVSS Ring accelerator virt_id range */ | ||
1059 | { | ||
1060 | .start_resource = 2, | ||
1061 | .num_resource = 5, | ||
1062 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1063 | RESASG_SUBTYPE_RA_VIRTID), | ||
1064 | .host_id = HOST_ID_A72_2, | ||
1065 | }, | ||
1066 | { | ||
1067 | .start_resource = 7, | ||
1068 | .num_resource = 1, | ||
1069 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1070 | RESASG_SUBTYPE_RA_VIRTID), | ||
1071 | .host_id = HOST_ID_A72_3, | ||
1072 | }, | ||
1073 | /* Main NAVSS Ring accelerator ring monitors */ | ||
1074 | { | ||
1075 | .start_resource = 0, | ||
1076 | .num_resource = 3, | ||
1077 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1078 | RESASG_SUBTYPE_RA_MONITORS), | ||
1079 | .host_id = HOST_ID_A72_2, | ||
1080 | }, | ||
1081 | { | ||
1082 | .start_resource = 3, | ||
1083 | .num_resource = 2, | ||
1084 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1085 | RESASG_SUBTYPE_RA_MONITORS), | ||
1086 | .host_id = HOST_ID_A72_3, | ||
1087 | }, | ||
1088 | { | ||
1089 | .start_resource = 5, | ||
1090 | .num_resource = 3, | ||
1091 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1092 | RESASG_SUBTYPE_RA_MONITORS), | ||
1093 | .host_id = HOST_ID_C7X_0_1, | ||
1094 | }, | ||
1095 | { | ||
1096 | .start_resource = 8, | ||
1097 | .num_resource = 3, | ||
1098 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1099 | RESASG_SUBTYPE_RA_MONITORS), | ||
1100 | .host_id = HOST_ID_C7X_1_1, | ||
1101 | }, | ||
1102 | { | ||
1103 | .start_resource = 11, | ||
1104 | .num_resource = 6, | ||
1105 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1106 | RESASG_SUBTYPE_RA_MONITORS), | ||
1107 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1108 | }, | ||
1109 | { | ||
1110 | .start_resource = 17, | ||
1111 | .num_resource = 3, | ||
1112 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1113 | RESASG_SUBTYPE_RA_MONITORS), | ||
1114 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1115 | }, | ||
1116 | { | ||
1117 | .start_resource = 20, | ||
1118 | .num_resource = 3, | ||
1119 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1120 | RESASG_SUBTYPE_RA_MONITORS), | ||
1121 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1122 | }, | ||
1123 | { | ||
1124 | .start_resource = 23, | ||
1125 | .num_resource = 3, | ||
1126 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1127 | RESASG_SUBTYPE_RA_MONITORS), | ||
1128 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1129 | }, | ||
1130 | { | ||
1131 | .start_resource = 26, | ||
1132 | .num_resource = 1, | ||
1133 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1134 | RESASG_SUBTYPE_RA_MONITORS), | ||
1135 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1136 | }, | ||
1137 | { | ||
1138 | .start_resource = 27, | ||
1139 | .num_resource = 1, | ||
1140 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1141 | RESASG_SUBTYPE_RA_MONITORS), | ||
1142 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1143 | }, | ||
1144 | { | ||
1145 | .start_resource = 28, | ||
1146 | .num_resource = 4, | ||
1147 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_RINGACC_0, | ||
1148 | RESASG_SUBTYPE_RA_MONITORS), | ||
1149 | .host_id = HOST_ID_ALL, | ||
1150 | }, | ||
1151 | /* Main NAVSS UDMA Rx free flows */ | ||
1152 | { | ||
1153 | .start_resource = 82, | ||
1154 | .num_resource = 16, | ||
1155 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1156 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1157 | .host_id = HOST_ID_A72_2, | ||
1158 | }, | ||
1159 | { | ||
1160 | .start_resource = 98, | ||
1161 | .num_resource = 16, | ||
1162 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1163 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1164 | .host_id = HOST_ID_A72_3, | ||
1165 | }, | ||
1166 | { | ||
1167 | .start_resource = 114, | ||
1168 | .num_resource = 110, | ||
1169 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1170 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1171 | .host_id = HOST_ID_ALL, | ||
1172 | }, | ||
1173 | /* Main NAVSS Invalid flow event config */ | ||
1174 | { | ||
1175 | .start_resource = 0, | ||
1176 | .num_resource = 1, | ||
1177 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1178 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | ||
1179 | .host_id = HOST_ID_ALL, | ||
1180 | }, | ||
1181 | /* Main NAVSS UDMA Global event trigger */ | ||
1182 | { | ||
1183 | .start_resource = 49152, | ||
1184 | .num_resource = 1024, | ||
1185 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1186 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
1187 | .host_id = HOST_ID_ALL, | ||
1188 | }, | ||
1189 | /* Main NAVSS UDMA Global config */ | ||
1190 | { | ||
1191 | .start_resource = 0, | ||
1192 | .num_resource = 1, | ||
1193 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1194 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), | ||
1195 | .host_id = HOST_ID_ALL, | ||
1196 | }, | ||
1197 | /* Main NAVSS UDMA Normal capacity Rx channels */ | ||
1198 | { | ||
1199 | .start_resource = 6, | ||
1200 | .num_resource = 6, | ||
1201 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1202 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1203 | .host_id = HOST_ID_A72_2, | ||
1204 | }, | ||
1205 | { | ||
1206 | .start_resource = 12, | ||
1207 | .num_resource = 0, | ||
1208 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1209 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1210 | .host_id = HOST_ID_A72_3, | ||
1211 | }, | ||
1212 | { | ||
1213 | .start_resource = 12, | ||
1214 | .num_resource = 2, | ||
1215 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1216 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1217 | .host_id = HOST_ID_C7X_0_1, | ||
1218 | }, | ||
1219 | { | ||
1220 | .start_resource = 14, | ||
1221 | .num_resource = 2, | ||
1222 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1223 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1224 | .host_id = HOST_ID_C7X_1_1, | ||
1225 | }, | ||
1226 | { | ||
1227 | .start_resource = 16, | ||
1228 | .num_resource = 6, | ||
1229 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1230 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1231 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1232 | }, | ||
1233 | { | ||
1234 | .start_resource = 22, | ||
1235 | .num_resource = 1, | ||
1236 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1237 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1238 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1239 | }, | ||
1240 | { | ||
1241 | .start_resource = 23, | ||
1242 | .num_resource = 1, | ||
1243 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1244 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1245 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1246 | }, | ||
1247 | { | ||
1248 | .start_resource = 24, | ||
1249 | .num_resource = 1, | ||
1250 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1251 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1252 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1253 | }, | ||
1254 | { | ||
1255 | .start_resource = 25, | ||
1256 | .num_resource = 2, | ||
1257 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1258 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1259 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1260 | }, | ||
1261 | { | ||
1262 | .start_resource = 27, | ||
1263 | .num_resource = 2, | ||
1264 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1265 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1266 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1267 | }, | ||
1268 | { | ||
1269 | .start_resource = 29, | ||
1270 | .num_resource = 16, | ||
1271 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1272 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1273 | .host_id = HOST_ID_A72_2, | ||
1274 | }, | ||
1275 | { | ||
1276 | .start_resource = 45, | ||
1277 | .num_resource = 12, | ||
1278 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1279 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1280 | .host_id = HOST_ID_A72_3, | ||
1281 | }, | ||
1282 | { | ||
1283 | .start_resource = 57, | ||
1284 | .num_resource = 4, | ||
1285 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1286 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1287 | .host_id = HOST_ID_C7X_0_1, | ||
1288 | }, | ||
1289 | { | ||
1290 | .start_resource = 61, | ||
1291 | .num_resource = 4, | ||
1292 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1293 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1294 | .host_id = HOST_ID_C7X_1_1, | ||
1295 | }, | ||
1296 | { | ||
1297 | .start_resource = 65, | ||
1298 | .num_resource = 12, | ||
1299 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1300 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1301 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1302 | }, | ||
1303 | { | ||
1304 | .start_resource = 77, | ||
1305 | .num_resource = 1, | ||
1306 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1307 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1308 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1309 | }, | ||
1310 | { | ||
1311 | .start_resource = 78, | ||
1312 | .num_resource = 2, | ||
1313 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1314 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1315 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1316 | }, | ||
1317 | { | ||
1318 | .start_resource = 80, | ||
1319 | .num_resource = 2, | ||
1320 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1321 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1322 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1323 | }, | ||
1324 | /* Main NAVSS UDMA High capacity Rx channels */ | ||
1325 | { | ||
1326 | .start_resource = 2, | ||
1327 | .num_resource = 0, | ||
1328 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1329 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
1330 | .host_id = HOST_ID_A72_2, | ||
1331 | }, | ||
1332 | { | ||
1333 | .start_resource = 2, | ||
1334 | .num_resource = 2, | ||
1335 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1336 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
1337 | .host_id = HOST_ID_A72_2, | ||
1338 | }, | ||
1339 | { | ||
1340 | .start_resource = 2, | ||
1341 | .num_resource = 0, | ||
1342 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1343 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
1344 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1345 | }, | ||
1346 | { | ||
1347 | .start_resource = 4, | ||
1348 | .num_resource = 2, | ||
1349 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1350 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
1351 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1352 | }, | ||
1353 | /* Main NAVSS UDMA Ultra High capacity Rx channels */ | ||
1354 | { | ||
1355 | .start_resource = 0, | ||
1356 | .num_resource = 0, | ||
1357 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1358 | RESASG_SUBTYPE_UDMAP_RX_UHCHAN), | ||
1359 | .host_id = HOST_ID_A72_2, | ||
1360 | }, | ||
1361 | { | ||
1362 | .start_resource = 0, | ||
1363 | .num_resource = 1, | ||
1364 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1365 | RESASG_SUBTYPE_UDMAP_RX_UHCHAN), | ||
1366 | .host_id = HOST_ID_A72_2, | ||
1367 | }, | ||
1368 | { | ||
1369 | .start_resource = 0, | ||
1370 | .num_resource = 0, | ||
1371 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1372 | RESASG_SUBTYPE_UDMAP_RX_UHCHAN), | ||
1373 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1374 | }, | ||
1375 | { | ||
1376 | .start_resource = 1, | ||
1377 | .num_resource = 1, | ||
1378 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1379 | RESASG_SUBTYPE_UDMAP_RX_UHCHAN), | ||
1380 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1381 | }, | ||
1382 | /* Main NAVSS UDMA Normal capacity Tx channels */ | ||
1383 | { | ||
1384 | .start_resource = 6, | ||
1385 | .num_resource = 6, | ||
1386 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1387 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1388 | .host_id = HOST_ID_A72_2, | ||
1389 | }, | ||
1390 | { | ||
1391 | .start_resource = 12, | ||
1392 | .num_resource = 0, | ||
1393 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1394 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1395 | .host_id = HOST_ID_A72_3, | ||
1396 | }, | ||
1397 | { | ||
1398 | .start_resource = 12, | ||
1399 | .num_resource = 2, | ||
1400 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1401 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1402 | .host_id = HOST_ID_C7X_0_1, | ||
1403 | }, | ||
1404 | { | ||
1405 | .start_resource = 14, | ||
1406 | .num_resource = 2, | ||
1407 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1408 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1409 | .host_id = HOST_ID_C7X_1_1, | ||
1410 | }, | ||
1411 | { | ||
1412 | .start_resource = 16, | ||
1413 | .num_resource = 6, | ||
1414 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1415 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1416 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1417 | }, | ||
1418 | { | ||
1419 | .start_resource = 22, | ||
1420 | .num_resource = 1, | ||
1421 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1422 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1423 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1424 | }, | ||
1425 | { | ||
1426 | .start_resource = 23, | ||
1427 | .num_resource = 1, | ||
1428 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1429 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1430 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1431 | }, | ||
1432 | { | ||
1433 | .start_resource = 24, | ||
1434 | .num_resource = 1, | ||
1435 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1436 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1437 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1438 | }, | ||
1439 | { | ||
1440 | .start_resource = 25, | ||
1441 | .num_resource = 2, | ||
1442 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1443 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1444 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1445 | }, | ||
1446 | { | ||
1447 | .start_resource = 27, | ||
1448 | .num_resource = 2, | ||
1449 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1450 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1451 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1452 | }, | ||
1453 | { | ||
1454 | .start_resource = 29, | ||
1455 | .num_resource = 16, | ||
1456 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1457 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1458 | .host_id = HOST_ID_A72_2, | ||
1459 | }, | ||
1460 | { | ||
1461 | .start_resource = 45, | ||
1462 | .num_resource = 12, | ||
1463 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1464 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1465 | .host_id = HOST_ID_A72_3, | ||
1466 | }, | ||
1467 | { | ||
1468 | .start_resource = 57, | ||
1469 | .num_resource = 4, | ||
1470 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1471 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1472 | .host_id = HOST_ID_C7X_0_1, | ||
1473 | }, | ||
1474 | { | ||
1475 | .start_resource = 61, | ||
1476 | .num_resource = 4, | ||
1477 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1478 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1479 | .host_id = HOST_ID_C7X_1_1, | ||
1480 | }, | ||
1481 | { | ||
1482 | .start_resource = 65, | ||
1483 | .num_resource = 12, | ||
1484 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1485 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1486 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1487 | }, | ||
1488 | { | ||
1489 | .start_resource = 77, | ||
1490 | .num_resource = 4, | ||
1491 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1492 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1493 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1494 | }, | ||
1495 | { | ||
1496 | .start_resource = 81, | ||
1497 | .num_resource = 2, | ||
1498 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1499 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1500 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1501 | }, | ||
1502 | { | ||
1503 | .start_resource = 83, | ||
1504 | .num_resource = 2, | ||
1505 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1506 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1507 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1508 | }, | ||
1509 | /* Main NAVSS UDMA Extended Tx channels for DRU */ | ||
1510 | { | ||
1511 | .start_resource = 85, | ||
1512 | .num_resource = 16, | ||
1513 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1514 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1515 | .host_id = HOST_ID_C7X_0_1, | ||
1516 | }, | ||
1517 | { | ||
1518 | .start_resource = 101, | ||
1519 | .num_resource = 12, | ||
1520 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1521 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1522 | .host_id = HOST_ID_C7X_1_1, | ||
1523 | }, | ||
1524 | { | ||
1525 | .start_resource = 113, | ||
1526 | .num_resource = 2, | ||
1527 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1528 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1529 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1530 | }, | ||
1531 | { | ||
1532 | .start_resource = 115, | ||
1533 | .num_resource = 2, | ||
1534 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1535 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1536 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1537 | }, | ||
1538 | /* Main NAVSS UDMA Extended Tx channels for HWA */ | ||
1539 | { | ||
1540 | .start_resource = 117, | ||
1541 | .num_resource = 192, | ||
1542 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1543 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1544 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1545 | }, | ||
1546 | { | ||
1547 | .start_resource = 309, | ||
1548 | .num_resource = 32, | ||
1549 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1550 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
1551 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1552 | }, | ||
1553 | /* Main NAVSS UDMA High capacity Tx channels */ | ||
1554 | { | ||
1555 | .start_resource = 2, | ||
1556 | .num_resource = 0, | ||
1557 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1558 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1559 | .host_id = HOST_ID_A72_2, | ||
1560 | }, | ||
1561 | { | ||
1562 | .start_resource = 2, | ||
1563 | .num_resource = 2, | ||
1564 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1565 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1566 | .host_id = HOST_ID_A72_2, | ||
1567 | }, | ||
1568 | { | ||
1569 | .start_resource = 2, | ||
1570 | .num_resource = 0, | ||
1571 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1572 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1573 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1574 | }, | ||
1575 | { | ||
1576 | .start_resource = 4, | ||
1577 | .num_resource = 2, | ||
1578 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1579 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1580 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1581 | }, | ||
1582 | /* Main NAVSS UDMA Ultra High capacity Tx channels */ | ||
1583 | { | ||
1584 | .start_resource = 0, | ||
1585 | .num_resource = 0, | ||
1586 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1587 | RESASG_SUBTYPE_UDMAP_TX_UHCHAN), | ||
1588 | .host_id = HOST_ID_A72_2, | ||
1589 | }, | ||
1590 | { | ||
1591 | .start_resource = 0, | ||
1592 | .num_resource = 1, | ||
1593 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1594 | RESASG_SUBTYPE_UDMAP_TX_UHCHAN), | ||
1595 | .host_id = HOST_ID_A72_2, | ||
1596 | }, | ||
1597 | { | ||
1598 | .start_resource = 0, | ||
1599 | .num_resource = 0, | ||
1600 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1601 | RESASG_SUBTYPE_UDMAP_TX_UHCHAN), | ||
1602 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1603 | }, | ||
1604 | { | ||
1605 | .start_resource = 1, | ||
1606 | .num_resource = 1, | ||
1607 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMAP_0, | ||
1608 | RESASG_SUBTYPE_UDMAP_TX_UHCHAN), | ||
1609 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1610 | }, | ||
1611 | /* Main NAVSS Interrupt aggregator Virtual interrupts */ | ||
1612 | { | ||
1613 | .start_resource = 34, | ||
1614 | .num_resource = 86, | ||
1615 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1616 | RESASG_SUBTYPE_IA_VINT), | ||
1617 | .host_id = HOST_ID_A72_2, | ||
1618 | }, | ||
1619 | { | ||
1620 | .start_resource = 120, | ||
1621 | .num_resource = 32, | ||
1622 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1623 | RESASG_SUBTYPE_IA_VINT), | ||
1624 | .host_id = HOST_ID_A72_3, | ||
1625 | }, | ||
1626 | { | ||
1627 | .start_resource = 152, | ||
1628 | .num_resource = 12, | ||
1629 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1630 | RESASG_SUBTYPE_IA_VINT), | ||
1631 | .host_id = HOST_ID_C7X_0_1, | ||
1632 | }, | ||
1633 | { | ||
1634 | .start_resource = 164, | ||
1635 | .num_resource = 12, | ||
1636 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1637 | RESASG_SUBTYPE_IA_VINT), | ||
1638 | .host_id = HOST_ID_C7X_1_1, | ||
1639 | }, | ||
1640 | { | ||
1641 | .start_resource = 176, | ||
1642 | .num_resource = 28, | ||
1643 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1644 | RESASG_SUBTYPE_IA_VINT), | ||
1645 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1646 | }, | ||
1647 | { | ||
1648 | .start_resource = 204, | ||
1649 | .num_resource = 8, | ||
1650 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1651 | RESASG_SUBTYPE_IA_VINT), | ||
1652 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1653 | }, | ||
1654 | { | ||
1655 | .start_resource = 212, | ||
1656 | .num_resource = 12, | ||
1657 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1658 | RESASG_SUBTYPE_IA_VINT), | ||
1659 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1660 | }, | ||
1661 | { | ||
1662 | .start_resource = 224, | ||
1663 | .num_resource = 12, | ||
1664 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1665 | RESASG_SUBTYPE_IA_VINT), | ||
1666 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1667 | }, | ||
1668 | { | ||
1669 | .start_resource = 236, | ||
1670 | .num_resource = 20, | ||
1671 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1672 | RESASG_SUBTYPE_IA_VINT), | ||
1673 | .host_id = HOST_ID_ALL, | ||
1674 | }, | ||
1675 | /* Main NAVSS UDMA Interrupt aggregator Global events */ | ||
1676 | { | ||
1677 | .start_resource = 34, | ||
1678 | .num_resource = 1024, | ||
1679 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1680 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1681 | .host_id = HOST_ID_A72_2, | ||
1682 | }, | ||
1683 | { | ||
1684 | .start_resource = 1058, | ||
1685 | .num_resource = 512, | ||
1686 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1687 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1688 | .host_id = HOST_ID_A72_3, | ||
1689 | }, | ||
1690 | { | ||
1691 | .start_resource = 1570, | ||
1692 | .num_resource = 256, | ||
1693 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1694 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1695 | .host_id = HOST_ID_C7X_0_1, | ||
1696 | }, | ||
1697 | { | ||
1698 | .start_resource = 1826, | ||
1699 | .num_resource = 256, | ||
1700 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1701 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1702 | .host_id = HOST_ID_C7X_1_1, | ||
1703 | }, | ||
1704 | { | ||
1705 | .start_resource = 2082, | ||
1706 | .num_resource = 512, | ||
1707 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1708 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1709 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1710 | }, | ||
1711 | { | ||
1712 | .start_resource = 2594, | ||
1713 | .num_resource = 256, | ||
1714 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1715 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1716 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1717 | }, | ||
1718 | { | ||
1719 | .start_resource = 2850, | ||
1720 | .num_resource = 256, | ||
1721 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1722 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1723 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1724 | }, | ||
1725 | { | ||
1726 | .start_resource = 3106, | ||
1727 | .num_resource = 256, | ||
1728 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1729 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1730 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1731 | }, | ||
1732 | { | ||
1733 | .start_resource = 3362, | ||
1734 | .num_resource = 32, | ||
1735 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1736 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1737 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1738 | }, | ||
1739 | { | ||
1740 | .start_resource = 3394, | ||
1741 | .num_resource = 32, | ||
1742 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1743 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1744 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1745 | }, | ||
1746 | { | ||
1747 | .start_resource = 3426, | ||
1748 | .num_resource = 1182, | ||
1749 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1750 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1751 | .host_id = HOST_ID_ALL, | ||
1752 | }, | ||
1753 | /* Main NAVSS Block Copy DMA Tx channel error event */ | ||
1754 | { | ||
1755 | .start_resource = 1536, | ||
1756 | .num_resource = 16, | ||
1757 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1758 | RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES), | ||
1759 | .host_id = HOST_ID_ALL, | ||
1760 | }, | ||
1761 | /* Main NAVSS Block Copy DMA Tx channel data completion event */ | ||
1762 | { | ||
1763 | .start_resource = 2048, | ||
1764 | .num_resource = 16, | ||
1765 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1766 | RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES), | ||
1767 | .host_id = HOST_ID_ALL, | ||
1768 | }, | ||
1769 | /* Main NAVSS Block Copy DMA Tx channel ring completion event */ | ||
1770 | { | ||
1771 | .start_resource = 2560, | ||
1772 | .num_resource = 16, | ||
1773 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1774 | RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES), | ||
1775 | .host_id = HOST_ID_ALL, | ||
1776 | }, | ||
1777 | /* Main NAVSS Block Copy DMA Rx channel error event */ | ||
1778 | { | ||
1779 | .start_resource = 3072, | ||
1780 | .num_resource = 32, | ||
1781 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1782 | RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES), | ||
1783 | .host_id = HOST_ID_ALL, | ||
1784 | }, | ||
1785 | /* Main NAVSS Block Copy DMA Rx channel data completion event */ | ||
1786 | { | ||
1787 | .start_resource = 3584, | ||
1788 | .num_resource = 32, | ||
1789 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1790 | RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES), | ||
1791 | .host_id = HOST_ID_ALL, | ||
1792 | }, | ||
1793 | /* Main NAVSS Block Copy DMA Rx channel ring completion event */ | ||
1794 | { | ||
1795 | .start_resource = 4096, | ||
1796 | .num_resource = 32, | ||
1797 | .type = RESASG_UTYPE (J721S2_DEV_NAVSS0_UDMASS_INTA_0, | ||
1798 | RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES), | ||
1799 | .host_id = HOST_ID_ALL, | ||
1800 | }, | ||
1801 | /* MCU NAVSS Interrupt router */ | ||
1802 | { | ||
1803 | .start_resource = 12, | ||
1804 | .num_resource = 12, | ||
1805 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0, | ||
1806 | RESASG_SUBTYPE_IR_OUTPUT), | ||
1807 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1808 | }, | ||
1809 | { | ||
1810 | .start_resource = 36, | ||
1811 | .num_resource = 20, | ||
1812 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_INTR_ROUTER_0, | ||
1813 | RESASG_SUBTYPE_IR_OUTPUT), | ||
1814 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1815 | }, | ||
1816 | /* MCU NAVSS Non secure proxies */ | ||
1817 | { | ||
1818 | .start_resource = 1, | ||
1819 | .num_resource = 4, | ||
1820 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1821 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1822 | .host_id = HOST_ID_A72_2, | ||
1823 | }, | ||
1824 | { | ||
1825 | .start_resource = 5, | ||
1826 | .num_resource = 4, | ||
1827 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1828 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1829 | .host_id = HOST_ID_A72_3, | ||
1830 | }, | ||
1831 | { | ||
1832 | .start_resource = 9, | ||
1833 | .num_resource = 4, | ||
1834 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1835 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1836 | .host_id = HOST_ID_C7X_0_1, | ||
1837 | }, | ||
1838 | { | ||
1839 | .start_resource = 13, | ||
1840 | .num_resource = 4, | ||
1841 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1842 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1843 | .host_id = HOST_ID_C7X_1_1, | ||
1844 | }, | ||
1845 | { | ||
1846 | .start_resource = 17, | ||
1847 | .num_resource = 16, | ||
1848 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1849 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1850 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1851 | }, | ||
1852 | { | ||
1853 | .start_resource = 33, | ||
1854 | .num_resource = 4, | ||
1855 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1856 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1857 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1858 | }, | ||
1859 | { | ||
1860 | .start_resource = 37, | ||
1861 | .num_resource = 4, | ||
1862 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1863 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1864 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1865 | }, | ||
1866 | { | ||
1867 | .start_resource = 41, | ||
1868 | .num_resource = 4, | ||
1869 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1870 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1871 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1872 | }, | ||
1873 | { | ||
1874 | .start_resource = 45, | ||
1875 | .num_resource = 4, | ||
1876 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1877 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1878 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1879 | }, | ||
1880 | { | ||
1881 | .start_resource = 49, | ||
1882 | .num_resource = 4, | ||
1883 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1884 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1885 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1886 | }, | ||
1887 | { | ||
1888 | .start_resource = 53, | ||
1889 | .num_resource = 11, | ||
1890 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_PROXY0, | ||
1891 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1892 | .host_id = HOST_ID_ALL, | ||
1893 | }, | ||
1894 | /* MCU NAVSS Ring accelerator error event config */ | ||
1895 | { | ||
1896 | .start_resource = 0, | ||
1897 | .num_resource = 1, | ||
1898 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1899 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
1900 | .host_id = HOST_ID_ALL, | ||
1901 | }, | ||
1902 | /* MCU NAVSS Ring accelerator Free rings */ | ||
1903 | { | ||
1904 | .start_resource = 96, | ||
1905 | .num_resource = 20, | ||
1906 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1907 | RESASG_SUBTYPE_RA_GP), | ||
1908 | .host_id = HOST_ID_A72_2, | ||
1909 | }, | ||
1910 | { | ||
1911 | .start_resource = 116, | ||
1912 | .num_resource = 8, | ||
1913 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1914 | RESASG_SUBTYPE_RA_GP), | ||
1915 | .host_id = HOST_ID_A72_3, | ||
1916 | }, | ||
1917 | { | ||
1918 | .start_resource = 124, | ||
1919 | .num_resource = 8, | ||
1920 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1921 | RESASG_SUBTYPE_RA_GP), | ||
1922 | .host_id = HOST_ID_C7X_0_1, | ||
1923 | }, | ||
1924 | { | ||
1925 | .start_resource = 132, | ||
1926 | .num_resource = 8, | ||
1927 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1928 | RESASG_SUBTYPE_RA_GP), | ||
1929 | .host_id = HOST_ID_C7X_1_1, | ||
1930 | }, | ||
1931 | { | ||
1932 | .start_resource = 140, | ||
1933 | .num_resource = 16, | ||
1934 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1935 | RESASG_SUBTYPE_RA_GP), | ||
1936 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
1937 | }, | ||
1938 | { | ||
1939 | .start_resource = 156, | ||
1940 | .num_resource = 8, | ||
1941 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1942 | RESASG_SUBTYPE_RA_GP), | ||
1943 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
1944 | }, | ||
1945 | { | ||
1946 | .start_resource = 164, | ||
1947 | .num_resource = 8, | ||
1948 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1949 | RESASG_SUBTYPE_RA_GP), | ||
1950 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
1951 | }, | ||
1952 | { | ||
1953 | .start_resource = 172, | ||
1954 | .num_resource = 8, | ||
1955 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1956 | RESASG_SUBTYPE_RA_GP), | ||
1957 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
1958 | }, | ||
1959 | { | ||
1960 | .start_resource = 180, | ||
1961 | .num_resource = 32, | ||
1962 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1963 | RESASG_SUBTYPE_RA_GP), | ||
1964 | .host_id = HOST_ID_MCU_0_R5_0, | ||
1965 | }, | ||
1966 | { | ||
1967 | .start_resource = 212, | ||
1968 | .num_resource = 12, | ||
1969 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1970 | RESASG_SUBTYPE_RA_GP), | ||
1971 | .host_id = HOST_ID_MCU_0_R5_2, | ||
1972 | }, | ||
1973 | { | ||
1974 | .start_resource = 224, | ||
1975 | .num_resource = 28, | ||
1976 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1977 | RESASG_SUBTYPE_RA_GP), | ||
1978 | .host_id = HOST_ID_ALL, | ||
1979 | }, | ||
1980 | /* MCU NAVSS Rings for Normal capacity Rx channels */ | ||
1981 | { | ||
1982 | .start_resource = 50, | ||
1983 | .num_resource = 4, | ||
1984 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1985 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1986 | .host_id = HOST_ID_A72_2, | ||
1987 | }, | ||
1988 | { | ||
1989 | .start_resource = 54, | ||
1990 | .num_resource = 0, | ||
1991 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1992 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1993 | .host_id = HOST_ID_A72_3, | ||
1994 | }, | ||
1995 | { | ||
1996 | .start_resource = 54, | ||
1997 | .num_resource = 1, | ||
1998 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
1999 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2000 | .host_id = HOST_ID_C7X_0_1, | ||
2001 | }, | ||
2002 | { | ||
2003 | .start_resource = 55, | ||
2004 | .num_resource = 1, | ||
2005 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2006 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2007 | .host_id = HOST_ID_C7X_1_1, | ||
2008 | }, | ||
2009 | { | ||
2010 | .start_resource = 56, | ||
2011 | .num_resource = 1, | ||
2012 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2013 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2014 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2015 | }, | ||
2016 | { | ||
2017 | .start_resource = 57, | ||
2018 | .num_resource = 1, | ||
2019 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2020 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2021 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2022 | }, | ||
2023 | { | ||
2024 | .start_resource = 58, | ||
2025 | .num_resource = 1, | ||
2026 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2027 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2028 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2029 | }, | ||
2030 | { | ||
2031 | .start_resource = 59, | ||
2032 | .num_resource = 1, | ||
2033 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2034 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2035 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2036 | }, | ||
2037 | { | ||
2038 | .start_resource = 60, | ||
2039 | .num_resource = 2, | ||
2040 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2041 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2042 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2043 | }, | ||
2044 | { | ||
2045 | .start_resource = 62, | ||
2046 | .num_resource = 0, | ||
2047 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2048 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2049 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2050 | }, | ||
2051 | { | ||
2052 | .start_resource = 62, | ||
2053 | .num_resource = 9, | ||
2054 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2055 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2056 | .host_id = HOST_ID_A72_2, | ||
2057 | }, | ||
2058 | { | ||
2059 | .start_resource = 71, | ||
2060 | .num_resource = 6, | ||
2061 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2062 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2063 | .host_id = HOST_ID_A72_3, | ||
2064 | }, | ||
2065 | { | ||
2066 | .start_resource = 77, | ||
2067 | .num_resource = 1, | ||
2068 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2069 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2070 | .host_id = HOST_ID_C7X_0_1, | ||
2071 | }, | ||
2072 | { | ||
2073 | .start_resource = 78, | ||
2074 | .num_resource = 1, | ||
2075 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2076 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2077 | .host_id = HOST_ID_C7X_1_1, | ||
2078 | }, | ||
2079 | { | ||
2080 | .start_resource = 79, | ||
2081 | .num_resource = 2, | ||
2082 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2083 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2084 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2085 | }, | ||
2086 | { | ||
2087 | .start_resource = 81, | ||
2088 | .num_resource = 1, | ||
2089 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2090 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2091 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2092 | }, | ||
2093 | { | ||
2094 | .start_resource = 82, | ||
2095 | .num_resource = 1, | ||
2096 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2097 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2098 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2099 | }, | ||
2100 | { | ||
2101 | .start_resource = 83, | ||
2102 | .num_resource = 1, | ||
2103 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2104 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2105 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2106 | }, | ||
2107 | { | ||
2108 | .start_resource = 84, | ||
2109 | .num_resource = 3, | ||
2110 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2111 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2112 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2113 | }, | ||
2114 | { | ||
2115 | .start_resource = 87, | ||
2116 | .num_resource = 2, | ||
2117 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2118 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2119 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2120 | }, | ||
2121 | { | ||
2122 | .start_resource = 89, | ||
2123 | .num_resource = 4, | ||
2124 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2125 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
2126 | .host_id = HOST_ID_ALL, | ||
2127 | }, | ||
2128 | /* MCU NAVSS Rings for Normal capacity Tx channels */ | ||
2129 | { | ||
2130 | .start_resource = 2, | ||
2131 | .num_resource = 4, | ||
2132 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2133 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2134 | .host_id = HOST_ID_A72_2, | ||
2135 | }, | ||
2136 | { | ||
2137 | .start_resource = 6, | ||
2138 | .num_resource = 0, | ||
2139 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2140 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2141 | .host_id = HOST_ID_A72_3, | ||
2142 | }, | ||
2143 | { | ||
2144 | .start_resource = 6, | ||
2145 | .num_resource = 1, | ||
2146 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2147 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2148 | .host_id = HOST_ID_C7X_0_1, | ||
2149 | }, | ||
2150 | { | ||
2151 | .start_resource = 7, | ||
2152 | .num_resource = 1, | ||
2153 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2154 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2155 | .host_id = HOST_ID_C7X_1_1, | ||
2156 | }, | ||
2157 | { | ||
2158 | .start_resource = 8, | ||
2159 | .num_resource = 1, | ||
2160 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2161 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2162 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2163 | }, | ||
2164 | { | ||
2165 | .start_resource = 9, | ||
2166 | .num_resource = 1, | ||
2167 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2168 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2169 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2170 | }, | ||
2171 | { | ||
2172 | .start_resource = 10, | ||
2173 | .num_resource = 1, | ||
2174 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2175 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2176 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2177 | }, | ||
2178 | { | ||
2179 | .start_resource = 11, | ||
2180 | .num_resource = 1, | ||
2181 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2182 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2183 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2184 | }, | ||
2185 | { | ||
2186 | .start_resource = 12, | ||
2187 | .num_resource = 2, | ||
2188 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2189 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2190 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2191 | }, | ||
2192 | { | ||
2193 | .start_resource = 14, | ||
2194 | .num_resource = 0, | ||
2195 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2196 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2197 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2198 | }, | ||
2199 | { | ||
2200 | .start_resource = 14, | ||
2201 | .num_resource = 9, | ||
2202 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2203 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2204 | .host_id = HOST_ID_A72_2, | ||
2205 | }, | ||
2206 | { | ||
2207 | .start_resource = 23, | ||
2208 | .num_resource = 6, | ||
2209 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2210 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2211 | .host_id = HOST_ID_A72_3, | ||
2212 | }, | ||
2213 | { | ||
2214 | .start_resource = 29, | ||
2215 | .num_resource = 1, | ||
2216 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2217 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2218 | .host_id = HOST_ID_C7X_0_1, | ||
2219 | }, | ||
2220 | { | ||
2221 | .start_resource = 30, | ||
2222 | .num_resource = 1, | ||
2223 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2224 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2225 | .host_id = HOST_ID_C7X_1_1, | ||
2226 | }, | ||
2227 | { | ||
2228 | .start_resource = 31, | ||
2229 | .num_resource = 2, | ||
2230 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2231 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2232 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2233 | }, | ||
2234 | { | ||
2235 | .start_resource = 33, | ||
2236 | .num_resource = 1, | ||
2237 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2238 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2239 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2240 | }, | ||
2241 | { | ||
2242 | .start_resource = 34, | ||
2243 | .num_resource = 1, | ||
2244 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2245 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2246 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2247 | }, | ||
2248 | { | ||
2249 | .start_resource = 35, | ||
2250 | .num_resource = 1, | ||
2251 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2252 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2253 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2254 | }, | ||
2255 | { | ||
2256 | .start_resource = 36, | ||
2257 | .num_resource = 3, | ||
2258 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2259 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2260 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2261 | }, | ||
2262 | { | ||
2263 | .start_resource = 39, | ||
2264 | .num_resource = 2, | ||
2265 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2266 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2267 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2268 | }, | ||
2269 | { | ||
2270 | .start_resource = 41, | ||
2271 | .num_resource = 5, | ||
2272 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2273 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
2274 | .host_id = HOST_ID_ALL, | ||
2275 | }, | ||
2276 | /* MCU NAVSS Rings for High capacity Rx channels */ | ||
2277 | { | ||
2278 | .start_resource = 48, | ||
2279 | .num_resource = 0, | ||
2280 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2281 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
2282 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2283 | }, | ||
2284 | { | ||
2285 | .start_resource = 48, | ||
2286 | .num_resource = 2, | ||
2287 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2288 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
2289 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2290 | }, | ||
2291 | /* MCU NAVSS Rings for High capacity Tx channels */ | ||
2292 | { | ||
2293 | .start_resource = 0, | ||
2294 | .num_resource = 0, | ||
2295 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2296 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
2297 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2298 | }, | ||
2299 | { | ||
2300 | .start_resource = 0, | ||
2301 | .num_resource = 2, | ||
2302 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2303 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
2304 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2305 | }, | ||
2306 | /* MCU NAVSS Ring accelerator virt_id range */ | ||
2307 | { | ||
2308 | .start_resource = 2, | ||
2309 | .num_resource = 5, | ||
2310 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2311 | RESASG_SUBTYPE_RA_VIRTID), | ||
2312 | .host_id = HOST_ID_A72_2, | ||
2313 | }, | ||
2314 | { | ||
2315 | .start_resource = 7, | ||
2316 | .num_resource = 1, | ||
2317 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2318 | RESASG_SUBTYPE_RA_VIRTID), | ||
2319 | .host_id = HOST_ID_A72_3, | ||
2320 | }, | ||
2321 | /* MCU NAVSS Ring accelerator ring monitors */ | ||
2322 | { | ||
2323 | .start_resource = 0, | ||
2324 | .num_resource = 3, | ||
2325 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2326 | RESASG_SUBTYPE_RA_MONITORS), | ||
2327 | .host_id = HOST_ID_A72_2, | ||
2328 | }, | ||
2329 | { | ||
2330 | .start_resource = 3, | ||
2331 | .num_resource = 2, | ||
2332 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2333 | RESASG_SUBTYPE_RA_MONITORS), | ||
2334 | .host_id = HOST_ID_A72_3, | ||
2335 | }, | ||
2336 | { | ||
2337 | .start_resource = 5, | ||
2338 | .num_resource = 3, | ||
2339 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2340 | RESASG_SUBTYPE_RA_MONITORS), | ||
2341 | .host_id = HOST_ID_C7X_0_1, | ||
2342 | }, | ||
2343 | { | ||
2344 | .start_resource = 8, | ||
2345 | .num_resource = 3, | ||
2346 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2347 | RESASG_SUBTYPE_RA_MONITORS), | ||
2348 | .host_id = HOST_ID_C7X_1_1, | ||
2349 | }, | ||
2350 | { | ||
2351 | .start_resource = 11, | ||
2352 | .num_resource = 3, | ||
2353 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2354 | RESASG_SUBTYPE_RA_MONITORS), | ||
2355 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2356 | }, | ||
2357 | { | ||
2358 | .start_resource = 14, | ||
2359 | .num_resource = 3, | ||
2360 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2361 | RESASG_SUBTYPE_RA_MONITORS), | ||
2362 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2363 | }, | ||
2364 | { | ||
2365 | .start_resource = 17, | ||
2366 | .num_resource = 3, | ||
2367 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2368 | RESASG_SUBTYPE_RA_MONITORS), | ||
2369 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2370 | }, | ||
2371 | { | ||
2372 | .start_resource = 20, | ||
2373 | .num_resource = 3, | ||
2374 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2375 | RESASG_SUBTYPE_RA_MONITORS), | ||
2376 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2377 | }, | ||
2378 | { | ||
2379 | .start_resource = 23, | ||
2380 | .num_resource = 3, | ||
2381 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2382 | RESASG_SUBTYPE_RA_MONITORS), | ||
2383 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2384 | }, | ||
2385 | { | ||
2386 | .start_resource = 26, | ||
2387 | .num_resource = 3, | ||
2388 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2389 | RESASG_SUBTYPE_RA_MONITORS), | ||
2390 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2391 | }, | ||
2392 | { | ||
2393 | .start_resource = 29, | ||
2394 | .num_resource = 3, | ||
2395 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_RINGACC0, | ||
2396 | RESASG_SUBTYPE_RA_MONITORS), | ||
2397 | .host_id = HOST_ID_ALL, | ||
2398 | }, | ||
2399 | /* MCU NAVSS UDMA Rx free flows */ | ||
2400 | { | ||
2401 | .start_resource = 48, | ||
2402 | .num_resource = 8, | ||
2403 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2404 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2405 | .host_id = HOST_ID_A72_2, | ||
2406 | }, | ||
2407 | { | ||
2408 | .start_resource = 56, | ||
2409 | .num_resource = 4, | ||
2410 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2411 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2412 | .host_id = HOST_ID_A72_3, | ||
2413 | }, | ||
2414 | { | ||
2415 | .start_resource = 60, | ||
2416 | .num_resource = 8, | ||
2417 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2418 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2419 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2420 | }, | ||
2421 | { | ||
2422 | .start_resource = 68, | ||
2423 | .num_resource = 4, | ||
2424 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2425 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2426 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2427 | }, | ||
2428 | { | ||
2429 | .start_resource = 72, | ||
2430 | .num_resource = 4, | ||
2431 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2432 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2433 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2434 | }, | ||
2435 | { | ||
2436 | .start_resource = 76, | ||
2437 | .num_resource = 4, | ||
2438 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2439 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2440 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2441 | }, | ||
2442 | { | ||
2443 | .start_resource = 80, | ||
2444 | .num_resource = 8, | ||
2445 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2446 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2447 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2448 | }, | ||
2449 | { | ||
2450 | .start_resource = 88, | ||
2451 | .num_resource = 4, | ||
2452 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2453 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2454 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2455 | }, | ||
2456 | { | ||
2457 | .start_resource = 92, | ||
2458 | .num_resource = 4, | ||
2459 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2460 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
2461 | .host_id = HOST_ID_ALL, | ||
2462 | }, | ||
2463 | /* MCU NAVSS Invalid flow event config */ | ||
2464 | { | ||
2465 | .start_resource = 0, | ||
2466 | .num_resource = 1, | ||
2467 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2468 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | ||
2469 | .host_id = HOST_ID_ALL, | ||
2470 | }, | ||
2471 | /* MCU NAVSS UDMA Global event trigger */ | ||
2472 | { | ||
2473 | .start_resource = 56320, | ||
2474 | .num_resource = 256, | ||
2475 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2476 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
2477 | .host_id = HOST_ID_ALL, | ||
2478 | }, | ||
2479 | /* MCU NAVSS UDMA Global config */ | ||
2480 | { | ||
2481 | .start_resource = 0, | ||
2482 | .num_resource = 1, | ||
2483 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2484 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), | ||
2485 | .host_id = HOST_ID_ALL, | ||
2486 | }, | ||
2487 | /* MCU NAVSS UDMA Normal capacity Rx channels */ | ||
2488 | { | ||
2489 | .start_resource = 2, | ||
2490 | .num_resource = 4, | ||
2491 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2492 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2493 | .host_id = HOST_ID_A72_2, | ||
2494 | }, | ||
2495 | { | ||
2496 | .start_resource = 6, | ||
2497 | .num_resource = 0, | ||
2498 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2499 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2500 | .host_id = HOST_ID_A72_3, | ||
2501 | }, | ||
2502 | { | ||
2503 | .start_resource = 6, | ||
2504 | .num_resource = 1, | ||
2505 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2506 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2507 | .host_id = HOST_ID_C7X_0_1, | ||
2508 | }, | ||
2509 | { | ||
2510 | .start_resource = 7, | ||
2511 | .num_resource = 1, | ||
2512 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2513 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2514 | .host_id = HOST_ID_C7X_1_1, | ||
2515 | }, | ||
2516 | { | ||
2517 | .start_resource = 8, | ||
2518 | .num_resource = 1, | ||
2519 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2520 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2521 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2522 | }, | ||
2523 | { | ||
2524 | .start_resource = 9, | ||
2525 | .num_resource = 1, | ||
2526 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2527 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2528 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2529 | }, | ||
2530 | { | ||
2531 | .start_resource = 10, | ||
2532 | .num_resource = 1, | ||
2533 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2534 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2535 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2536 | }, | ||
2537 | { | ||
2538 | .start_resource = 11, | ||
2539 | .num_resource = 1, | ||
2540 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2541 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2542 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2543 | }, | ||
2544 | { | ||
2545 | .start_resource = 12, | ||
2546 | .num_resource = 2, | ||
2547 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2548 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2549 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2550 | }, | ||
2551 | { | ||
2552 | .start_resource = 14, | ||
2553 | .num_resource = 0, | ||
2554 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2555 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2556 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2557 | }, | ||
2558 | { | ||
2559 | .start_resource = 14, | ||
2560 | .num_resource = 9, | ||
2561 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2562 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2563 | .host_id = HOST_ID_A72_2, | ||
2564 | }, | ||
2565 | { | ||
2566 | .start_resource = 23, | ||
2567 | .num_resource = 6, | ||
2568 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2569 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2570 | .host_id = HOST_ID_A72_3, | ||
2571 | }, | ||
2572 | { | ||
2573 | .start_resource = 29, | ||
2574 | .num_resource = 1, | ||
2575 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2576 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2577 | .host_id = HOST_ID_C7X_0_1, | ||
2578 | }, | ||
2579 | { | ||
2580 | .start_resource = 30, | ||
2581 | .num_resource = 1, | ||
2582 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2583 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2584 | .host_id = HOST_ID_C7X_1_1, | ||
2585 | }, | ||
2586 | { | ||
2587 | .start_resource = 31, | ||
2588 | .num_resource = 2, | ||
2589 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2590 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2591 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2592 | }, | ||
2593 | { | ||
2594 | .start_resource = 33, | ||
2595 | .num_resource = 1, | ||
2596 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2597 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2598 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2599 | }, | ||
2600 | { | ||
2601 | .start_resource = 34, | ||
2602 | .num_resource = 1, | ||
2603 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2604 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2605 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2606 | }, | ||
2607 | { | ||
2608 | .start_resource = 35, | ||
2609 | .num_resource = 1, | ||
2610 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2611 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2612 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2613 | }, | ||
2614 | { | ||
2615 | .start_resource = 36, | ||
2616 | .num_resource = 3, | ||
2617 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2618 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2619 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2620 | }, | ||
2621 | { | ||
2622 | .start_resource = 39, | ||
2623 | .num_resource = 2, | ||
2624 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2625 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2626 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2627 | }, | ||
2628 | { | ||
2629 | .start_resource = 41, | ||
2630 | .num_resource = 4, | ||
2631 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2632 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
2633 | .host_id = HOST_ID_ALL, | ||
2634 | }, | ||
2635 | /* MCU NAVSS UDMA High capacity Rx channels */ | ||
2636 | { | ||
2637 | .start_resource = 0, | ||
2638 | .num_resource = 0, | ||
2639 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2640 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
2641 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2642 | }, | ||
2643 | { | ||
2644 | .start_resource = 0, | ||
2645 | .num_resource = 2, | ||
2646 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2647 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
2648 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2649 | }, | ||
2650 | /* MCU NAVSS UDMA Normal capacity Tx channels */ | ||
2651 | { | ||
2652 | .start_resource = 2, | ||
2653 | .num_resource = 4, | ||
2654 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2655 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2656 | .host_id = HOST_ID_A72_2, | ||
2657 | }, | ||
2658 | { | ||
2659 | .start_resource = 6, | ||
2660 | .num_resource = 0, | ||
2661 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2662 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2663 | .host_id = HOST_ID_A72_3, | ||
2664 | }, | ||
2665 | { | ||
2666 | .start_resource = 6, | ||
2667 | .num_resource = 1, | ||
2668 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2669 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2670 | .host_id = HOST_ID_C7X_0_1, | ||
2671 | }, | ||
2672 | { | ||
2673 | .start_resource = 7, | ||
2674 | .num_resource = 1, | ||
2675 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2676 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2677 | .host_id = HOST_ID_C7X_1_1, | ||
2678 | }, | ||
2679 | { | ||
2680 | .start_resource = 8, | ||
2681 | .num_resource = 1, | ||
2682 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2683 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2684 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2685 | }, | ||
2686 | { | ||
2687 | .start_resource = 9, | ||
2688 | .num_resource = 1, | ||
2689 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2690 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2691 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2692 | }, | ||
2693 | { | ||
2694 | .start_resource = 10, | ||
2695 | .num_resource = 1, | ||
2696 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2697 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2698 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2699 | }, | ||
2700 | { | ||
2701 | .start_resource = 11, | ||
2702 | .num_resource = 1, | ||
2703 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2704 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2705 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2706 | }, | ||
2707 | { | ||
2708 | .start_resource = 12, | ||
2709 | .num_resource = 2, | ||
2710 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2711 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2712 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2713 | }, | ||
2714 | { | ||
2715 | .start_resource = 14, | ||
2716 | .num_resource = 0, | ||
2717 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2718 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2719 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2720 | }, | ||
2721 | { | ||
2722 | .start_resource = 14, | ||
2723 | .num_resource = 9, | ||
2724 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2725 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2726 | .host_id = HOST_ID_A72_2, | ||
2727 | }, | ||
2728 | { | ||
2729 | .start_resource = 23, | ||
2730 | .num_resource = 6, | ||
2731 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2732 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2733 | .host_id = HOST_ID_A72_3, | ||
2734 | }, | ||
2735 | { | ||
2736 | .start_resource = 29, | ||
2737 | .num_resource = 1, | ||
2738 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2739 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2740 | .host_id = HOST_ID_C7X_0_1, | ||
2741 | }, | ||
2742 | { | ||
2743 | .start_resource = 30, | ||
2744 | .num_resource = 1, | ||
2745 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2746 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2747 | .host_id = HOST_ID_C7X_1_1, | ||
2748 | }, | ||
2749 | { | ||
2750 | .start_resource = 31, | ||
2751 | .num_resource = 2, | ||
2752 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2753 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2754 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2755 | }, | ||
2756 | { | ||
2757 | .start_resource = 33, | ||
2758 | .num_resource = 1, | ||
2759 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2760 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2761 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2762 | }, | ||
2763 | { | ||
2764 | .start_resource = 34, | ||
2765 | .num_resource = 1, | ||
2766 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2767 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2768 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2769 | }, | ||
2770 | { | ||
2771 | .start_resource = 35, | ||
2772 | .num_resource = 1, | ||
2773 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2774 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2775 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2776 | }, | ||
2777 | { | ||
2778 | .start_resource = 36, | ||
2779 | .num_resource = 3, | ||
2780 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2781 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2782 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2783 | }, | ||
2784 | { | ||
2785 | .start_resource = 39, | ||
2786 | .num_resource = 2, | ||
2787 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2788 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2789 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2790 | }, | ||
2791 | { | ||
2792 | .start_resource = 41, | ||
2793 | .num_resource = 5, | ||
2794 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2795 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
2796 | .host_id = HOST_ID_ALL, | ||
2797 | }, | ||
2798 | /* MCU NAVSS UDMA High capacity Tx channels */ | ||
2799 | { | ||
2800 | .start_resource = 0, | ||
2801 | .num_resource = 0, | ||
2802 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2803 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
2804 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2805 | }, | ||
2806 | { | ||
2807 | .start_resource = 0, | ||
2808 | .num_resource = 2, | ||
2809 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMAP_0, | ||
2810 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
2811 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2812 | }, | ||
2813 | /* MCU NAVSS Interrupt aggregator Virtual interrupts */ | ||
2814 | { | ||
2815 | .start_resource = 22, | ||
2816 | .num_resource = 32, | ||
2817 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2818 | RESASG_SUBTYPE_IA_VINT), | ||
2819 | .host_id = HOST_ID_A72_2, | ||
2820 | }, | ||
2821 | { | ||
2822 | .start_resource = 54, | ||
2823 | .num_resource = 16, | ||
2824 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2825 | RESASG_SUBTYPE_IA_VINT), | ||
2826 | .host_id = HOST_ID_A72_3, | ||
2827 | }, | ||
2828 | { | ||
2829 | .start_resource = 70, | ||
2830 | .num_resource = 8, | ||
2831 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2832 | RESASG_SUBTYPE_IA_VINT), | ||
2833 | .host_id = HOST_ID_C7X_0_1, | ||
2834 | }, | ||
2835 | { | ||
2836 | .start_resource = 78, | ||
2837 | .num_resource = 8, | ||
2838 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2839 | RESASG_SUBTYPE_IA_VINT), | ||
2840 | .host_id = HOST_ID_C7X_1_1, | ||
2841 | }, | ||
2842 | { | ||
2843 | .start_resource = 86, | ||
2844 | .num_resource = 24, | ||
2845 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2846 | RESASG_SUBTYPE_IA_VINT), | ||
2847 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2848 | }, | ||
2849 | { | ||
2850 | .start_resource = 110, | ||
2851 | .num_resource = 8, | ||
2852 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2853 | RESASG_SUBTYPE_IA_VINT), | ||
2854 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2855 | }, | ||
2856 | { | ||
2857 | .start_resource = 118, | ||
2858 | .num_resource = 16, | ||
2859 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2860 | RESASG_SUBTYPE_IA_VINT), | ||
2861 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2862 | }, | ||
2863 | { | ||
2864 | .start_resource = 134, | ||
2865 | .num_resource = 16, | ||
2866 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2867 | RESASG_SUBTYPE_IA_VINT), | ||
2868 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2869 | }, | ||
2870 | { | ||
2871 | .start_resource = 150, | ||
2872 | .num_resource = 64, | ||
2873 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2874 | RESASG_SUBTYPE_IA_VINT), | ||
2875 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2876 | }, | ||
2877 | { | ||
2878 | .start_resource = 214, | ||
2879 | .num_resource = 4, | ||
2880 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2881 | RESASG_SUBTYPE_IA_VINT), | ||
2882 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2883 | }, | ||
2884 | { | ||
2885 | .start_resource = 218, | ||
2886 | .num_resource = 38, | ||
2887 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2888 | RESASG_SUBTYPE_IA_VINT), | ||
2889 | .host_id = HOST_ID_ALL, | ||
2890 | }, | ||
2891 | /* MCU NAVSS Interrupt aggregator Global events */ | ||
2892 | { | ||
2893 | .start_resource = 16406, | ||
2894 | .num_resource = 128, | ||
2895 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2896 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2897 | .host_id = HOST_ID_A72_2, | ||
2898 | }, | ||
2899 | { | ||
2900 | .start_resource = 16534, | ||
2901 | .num_resource = 128, | ||
2902 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2903 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2904 | .host_id = HOST_ID_A72_3, | ||
2905 | }, | ||
2906 | { | ||
2907 | .start_resource = 16662, | ||
2908 | .num_resource = 64, | ||
2909 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2910 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2911 | .host_id = HOST_ID_C7X_0_1, | ||
2912 | }, | ||
2913 | { | ||
2914 | .start_resource = 16726, | ||
2915 | .num_resource = 64, | ||
2916 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2917 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2918 | .host_id = HOST_ID_C7X_1_1, | ||
2919 | }, | ||
2920 | { | ||
2921 | .start_resource = 16790, | ||
2922 | .num_resource = 128, | ||
2923 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2924 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2925 | .host_id = HOST_ID_MAIN_0_R5_0, | ||
2926 | }, | ||
2927 | { | ||
2928 | .start_resource = 16918, | ||
2929 | .num_resource = 128, | ||
2930 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2931 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2932 | .host_id = HOST_ID_MAIN_0_R5_2, | ||
2933 | }, | ||
2934 | { | ||
2935 | .start_resource = 17046, | ||
2936 | .num_resource = 128, | ||
2937 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2938 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2939 | .host_id = HOST_ID_MAIN_1_R5_0, | ||
2940 | }, | ||
2941 | { | ||
2942 | .start_resource = 17174, | ||
2943 | .num_resource = 128, | ||
2944 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2945 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2946 | .host_id = HOST_ID_MAIN_1_R5_2, | ||
2947 | }, | ||
2948 | { | ||
2949 | .start_resource = 17302, | ||
2950 | .num_resource = 256, | ||
2951 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2952 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2953 | .host_id = HOST_ID_MCU_0_R5_0, | ||
2954 | }, | ||
2955 | { | ||
2956 | .start_resource = 17558, | ||
2957 | .num_resource = 64, | ||
2958 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2959 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2960 | .host_id = HOST_ID_MCU_0_R5_2, | ||
2961 | }, | ||
2962 | { | ||
2963 | .start_resource = 17622, | ||
2964 | .num_resource = 298, | ||
2965 | .type = RESASG_UTYPE (J721S2_DEV_MCU_NAVSS0_UDMASS_INTA_0, | ||
2966 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
2967 | .host_id = HOST_ID_ALL, | ||
2968 | }, | ||
2969 | /* MCU Security Accelerator Packet DMA Timer manager event */ | ||
2970 | { | ||
2971 | .start_resource = 0, | ||
2972 | .num_resource = 1024, | ||
2973 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
2974 | RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES), | ||
2975 | .host_id = HOST_ID_ALL, | ||
2976 | }, | ||
2977 | /* MCU Security Accelerator Packet DMA Tx channel error event */ | ||
2978 | { | ||
2979 | .start_resource = 4096, | ||
2980 | .num_resource = 2, | ||
2981 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
2982 | RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES), | ||
2983 | .host_id = HOST_ID_ALL, | ||
2984 | }, | ||
2985 | /* MCU Security Accelerator Packet DMA Tx flow completion event */ | ||
2986 | { | ||
2987 | .start_resource = 4608, | ||
2988 | .num_resource = 8, | ||
2989 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
2990 | RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES), | ||
2991 | .host_id = HOST_ID_ALL, | ||
2992 | }, | ||
2993 | /* MCU Security Accelerator Packet DMA Rx channel error event */ | ||
2994 | { | ||
2995 | .start_resource = 5120, | ||
2996 | .num_resource = 4, | ||
2997 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
2998 | RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES), | ||
2999 | .host_id = HOST_ID_ALL, | ||
3000 | }, | ||
3001 | /* MCU Security Accelerator Packet DMA Rx flow completion event */ | ||
3002 | { | ||
3003 | .start_resource = 5632, | ||
3004 | .num_resource = 16, | ||
3005 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
3006 | RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES), | ||
3007 | .host_id = HOST_ID_ALL, | ||
3008 | }, | ||
3009 | /* MCU Security Accelerator Packet DMA Rx flow starvation event */ | ||
3010 | { | ||
3011 | .start_resource = 6144, | ||
3012 | .num_resource = 16, | ||
3013 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
3014 | RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES), | ||
3015 | .host_id = HOST_ID_ALL, | ||
3016 | }, | ||
3017 | /* MCU Security Accelerator Packet DMA Rx flow firewall event */ | ||
3018 | { | ||
3019 | .start_resource = 6656, | ||
3020 | .num_resource = 16, | ||
3021 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_INTAGGR_0, | ||
3022 | RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES), | ||
3023 | .host_id = HOST_ID_ALL, | ||
3024 | }, | ||
3025 | /* MCU Security Accelerator Packet DMA Global config */ | ||
3026 | { | ||
3027 | .start_resource = 0, | ||
3028 | .num_resource = 1, | ||
3029 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_PKTDMA_0, | ||
3030 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), | ||
3031 | .host_id = HOST_ID_ALL, | ||
3032 | }, | ||
3033 | /* MCU Security Accelerator Packet DMA SA2UL Rx channel0 flows */ | ||
3034 | { | ||
3035 | .start_resource = 0, | ||
3036 | .num_resource = 8, | ||
3037 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_PKTDMA_0, | ||
3038 | RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN), | ||
3039 | .host_id = HOST_ID_ALL, | ||
3040 | }, | ||
3041 | /* MCU Security Accelerator Packet DMA SA2UL Rx channel1 flows */ | ||
3042 | { | ||
3043 | .start_resource = 8, | ||
3044 | .num_resource = 8, | ||
3045 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_PKTDMA_0, | ||
3046 | RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN), | ||
3047 | .host_id = HOST_ID_ALL, | ||
3048 | }, | ||
3049 | /* MCU Security Accelerator Packet DMA Ring accelerator error event */ | ||
3050 | { | ||
3051 | .start_resource = 0, | ||
3052 | .num_resource = 1, | ||
3053 | .type = RESASG_UTYPE (J721S2_DEV_MCU_SA3_SS0_RINGACC_0, | ||
3054 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
3055 | .host_id = HOST_ID_ALL, | ||
3056 | }, | ||
3057 | }, | ||
3058 | }; | ||
diff --git a/soc/j721s2/evm/sec-cfg.c b/soc/j721s2/evm/sec-cfg.c new file mode 100644 index 000000000..e0aa3fa53 --- /dev/null +++ b/soc/j721s2/evm/sec-cfg.c | |||
@@ -0,0 +1,117 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Security Configuration Data | ||
3 | * | ||
4 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
5 | * | ||
6 | * Redistribution and use in source and binary forms, with or without | ||
7 | * modification, are permitted provided that the following conditions | ||
8 | * are met: | ||
9 | * | ||
10 | * Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * | ||
13 | * Redistributions in binary form must reproduce the above copyright | ||
14 | * notice, this list of conditions and the following disclaimer in the | ||
15 | * documentation and/or other materials provided with the | ||
16 | * distribution. | ||
17 | * | ||
18 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
19 | * its contributors may be used to endorse or promote products derived | ||
20 | * from this software without specific prior written permission. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
23 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
25 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
26 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
27 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
28 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
29 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
30 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #include "common.h" | ||
36 | |||
37 | const struct boardcfg_security j721s2_boardcfg_security_data = { | ||
38 | /* boardcfg_abi_rev */ | ||
39 | .rev = { | ||
40 | .boardcfg_abi_maj = 0x0, | ||
41 | .boardcfg_abi_min = 0x1, | ||
42 | }, | ||
43 | |||
44 | /* boardcfg_proc_acl */ | ||
45 | .processor_acl_list = { | ||
46 | .subhdr = { | ||
47 | .magic = BOARDCFG_PROC_ACL_MAGIC_NUM, | ||
48 | .size = sizeof(struct boardcfg_proc_acl), | ||
49 | }, | ||
50 | .proc_acl_entries = {{ 0 } }, | ||
51 | }, | ||
52 | |||
53 | /* boardcfg_host_hierarchy */ | ||
54 | .host_hierarchy = { | ||
55 | .subhdr = { | ||
56 | .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM, | ||
57 | .size = sizeof(struct boardcfg_host_hierarchy), | ||
58 | }, | ||
59 | .host_hierarchy_entries = {{ 0 } }, | ||
60 | }, | ||
61 | |||
62 | /* OTP access configuration */ | ||
63 | .otp_config = { | ||
64 | .subhdr = { | ||
65 | .magic = BOARDCFG_OTP_CFG_MAGIC_NUM, | ||
66 | .size = sizeof(struct boardcfg_extended_otp), | ||
67 | }, | ||
68 | /* Host ID 0 is DMSC. This means no host has write access to OTP array */ | ||
69 | .write_host_id = 0, | ||
70 | /* This is an array with 32 entries */ | ||
71 | .otp_entry = {{ 0 } }, | ||
72 | }, | ||
73 | |||
74 | /* DKEK configuration */ | ||
75 | .dkek_config = { | ||
76 | .subhdr = { | ||
77 | .magic = BOARDCFG_DKEK_CFG_MAGIC_NUM, | ||
78 | .size = sizeof(struct boardcfg_dkek), | ||
79 | }, | ||
80 | .allowed_hosts = { HOST_ID_ALL, 0, 0, 0 }, | ||
81 | .allow_dkek_export_tisci = 0x5A, | ||
82 | .rsvd = {0, 0, 0}, | ||
83 | }, | ||
84 | |||
85 | /* SA2UL RM config is not supported on this device */ | ||
86 | .sa2ul_cfg = { | ||
87 | .subhdr = { | ||
88 | .magic = BOARDCFG_SA2UL_CFG_MAGIC_NUM_RSVD, | ||
89 | .size = 0, | ||
90 | }, | ||
91 | |||
92 | .rsvd = {0, 0, 0, 0}, | ||
93 | }, | ||
94 | |||
95 | /* Secure JTAG Unlock Configuration */ | ||
96 | .sec_dbg_config = { | ||
97 | .subhdr = { | ||
98 | .magic = BOARDCFG_SEC_DBG_CTRL_MAGIC_NUM, | ||
99 | .size = sizeof(struct boardcfg_secure_debug_config), | ||
100 | }, | ||
101 | .allow_jtag_unlock = 0U, | ||
102 | .allow_wildcard_unlock = 0x0, | ||
103 | .min_cert_rev = 0x0, | ||
104 | .jtag_unlock_hosts = {0, 0, 0, 0}, | ||
105 | }, | ||
106 | |||
107 | /* Secure Handover Configuration */ | ||
108 | .sec_handover_cfg = { | ||
109 | .subhdr = { | ||
110 | .magic = BOARDCFG_SEC_HANDOVER_CFG_MAGIC_NUM, | ||
111 | .size = sizeof(struct boardcfg_sec_handover), | ||
112 | }, | ||
113 | .handover_msg_sender = 0, | ||
114 | .handover_to_host_id = 0, | ||
115 | .rsvd = {0,0,0,0}, | ||
116 | }, | ||
117 | }; | ||
diff --git a/soc/j721s2/evm/sysfw_img_cfg.h b/soc/j721s2/evm/sysfw_img_cfg.h new file mode 100644 index 000000000..acd117cf1 --- /dev/null +++ b/soc/j721s2/evm/sysfw_img_cfg.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * K3 System Firmware Resource Management Board Config Data | ||
3 | * Auto generated from K3 Resource Partitioning tool | ||
4 | * | ||
5 | * | ||
6 | * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
7 | * | ||
8 | * Redistribution and use in source and binary forms, with or without | ||
9 | * modification, are permitted provided that the following conditions | ||
10 | * are met: | ||
11 | * | ||
12 | * Redistributions of source code must retain the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer. | ||
14 | * | ||
15 | * Redistributions in binary form must reproduce the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer in the | ||
17 | * documentation and/or other materials provided with the | ||
18 | * distribution. | ||
19 | * | ||
20 | * Neither the name of Texas Instruments Incorporated nor the names of | ||
21 | * its contributors may be used to endorse or promote products derived | ||
22 | * from this software without specific prior written permission. | ||
23 | * | ||
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
25 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
26 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | ||
27 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | ||
28 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | ||
29 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | ||
30 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
31 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
32 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
33 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
35 | */ | ||
36 | |||
37 | #ifndef SYSFW_IMG_CFG_H | ||
38 | #define SYSFW_IMG_CFG_H | ||
39 | |||
40 | #define BOARDCFG_RM_RESASG_ENTRIES 403 | ||
41 | |||
42 | #endif /* SYSFW_IMG_CFG_H */ | ||