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authorVignesh Raghavendra2022-12-02 04:56:16 -0600
committerVignesh Raghavendra2022-12-03 23:21:53 -0600
commitaae4f16a1ac28d4e5a571d86466feac4c8b65722 (patch)
treeda8cf9309519d240cc7b2a3e7a582a6a46e3eb6e /soc
parentfe663d31c4884f1d7aeb4a79dd262bda819c5737 (diff)
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Add base board, PM, RM and Security cfg data for AM62AX based on latest k3-resource-partitioning tool data Note that SA3UL is shared with public world. Resource allocation is similar to AM62x. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'soc')
-rw-r--r--soc/am62ax/Makefile45
-rw-r--r--soc/am62ax/evm/board-cfg.c93
-rw-r--r--soc/am62ax/evm/pm-cfg.c43
-rw-r--r--soc/am62ax/evm/rm-cfg.c1085
-rw-r--r--soc/am62ax/evm/sec-cfg.c121
-rw-r--r--soc/am62ax/evm/sysfw_img_cfg.h43
-rw-r--r--soc/am62ax/evm/tifs-rm-cfg.c956
7 files changed, 2386 insertions, 0 deletions
diff --git a/soc/am62ax/Makefile b/soc/am62ax/Makefile
new file mode 100644
index 000000000..02c4c701a
--- /dev/null
+++ b/soc/am62ax/Makefile
@@ -0,0 +1,45 @@
1#
2# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions
6# are met:
7#
8# Redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer.
10#
11# Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the
14# distribution.
15#
16# Neither the name of Texas Instruments Incorporated nor the names of
17# its contributors may be used to endorse or promote products derived
18# from this software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31#
32
33SBL_LOADADDDR ?= 0x43c00000
34COMBINED_TIFS_BRDCFG_LOADADDR ?= 0x67000
35COMBINED_DM_BRDCFG_LOADADDR ?= 0x43c3c800
36LOADADDR ?= 0x40000
37SCIFS = fs
38
39.PHONY: all
40ifeq (,$(SBL))
41all: _objtree_build $(ITB) sysfw.itb
42 @echo "**WARNING**: AM62a requires SBL to be provided (allowing temporarily)"
43else
44all: _objtree_build $(ITB) sysfw.itb tiboot3.bin
45endif
diff --git a/soc/am62ax/evm/board-cfg.c b/soc/am62ax/evm/board-cfg.c
new file mode 100644
index 000000000..e3278baac
--- /dev/null
+++ b/soc/am62ax/evm/board-cfg.c
@@ -0,0 +1,93 @@
1/*
2 * K3 System Firmware Board Configuration Data
3 *
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg am62x_boardcfg_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43
44 /* boardcfg_control */
45 .control = {
46 .subhdr = {
47 .magic = BOARDCFG_CONTROL_MAGIC_NUM,
48 .size = sizeof(struct boardcfg_control),
49 },
50 .main_isolation_enable = 0x5A,
51 .main_isolation_hostid = 0x2,
52 },
53
54 /* boardcfg sec_proxy */
55 .secproxy = {
56 .subhdr = {
57 .magic = BOARDCFG_SECPROXY_MAGIC_NUM,
58 .size = sizeof(struct boardcfg_secproxy),
59 },
60 .scaling_factor = 0x1,
61 .scaling_profile = 0x1,
62 .disable_main_nav_secure_proxy = 0,
63 },
64
65 /* boardcfg_msmc */
66 .msmc = {
67 .subhdr = {
68 .magic = BOARDCFG_MSMC_MAGIC_NUM,
69 .size = sizeof(struct boardcfg_msmc),
70 },
71 .msmc_cache_size = 0x10,
72 },
73
74 /* boardcfg_dbg_cfg */
75 .debug_cfg = {
76 .subhdr = {
77 .magic = BOARDCFG_DBG_CFG_MAGIC_NUM,
78 .size = sizeof(struct boardcfg_dbg_cfg),
79 },
80
81#ifdef ENABLE_TRACE
82 .trace_dst_enables = BOARDCFG_TRACE_DST_UART0 |
83 BOARDCFG_TRACE_DST_ITM |
84 BOARDCFG_TRACE_DST_MEM,
85 .trace_src_enables = BOARDCFG_TRACE_SRC_PM |
86 BOARDCFG_TRACE_SRC_RM |
87 BOARDCFG_TRACE_SRC_SEC |
88 BOARDCFG_TRACE_SRC_BASE |
89 BOARDCFG_TRACE_SRC_USER |
90 BOARDCFG_TRACE_SRC_SUPR,
91#endif
92 },
93};
diff --git a/soc/am62ax/evm/pm-cfg.c b/soc/am62ax/evm/pm-cfg.c
new file mode 100644
index 000000000..f8b9d7a4a
--- /dev/null
+++ b/soc/am62ax/evm/pm-cfg.c
@@ -0,0 +1,43 @@
1/*
2 * K3 System Firmware Power Management Configuration Data
3 *
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37const struct boardcfg_pm am62x_boardcfg_pm_data = {
38 /* boardcfg_abi_rev */
39 .rev = {
40 .boardcfg_abi_maj = 0x0,
41 .boardcfg_abi_min = 0x1,
42 },
43};
diff --git a/soc/am62ax/evm/rm-cfg.c b/soc/am62ax/evm/rm-cfg.c
new file mode 100644
index 000000000..73fe32b2f
--- /dev/null
+++ b/soc/am62ax/evm/rm-cfg.c
@@ -0,0 +1,1085 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37#include <hosts.h>
38#include <devices.h>
39#include <resasg_types.h>
40
41const struct boardcfg_rm_local am62a_boardcfg_rm_data = {
42 .rm_boardcfg = {
43 /* boardcfg_abi_rev */
44 .rev = {
45 .boardcfg_abi_maj = 0x0,
46 .boardcfg_abi_min = 0x1,
47 },
48
49 /* boardcfg_rm_host_cfg */
50 .host_cfg = {
51 .subhdr = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 },
55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_A53_2,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_MCU_0_R5_0,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_MAIN_0_R5_1,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 }
81 },
82
83 /* boardcfg_rm_resasg */
84 .resasg = {
85 .subhdr = {
86 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
87 .size = sizeof (struct boardcfg_rm_resasg),
88 },
89 .resasg_entries_size =
90 BOARDCFG_RM_RESASG_ENTRIES *
91 sizeof (struct boardcfg_rm_resasg_entry),
92 .reserved = 0,
93 /* .resasg_entries is set via boardcfg_rm_local */
94 },
95 },
96
97 /* This is actually part of .resasg */
98 .resasg_entries = {
99 /* Compare event Interrupt Router */
100 {
101 .start_resource = 0,
102 .num_resource = 16,
103 .type = RESASG_UTYPE (AM62A_DEV_CMP_EVENT_INTROUTER0,
104 RESASG_SUBTYPE_IR_OUTPUT),
105 .host_id = HOST_ID_A53_2,
106 },
107 {
108 .start_resource = 16,
109 .num_resource = 4,
110 .type = RESASG_UTYPE (AM62A_DEV_CMP_EVENT_INTROUTER0,
111 RESASG_SUBTYPE_IR_OUTPUT),
112 .host_id = HOST_ID_MAIN_0_R5_0,
113 },
114 {
115 .start_resource = 16,
116 .num_resource = 4,
117 .type = RESASG_UTYPE (AM62A_DEV_CMP_EVENT_INTROUTER0,
118 RESASG_SUBTYPE_IR_OUTPUT),
119 .host_id = HOST_ID_MAIN_0_R5_1,
120 },
121 {
122 .start_resource = 20,
123 .num_resource = 22,
124 .type = RESASG_UTYPE (AM62A_DEV_CMP_EVENT_INTROUTER0,
125 RESASG_SUBTYPE_IR_OUTPUT),
126 .host_id = HOST_ID_MCU_0_R5_0,
127 },
128 /* MAIN GPIO Interrupt Router */
129 {
130 .start_resource = 0,
131 .num_resource = 16,
132 .type = RESASG_UTYPE (AM62A_DEV_MAIN_GPIOMUX_INTROUTER0,
133 RESASG_SUBTYPE_IR_OUTPUT),
134 .host_id = HOST_ID_A53_2,
135 },
136 {
137 .start_resource = 34,
138 .num_resource = 2,
139 .type = RESASG_UTYPE (AM62A_DEV_MAIN_GPIOMUX_INTROUTER0,
140 RESASG_SUBTYPE_IR_OUTPUT),
141 .host_id = HOST_ID_MCU_0_R5_0,
142 },
143 /* WKUP MCU GPIO Interrupt Router */
144 {
145 .start_resource = 0,
146 .num_resource = 4,
147 .type = RESASG_UTYPE (AM62A_DEV_WKUP_MCU_GPIOMUX_INTROUTER0,
148 RESASG_SUBTYPE_IR_OUTPUT),
149 .host_id = HOST_ID_A53_2,
150 },
151 {
152 .start_resource = 4,
153 .num_resource = 4,
154 .type = RESASG_UTYPE (AM62A_DEV_WKUP_MCU_GPIOMUX_INTROUTER0,
155 RESASG_SUBTYPE_IR_OUTPUT),
156 .host_id = HOST_ID_MCU_0_R5_0,
157 },
158 /* Timesync Interrupt Router */
159 {
160 .start_resource = 0,
161 .num_resource = 26,
162 .type = RESASG_UTYPE (AM62A_DEV_TIMESYNC_EVENT_ROUTER0,
163 RESASG_SUBTYPE_IR_OUTPUT),
164 .host_id = HOST_ID_ALL,
165 },
166 /* Block Copy DMA Global event trigger */
167 {
168 .start_resource = 50176,
169 .num_resource = 164,
170 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
171 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
172 .host_id = HOST_ID_ALL,
173 },
174 /* Block Copy DMA Global config */
175 {
176 .start_resource = 0,
177 .num_resource = 1,
178 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
179 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
180 .host_id = HOST_ID_ALL,
181 },
182 /* Block Copy DMA Rings for Block copy channel */
183 {
184 .start_resource = 0,
185 .num_resource = 18,
186 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
187 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
188 .host_id = HOST_ID_A53_2,
189 },
190 {
191 .start_resource = 18,
192 .num_resource = 6,
193 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
194 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
195 .host_id = HOST_ID_MAIN_0_R5_0,
196 },
197 {
198 .start_resource = 18,
199 .num_resource = 6,
200 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
201 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
202 .host_id = HOST_ID_MAIN_0_R5_1,
203 },
204 {
205 .start_resource = 24,
206 .num_resource = 2,
207 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
208 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
209 .host_id = HOST_ID_MCU_0_R5_0,
210 },
211 {
212 .start_resource = 26,
213 .num_resource = 6,
214 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
215 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
216 .host_id = HOST_ID_ALL,
217 },
218 /* Block Copy DMA Rings for Split TR Rx channel */
219 {
220 .start_resource = 54,
221 .num_resource = 18,
222 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
223 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
224 .host_id = HOST_ID_A53_2,
225 },
226 {
227 .start_resource = 72,
228 .num_resource = 6,
229 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
230 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
231 .host_id = HOST_ID_MAIN_0_R5_0,
232 },
233 {
234 .start_resource = 72,
235 .num_resource = 6,
236 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
237 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
238 .host_id = HOST_ID_MAIN_0_R5_1,
239 },
240 {
241 .start_resource = 78,
242 .num_resource = 2,
243 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
244 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
245 .host_id = HOST_ID_MCU_0_R5_0,
246 },
247 {
248 .start_resource = 80,
249 .num_resource = 2,
250 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
251 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
252 .host_id = HOST_ID_ALL,
253 },
254 /* Block Copy DMA Rings for Split TR Tx channel */
255 {
256 .start_resource = 32,
257 .num_resource = 12,
258 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
259 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
260 .host_id = HOST_ID_A53_2,
261 },
262 {
263 .start_resource = 44,
264 .num_resource = 6,
265 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
266 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
267 .host_id = HOST_ID_MAIN_0_R5_0,
268 },
269 {
270 .start_resource = 44,
271 .num_resource = 6,
272 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
273 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
274 .host_id = HOST_ID_MAIN_0_R5_1,
275 },
276 {
277 .start_resource = 50,
278 .num_resource = 2,
279 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
280 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
281 .host_id = HOST_ID_MCU_0_R5_0,
282 },
283 {
284 .start_resource = 52,
285 .num_resource = 2,
286 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
287 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
288 .host_id = HOST_ID_ALL,
289 },
290 /* Block Copy DMA Block copy channel */
291 {
292 .start_resource = 0,
293 .num_resource = 18,
294 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
295 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
296 .host_id = HOST_ID_A53_2,
297 },
298 {
299 .start_resource = 18,
300 .num_resource = 6,
301 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
302 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
303 .host_id = HOST_ID_MAIN_0_R5_0,
304 },
305 {
306 .start_resource = 18,
307 .num_resource = 6,
308 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
309 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
310 .host_id = HOST_ID_MAIN_0_R5_1,
311 },
312 {
313 .start_resource = 24,
314 .num_resource = 2,
315 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
316 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
317 .host_id = HOST_ID_MCU_0_R5_0,
318 },
319 {
320 .start_resource = 26,
321 .num_resource = 6,
322 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
323 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
324 .host_id = HOST_ID_ALL,
325 },
326 /* Block Copy DMA Split TR Rx channel */
327 {
328 .start_resource = 0,
329 .num_resource = 18,
330 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
331 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
332 .host_id = HOST_ID_A53_2,
333 },
334 {
335 .start_resource = 18,
336 .num_resource = 6,
337 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
338 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
339 .host_id = HOST_ID_MAIN_0_R5_0,
340 },
341 {
342 .start_resource = 18,
343 .num_resource = 6,
344 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
345 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
346 .host_id = HOST_ID_MAIN_0_R5_1,
347 },
348 {
349 .start_resource = 24,
350 .num_resource = 2,
351 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
352 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
353 .host_id = HOST_ID_MCU_0_R5_0,
354 },
355 {
356 .start_resource = 26,
357 .num_resource = 2,
358 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
359 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
360 .host_id = HOST_ID_ALL,
361 },
362 /* Block Copy DMA Split TR Tx channel */
363 {
364 .start_resource = 0,
365 .num_resource = 12,
366 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
367 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
368 .host_id = HOST_ID_A53_2,
369 },
370 {
371 .start_resource = 12,
372 .num_resource = 6,
373 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
374 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
375 .host_id = HOST_ID_MAIN_0_R5_0,
376 },
377 {
378 .start_resource = 12,
379 .num_resource = 6,
380 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
381 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
382 .host_id = HOST_ID_MAIN_0_R5_1,
383 },
384 {
385 .start_resource = 18,
386 .num_resource = 2,
387 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
388 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
389 .host_id = HOST_ID_MCU_0_R5_0,
390 },
391 {
392 .start_resource = 20,
393 .num_resource = 2,
394 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
395 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
396 .host_id = HOST_ID_ALL,
397 },
398 /* DMASS Interrupt aggregator Virtual interrupts */
399 {
400 .start_resource = 6,
401 .num_resource = 34,
402 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
403 RESASG_SUBTYPE_IA_VINT),
404 .host_id = HOST_ID_A53_2,
405 },
406 {
407 .start_resource = 44,
408 .num_resource = 36,
409 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
410 RESASG_SUBTYPE_IA_VINT),
411 .host_id = HOST_ID_MAIN_0_R5_0,
412 },
413 {
414 .start_resource = 44,
415 .num_resource = 36,
416 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
417 RESASG_SUBTYPE_IA_VINT),
418 .host_id = HOST_ID_MAIN_0_R5_1,
419 },
420 {
421 .start_resource = 168,
422 .num_resource = 8,
423 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
424 RESASG_SUBTYPE_IA_VINT),
425 .host_id = HOST_ID_MCU_0_R5_0,
426 },
427 /* DMASS Interrupt aggregator Global events */
428 {
429 .start_resource = 14,
430 .num_resource = 512,
431 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
432 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
433 .host_id = HOST_ID_A53_2,
434 },
435 {
436 .start_resource = 526,
437 .num_resource = 256,
438 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
439 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
440 .host_id = HOST_ID_MAIN_0_R5_0,
441 },
442 {
443 .start_resource = 526,
444 .num_resource = 256,
445 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
446 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
447 .host_id = HOST_ID_MAIN_0_R5_1,
448 },
449 {
450 .start_resource = 782,
451 .num_resource = 128,
452 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
453 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
454 .host_id = HOST_ID_MCU_0_R5_0,
455 },
456 {
457 .start_resource = 910,
458 .num_resource = 626,
459 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
460 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
461 .host_id = HOST_ID_ALL,
462 },
463 /* DMASS timer manager event */
464 {
465 .start_resource = 0,
466 .num_resource = 1024,
467 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
468 RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
469 .host_id = HOST_ID_ALL,
470 },
471 /* DMASS Packet DMA Tx channel error event */
472 {
473 .start_resource = 4096,
474 .num_resource = 29,
475 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
476 RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
477 .host_id = HOST_ID_ALL,
478 },
479 /* DMASS Packet DMA Tx flow completion event */
480 {
481 .start_resource = 4608,
482 .num_resource = 99,
483 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
484 RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
485 .host_id = HOST_ID_ALL,
486 },
487 /* DMASS Packet DMA Rx channel error event */
488 {
489 .start_resource = 5120,
490 .num_resource = 24,
491 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
492 RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
493 .host_id = HOST_ID_ALL,
494 },
495 /* DMASS Packet DMA Rx flow completion event */
496 {
497 .start_resource = 5632,
498 .num_resource = 51,
499 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
500 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
501 .host_id = HOST_ID_ALL,
502 },
503 /* DMASS Packet DMA Rx flow starvation event */
504 {
505 .start_resource = 6144,
506 .num_resource = 51,
507 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
508 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
509 .host_id = HOST_ID_ALL,
510 },
511 /* DMASS Packet DMA Rx flow firewall event */
512 {
513 .start_resource = 6656,
514 .num_resource = 51,
515 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
516 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
517 .host_id = HOST_ID_ALL,
518 },
519 /* Block copy DMA BC channel error event */
520 {
521 .start_resource = 8192,
522 .num_resource = 32,
523 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
524 RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
525 .host_id = HOST_ID_ALL,
526 },
527 /* Block copy DMA BC channel data completion event */
528 {
529 .start_resource = 8704,
530 .num_resource = 32,
531 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
532 RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
533 .host_id = HOST_ID_ALL,
534 },
535 /* Block copy DMA BC channel ring completion event */
536 {
537 .start_resource = 9216,
538 .num_resource = 32,
539 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
540 RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
541 .host_id = HOST_ID_ALL,
542 },
543 /* Block copy DMA Tx channel error event */
544 {
545 .start_resource = 9728,
546 .num_resource = 22,
547 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
548 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
549 .host_id = HOST_ID_ALL,
550 },
551 /* Block copy DMA Tx channel data completion event */
552 {
553 .start_resource = 10240,
554 .num_resource = 22,
555 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
556 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
557 .host_id = HOST_ID_ALL,
558 },
559 /* Block copy DMA Tx channel ring completion event */
560 {
561 .start_resource = 10752,
562 .num_resource = 22,
563 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
564 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
565 .host_id = HOST_ID_ALL,
566 },
567 /* Block copy DMA Rx channel error event */
568 {
569 .start_resource = 11264,
570 .num_resource = 28,
571 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
572 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
573 .host_id = HOST_ID_ALL,
574 },
575 /* Block copy DMA Rx channel data completion event */
576 {
577 .start_resource = 11776,
578 .num_resource = 28,
579 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
580 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
581 .host_id = HOST_ID_ALL,
582 },
583 /* Block copy DMA Rx channel ring completion event */
584 {
585 .start_resource = 12288,
586 .num_resource = 28,
587 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
588 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
589 .host_id = HOST_ID_ALL,
590 },
591 /* DMASS DMASS UDMA global config */
592 {
593 .start_resource = 0,
594 .num_resource = 1,
595 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
596 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
597 .host_id = HOST_ID_ALL,
598 },
599 /* DMASS Packet DMA Free rings for Tx channel */
600 {
601 .start_resource = 0,
602 .num_resource = 10,
603 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
604 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
605 .host_id = HOST_ID_A53_2,
606 },
607 {
608 .start_resource = 10,
609 .num_resource = 3,
610 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
611 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
612 .host_id = HOST_ID_MAIN_0_R5_0,
613 },
614 {
615 .start_resource = 10,
616 .num_resource = 3,
617 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
618 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
619 .host_id = HOST_ID_MAIN_0_R5_1,
620 },
621 {
622 .start_resource = 13,
623 .num_resource = 3,
624 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
625 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
626 .host_id = HOST_ID_MCU_0_R5_0,
627 },
628 {
629 .start_resource = 16,
630 .num_resource = 3,
631 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
632 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
633 .host_id = HOST_ID_ALL,
634 },
635 /* DMASS Packet DMA Rings for CPSW Tx channel */
636 {
637 .start_resource = 19,
638 .num_resource = 64,
639 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
640 RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
641 .host_id = HOST_ID_A53_2,
642 },
643 {
644 .start_resource = 19,
645 .num_resource = 64,
646 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
647 RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
648 .host_id = HOST_ID_MCU_0_R5_0,
649 },
650 /* DMASS Packet DMA Rings for SA2UL Tx channel0 */
651 {
652 .start_resource = 83,
653 .num_resource = 8,
654 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
655 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
656 .host_id = HOST_ID_A53_2,
657 },
658 /* DMASS Packet DMA Rings for SA2UL Tx channel1 */
659 {
660 .start_resource = 91,
661 .num_resource = 8,
662 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
663 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
664 .host_id = HOST_ID_A53_2,
665 },
666 /* DMASS Packet DMA Free rings for Rx channel */
667 {
668 .start_resource = 99,
669 .num_resource = 10,
670 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
671 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
672 .host_id = HOST_ID_A53_2,
673 },
674 {
675 .start_resource = 109,
676 .num_resource = 3,
677 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
678 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
679 .host_id = HOST_ID_MAIN_0_R5_0,
680 },
681 {
682 .start_resource = 109,
683 .num_resource = 3,
684 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
685 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
686 .host_id = HOST_ID_MAIN_0_R5_1,
687 },
688 {
689 .start_resource = 112,
690 .num_resource = 3,
691 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
692 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
693 .host_id = HOST_ID_MCU_0_R5_0,
694 },
695 {
696 .start_resource = 115,
697 .num_resource = 3,
698 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
699 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
700 .host_id = HOST_ID_ALL,
701 },
702 /* DMASS Packet DMA Rings for CPSW Rx channel */
703 {
704 .start_resource = 118,
705 .num_resource = 16,
706 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
707 RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
708 .host_id = HOST_ID_A53_2,
709 },
710 {
711 .start_resource = 118,
712 .num_resource = 16,
713 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
714 RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
715 .host_id = HOST_ID_MCU_0_R5_0,
716 },
717 /* DMASS Packet DMA Rings for SA2UL Rx channel0 */
718 {
719 .start_resource = 134,
720 .num_resource = 8,
721 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
722 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
723 .host_id = HOST_ID_A53_2,
724 },
725 /* DMASS Packet DMA Rings for SA2UL Rx channel1 */
726 {
727 .start_resource = 134,
728 .num_resource = 8,
729 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
730 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
731 .host_id = HOST_ID_A53_2,
732 },
733 /* DMASS Packet DMA Rings for SA2UL Rx channel2 */
734 {
735 .start_resource = 142,
736 .num_resource = 8,
737 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
738 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
739 .host_id = HOST_ID_A53_2,
740 },
741 /* DMASS Packet DMA Rings for SA2UL Rx channel3 */
742 {
743 .start_resource = 142,
744 .num_resource = 8,
745 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
746 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
747 .host_id = HOST_ID_A53_2,
748 },
749 /* DMASS Packet DMA Free Tx channel */
750 {
751 .start_resource = 0,
752 .num_resource = 10,
753 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
754 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
755 .host_id = HOST_ID_A53_2,
756 },
757 {
758 .start_resource = 10,
759 .num_resource = 3,
760 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
761 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
762 .host_id = HOST_ID_MAIN_0_R5_0,
763 },
764 {
765 .start_resource = 10,
766 .num_resource = 3,
767 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
768 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
769 .host_id = HOST_ID_MAIN_0_R5_1,
770 },
771 {
772 .start_resource = 13,
773 .num_resource = 3,
774 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
775 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
776 .host_id = HOST_ID_MCU_0_R5_0,
777 },
778 {
779 .start_resource = 16,
780 .num_resource = 3,
781 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
782 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
783 .host_id = HOST_ID_ALL,
784 },
785 /* DMASS Packet DMA CPSW Tx channel */
786 {
787 .start_resource = 19,
788 .num_resource = 8,
789 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
790 RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
791 .host_id = HOST_ID_A53_2,
792 },
793 {
794 .start_resource = 19,
795 .num_resource = 8,
796 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
797 RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
798 .host_id = HOST_ID_MCU_0_R5_0,
799 },
800 /* DMASS Packet DMA SA2UL Tx channel0 */
801 {
802 .start_resource = 27,
803 .num_resource = 1,
804 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
805 RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN),
806 .host_id = HOST_ID_A53_2,
807 },
808 /* DMASS Packet DMA SA2UL Tx channel1 */
809 {
810 .start_resource = 28,
811 .num_resource = 1,
812 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
813 RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
814 .host_id = HOST_ID_A53_2,
815 },
816 /* DMASS Packet DMA Free Rx channel */
817 {
818 .start_resource = 0,
819 .num_resource = 10,
820 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
821 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
822 .host_id = HOST_ID_A53_2,
823 },
824 {
825 .start_resource = 10,
826 .num_resource = 3,
827 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
828 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
829 .host_id = HOST_ID_MAIN_0_R5_0,
830 },
831 {
832 .start_resource = 10,
833 .num_resource = 3,
834 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
835 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
836 .host_id = HOST_ID_MAIN_0_R5_1,
837 },
838 {
839 .start_resource = 13,
840 .num_resource = 3,
841 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
842 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
843 .host_id = HOST_ID_MCU_0_R5_0,
844 },
845 {
846 .start_resource = 16,
847 .num_resource = 3,
848 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
849 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
850 .host_id = HOST_ID_ALL,
851 },
852 /* DMASS Packet DMA Free flows for Rx channel */
853 {
854 .start_resource = 0,
855 .num_resource = 10,
856 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
857 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
858 .host_id = HOST_ID_A53_2,
859 },
860 {
861 .start_resource = 10,
862 .num_resource = 3,
863 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
864 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
865 .host_id = HOST_ID_MAIN_0_R5_0,
866 },
867 {
868 .start_resource = 10,
869 .num_resource = 3,
870 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
871 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
872 .host_id = HOST_ID_MAIN_0_R5_1,
873 },
874 {
875 .start_resource = 13,
876 .num_resource = 3,
877 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
878 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
879 .host_id = HOST_ID_MCU_0_R5_0,
880 },
881 {
882 .start_resource = 16,
883 .num_resource = 3,
884 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
885 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
886 .host_id = HOST_ID_ALL,
887 },
888 /* DMASS Packet DMA CPSW Rx channel */
889 {
890 .start_resource = 19,
891 .num_resource = 1,
892 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
893 RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
894 .host_id = HOST_ID_A53_2,
895 },
896 {
897 .start_resource = 19,
898 .num_resource = 1,
899 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
900 RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
901 .host_id = HOST_ID_MCU_0_R5_0,
902 },
903 /* DMASS Packet DMA CPSW Rx flows */
904 {
905 .start_resource = 19,
906 .num_resource = 16,
907 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
908 RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
909 .host_id = HOST_ID_A53_2,
910 },
911 {
912 .start_resource = 19,
913 .num_resource = 16,
914 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
915 RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
916 .host_id = HOST_ID_MCU_0_R5_0,
917 },
918 /* DMASS Packet DMA SA2UL Rx channel0 */
919 {
920 .start_resource = 20,
921 .num_resource = 1,
922 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
923 RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN),
924 .host_id = HOST_ID_A53_2,
925 },
926 /* DMASS Packet DMA SA2UL Rx channel0 flows */
927 {
928 .start_resource = 35,
929 .num_resource = 8,
930 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
931 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
932 .host_id = HOST_ID_A53_2,
933 },
934 /* DMASS Packet DMA SA2UL Rx channel1 */
935 {
936 .start_resource = 21,
937 .num_resource = 1,
938 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
939 RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN),
940 .host_id = HOST_ID_A53_2,
941 },
942 /* DMASS Packet DMA SA2UL Rx channel1 flows */
943 {
944 .start_resource = 35,
945 .num_resource = 8,
946 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
947 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
948 .host_id = HOST_ID_A53_2,
949 },
950 /* DMASS Packet DMA SA2UL Rx channel2 */
951 {
952 .start_resource = 22,
953 .num_resource = 1,
954 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
955 RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
956 .host_id = HOST_ID_A53_2,
957 },
958 /* DMASS Packet DMA SA2UL Rx channel2 flows */
959 {
960 .start_resource = 43,
961 .num_resource = 8,
962 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
963 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
964 .host_id = HOST_ID_A53_2,
965 },
966 /* DMASS Packet DMA SA2UL Rx channel3 */
967 {
968 .start_resource = 23,
969 .num_resource = 1,
970 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
971 RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
972 .host_id = HOST_ID_A53_2,
973 },
974 /* DMASS Packet DMA SA2UL Rx channel3 flows */
975 {
976 .start_resource = 43,
977 .num_resource = 8,
978 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
979 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
980 .host_id = HOST_ID_A53_2,
981 },
982 /* DMASS Packet DMA Ring accelerator error event */
983 {
984 .start_resource = 0,
985 .num_resource = 1,
986 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_RINGACC_0,
987 RESASG_SUBTYPE_RA_ERROR_OES),
988 .host_id = HOST_ID_ALL,
989 },
990 /* DMASS Packet DMA virt_id range */
991 {
992 .start_resource = 2,
993 .num_resource = 2,
994 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_RINGACC_0,
995 RESASG_SUBTYPE_RA_VIRTID),
996 .host_id = HOST_ID_A53_2,
997 },
998 /* Block Copy DMA DMASS1 Global event trigger */
999 {
1000 .start_resource = 51200,
1001 .num_resource = 12,
1002 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1003 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
1004 .host_id = HOST_ID_ALL,
1005 },
1006 /* Block Copy DMA DMASS1 Global config */
1007 {
1008 .start_resource = 0,
1009 .num_resource = 1,
1010 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1011 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
1012 .host_id = HOST_ID_ALL,
1013 },
1014 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */
1015 {
1016 .start_resource = 0,
1017 .num_resource = 4,
1018 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1019 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
1020 .host_id = HOST_ID_A53_2,
1021 },
1022 {
1023 .start_resource = 4,
1024 .num_resource = 2,
1025 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1026 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
1027 .host_id = HOST_ID_ALL,
1028 },
1029 /* Block Copy DMA DMASS1 Split TR Rx channel */
1030 {
1031 .start_resource = 0,
1032 .num_resource = 4,
1033 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1034 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
1035 .host_id = HOST_ID_A53_2,
1036 },
1037 {
1038 .start_resource = 4,
1039 .num_resource = 2,
1040 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
1041 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
1042 .host_id = HOST_ID_ALL,
1043 },
1044 /* DMASS1 Interrupt aggregator Virtual interrupts */
1045 {
1046 .start_resource = 0,
1047 .num_resource = 8,
1048 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
1049 RESASG_SUBTYPE_IA_VINT),
1050 .host_id = HOST_ID_A53_2,
1051 },
1052 /* DMASS1 Interrupt aggregator Global events */
1053 {
1054 .start_resource = 12288,
1055 .num_resource = 128,
1056 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
1057 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1058 .host_id = HOST_ID_A53_2,
1059 },
1060 /* Block copy DMA DMASS1 Rx channel error event */
1061 {
1062 .start_resource = 3072,
1063 .num_resource = 6,
1064 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
1065 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
1066 .host_id = HOST_ID_ALL,
1067 },
1068 /* Block copy DMA DMASS1 Rx channel data completion event */
1069 {
1070 .start_resource = 3584,
1071 .num_resource = 6,
1072 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
1073 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
1074 .host_id = HOST_ID_ALL,
1075 },
1076 /* Block copy DMA DMASS1 Rx channel ring completion event */
1077 {
1078 .start_resource = 4096,
1079 .num_resource = 6,
1080 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
1081 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
1082 .host_id = HOST_ID_ALL,
1083 },
1084 },
1085};
diff --git a/soc/am62ax/evm/sec-cfg.c b/soc/am62ax/evm/sec-cfg.c
new file mode 100644
index 000000000..ea965d10f
--- /dev/null
+++ b/soc/am62ax/evm/sec-cfg.c
@@ -0,0 +1,121 @@
1/*
2 * K3 System Firmware Security Configuration Data
3 *
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "common.h"
36
37
38#define SYSFW_TEST_HOST_ID HOST_ID_MAIN_0_R5_0
39#define OTHER_HOST_ID HOST_ID_A53_0
40
41const struct boardcfg_security am62_boardcfg_security_data = {
42 /* boardcfg_abi_rev */
43 .rev = {
44 .boardcfg_abi_maj = 0x0,
45 .boardcfg_abi_min = 0x1,
46 },
47
48 /* boardcfg_proc_acl */
49 .processor_acl_list = {
50 .subhdr = {
51 .magic = BOARDCFG_PROC_ACL_MAGIC_NUM,
52 .size = sizeof(struct boardcfg_proc_acl),
53 },
54 .proc_acl_entries = {{ 0 }},
55 },
56
57 /* boardcfg_host_hierarchy */
58 .host_hierarchy = {
59 .subhdr = {
60 .magic = BOARDCFG_HOST_HIERARCHY_MAGIC_NUM,
61 .size = sizeof(struct boardcfg_host_hierarchy),
62 },
63 .host_hierarchy_entries = {{ 0 }},
64 },
65
66 /* OTP access configuration */
67 .otp_config = {
68 .subhdr = {
69 .magic = BOARDCFG_OTP_CFG_MAGIC_NUM,
70 .size = sizeof(struct boardcfg_extended_otp),
71 },
72 /* Host ID 0 is DMSC. This means no host has write access to OTP array */
73 .write_host_id = 0,
74 /* This is an array with 32 entries */
75 .otp_entry = {{ 0 } },
76 },
77
78 /* DKEK configuration */
79 .dkek_config = {
80 .subhdr = {
81 .magic = BOARDCFG_DKEK_CFG_MAGIC_NUM,
82 .size = sizeof(struct boardcfg_dkek),
83 },
84 .allowed_hosts = { HOST_ID_ALL, 0, 0, 0 },
85 .allow_dkek_export_tisci = 0x5A,
86 .rsvd = {0, 0, 0},
87 },
88
89 /* SA2UL configuration */
90 .sa2ul_cfg = {
91 .subhdr = {
92 .magic = BOARDCFG_SA2UL_CFG_MAGIC_NUM_RSVD,
93 .size = 0,
94 },
95 .auth_resource_owner = 0,
96 .enable_saul_psil_global_config_writes = 0x5A,
97 .rsvd = {0, 0},
98 },
99
100 /* Secure JTAG Unlock Configuration */
101 .sec_dbg_config = {
102 .subhdr = {
103 .magic = BOARDCFG_SEC_DBG_CTRL_MAGIC_NUM,
104 .size = sizeof(struct boardcfg_secure_debug_config),
105 },
106 .allow_jtag_unlock = 0x5A,
107 .allow_wildcard_unlock = 0x5A,
108 .min_cert_rev = 0x0,
109 .jtag_unlock_hosts = {0, 0, 0, 0},
110 },
111
112 .sec_handover_cfg = {
113 .subhdr = {
114 .magic = BOARDCFG_SEC_HANDOVER_CFG_MAGIC_NUM,
115 .size = sizeof(struct boardcfg_sec_handover),
116 },
117 .handover_msg_sender = 0,
118 .handover_to_host_id = 0,
119 .rsvd = {0,0,0,0},
120 },
121};
diff --git a/soc/am62ax/evm/sysfw_img_cfg.h b/soc/am62ax/evm/sysfw_img_cfg.h
new file mode 100644
index 000000000..bd1c7d7e0
--- /dev/null
+++ b/soc/am62ax/evm/sysfw_img_cfg.h
@@ -0,0 +1,43 @@
1/*
2 * K3 System Firmware Resource Management Board Config Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 *
6 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H
39
40#define BOARDCFG_RM_RESASG_ENTRIES 131
41#define BOARDCFG_TIFS_RM_RESASG_ENTRIES 111
42
43#endif /* SYSFW_IMG_CFG_H */
diff --git a/soc/am62ax/evm/tifs-rm-cfg.c b/soc/am62ax/evm/tifs-rm-cfg.c
new file mode 100644
index 000000000..d50f11080
--- /dev/null
+++ b/soc/am62ax/evm/tifs-rm-cfg.c
@@ -0,0 +1,956 @@
1/*
2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 *
14 * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the
17 * distribution.
18 *
19 * Neither the name of Texas Instruments Incorporated nor the names of
20 * its contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include "common.h"
37#include <hosts.h>
38#include <devices.h>
39#include <resasg_types.h>
40
41const struct boardcfg_tifs_rm_local am62a_boardcfg_rm_data = {
42 .rm_boardcfg = {
43 /* boardcfg_abi_rev */
44 .rev = {
45 .boardcfg_abi_maj = 0x0,
46 .boardcfg_abi_min = 0x1,
47 },
48
49 /* boardcfg_rm_host_cfg */
50 .host_cfg = {
51 .subhdr = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 },
55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_A53_2,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_MCU_0_R5_0,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_MAIN_0_R5_1,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 }
81 },
82
83 /* boardcfg_rm_resasg */
84 .resasg = {
85 .subhdr = {
86 .magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
87 .size = sizeof (struct boardcfg_rm_resasg),
88 },
89 .resasg_entries_size =
90 BOARDCFG_TIFS_RM_RESASG_ENTRIES *
91 sizeof (struct boardcfg_rm_resasg_entry),
92 .reserved = 0,
93 /* .resasg_entries is set via boardcfg_rm_local */
94 },
95 },
96
97 /* This is actually part of .resasg */
98 .resasg_entries = {
99 /* Compare event Interrupt Router */
100 /* Not Applicable for TIFS */
101 /* MAIN GPIO Interrupt Router */
102 /* Not Applicable for TIFS */
103 /* WKUP MCU GPIO Interrupt Router */
104 /* Not Applicable for TIFS */
105 /* Timesync Interrupt Router */
106 /* Not Applicable for TIFS */
107 /* Block Copy DMA Global event trigger */
108 /* Not Applicable for TIFS */
109 /* Block Copy DMA Global config */
110 /* Not Applicable for TIFS */
111 /* Block Copy DMA Rings for Block copy channel */
112 {
113 .start_resource = 0,
114 .num_resource = 18,
115 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
116 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
117 .host_id = HOST_ID_A53_2,
118 },
119 {
120 .start_resource = 18,
121 .num_resource = 6,
122 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
123 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
124 .host_id = HOST_ID_MAIN_0_R5_0,
125 },
126 {
127 .start_resource = 18,
128 .num_resource = 6,
129 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
130 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
131 .host_id = HOST_ID_MAIN_0_R5_1,
132 },
133 {
134 .start_resource = 24,
135 .num_resource = 2,
136 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
137 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
138 .host_id = HOST_ID_MCU_0_R5_0,
139 },
140 {
141 .start_resource = 26,
142 .num_resource = 6,
143 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
144 RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
145 .host_id = HOST_ID_ALL,
146 },
147 /* Block Copy DMA Rings for Split TR Rx channel */
148 {
149 .start_resource = 54,
150 .num_resource = 18,
151 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
152 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
153 .host_id = HOST_ID_A53_2,
154 },
155 {
156 .start_resource = 72,
157 .num_resource = 6,
158 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
159 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
160 .host_id = HOST_ID_MAIN_0_R5_0,
161 },
162 {
163 .start_resource = 72,
164 .num_resource = 6,
165 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
166 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
167 .host_id = HOST_ID_MAIN_0_R5_1,
168 },
169 {
170 .start_resource = 78,
171 .num_resource = 2,
172 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
173 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
174 .host_id = HOST_ID_MCU_0_R5_0,
175 },
176 {
177 .start_resource = 80,
178 .num_resource = 2,
179 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
180 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
181 .host_id = HOST_ID_ALL,
182 },
183 /* Block Copy DMA Rings for Split TR Tx channel */
184 {
185 .start_resource = 32,
186 .num_resource = 12,
187 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
188 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
189 .host_id = HOST_ID_A53_2,
190 },
191 {
192 .start_resource = 44,
193 .num_resource = 6,
194 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
195 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
196 .host_id = HOST_ID_MAIN_0_R5_0,
197 },
198 {
199 .start_resource = 44,
200 .num_resource = 6,
201 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
202 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
203 .host_id = HOST_ID_MAIN_0_R5_1,
204 },
205 {
206 .start_resource = 50,
207 .num_resource = 2,
208 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
209 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
210 .host_id = HOST_ID_MCU_0_R5_0,
211 },
212 {
213 .start_resource = 52,
214 .num_resource = 2,
215 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
216 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
217 .host_id = HOST_ID_ALL,
218 },
219 /* Block Copy DMA Block copy channel */
220 {
221 .start_resource = 0,
222 .num_resource = 18,
223 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
224 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
225 .host_id = HOST_ID_A53_2,
226 },
227 {
228 .start_resource = 18,
229 .num_resource = 6,
230 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
231 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
232 .host_id = HOST_ID_MAIN_0_R5_0,
233 },
234 {
235 .start_resource = 18,
236 .num_resource = 6,
237 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
238 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
239 .host_id = HOST_ID_MAIN_0_R5_1,
240 },
241 {
242 .start_resource = 24,
243 .num_resource = 2,
244 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
245 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
246 .host_id = HOST_ID_MCU_0_R5_0,
247 },
248 {
249 .start_resource = 26,
250 .num_resource = 6,
251 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
252 RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
253 .host_id = HOST_ID_ALL,
254 },
255 /* Block Copy DMA Split TR Rx channel */
256 {
257 .start_resource = 0,
258 .num_resource = 18,
259 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
260 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
261 .host_id = HOST_ID_A53_2,
262 },
263 {
264 .start_resource = 18,
265 .num_resource = 6,
266 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
267 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
268 .host_id = HOST_ID_MAIN_0_R5_0,
269 },
270 {
271 .start_resource = 18,
272 .num_resource = 6,
273 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
274 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
275 .host_id = HOST_ID_MAIN_0_R5_1,
276 },
277 {
278 .start_resource = 24,
279 .num_resource = 2,
280 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
281 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
282 .host_id = HOST_ID_MCU_0_R5_0,
283 },
284 {
285 .start_resource = 26,
286 .num_resource = 2,
287 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
288 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
289 .host_id = HOST_ID_ALL,
290 },
291 /* Block Copy DMA Split TR Tx channel */
292 {
293 .start_resource = 0,
294 .num_resource = 12,
295 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
296 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
297 .host_id = HOST_ID_A53_2,
298 },
299 {
300 .start_resource = 12,
301 .num_resource = 6,
302 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
303 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
304 .host_id = HOST_ID_MAIN_0_R5_0,
305 },
306 {
307 .start_resource = 12,
308 .num_resource = 6,
309 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
310 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
311 .host_id = HOST_ID_MAIN_0_R5_1,
312 },
313 {
314 .start_resource = 18,
315 .num_resource = 2,
316 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
317 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
318 .host_id = HOST_ID_MCU_0_R5_0,
319 },
320 {
321 .start_resource = 20,
322 .num_resource = 2,
323 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_BCDMA_0,
324 RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
325 .host_id = HOST_ID_ALL,
326 },
327 /* DMASS Interrupt aggregator Virtual interrupts */
328 {
329 .start_resource = 6,
330 .num_resource = 34,
331 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
332 RESASG_SUBTYPE_IA_VINT),
333 .host_id = HOST_ID_A53_2,
334 },
335 {
336 .start_resource = 44,
337 .num_resource = 36,
338 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
339 RESASG_SUBTYPE_IA_VINT),
340 .host_id = HOST_ID_MAIN_0_R5_0,
341 },
342 {
343 .start_resource = 44,
344 .num_resource = 36,
345 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
346 RESASG_SUBTYPE_IA_VINT),
347 .host_id = HOST_ID_MAIN_0_R5_1,
348 },
349 {
350 .start_resource = 168,
351 .num_resource = 8,
352 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
353 RESASG_SUBTYPE_IA_VINT),
354 .host_id = HOST_ID_MCU_0_R5_0,
355 },
356 /* DMASS Interrupt aggregator Global events */
357 /* Not Applicable for TIFS */
358 /* DMASS timer manager event */
359 {
360 .start_resource = 0,
361 .num_resource = 1024,
362 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
363 RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
364 .host_id = HOST_ID_ALL,
365 },
366 /* DMASS Packet DMA Tx channel error event */
367 {
368 .start_resource = 4096,
369 .num_resource = 29,
370 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
371 RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
372 .host_id = HOST_ID_ALL,
373 },
374 /* DMASS Packet DMA Tx flow completion event */
375 {
376 .start_resource = 4608,
377 .num_resource = 99,
378 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
379 RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
380 .host_id = HOST_ID_ALL,
381 },
382 /* DMASS Packet DMA Rx channel error event */
383 {
384 .start_resource = 5120,
385 .num_resource = 24,
386 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
387 RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
388 .host_id = HOST_ID_ALL,
389 },
390 /* DMASS Packet DMA Rx flow completion event */
391 {
392 .start_resource = 5632,
393 .num_resource = 51,
394 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
395 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
396 .host_id = HOST_ID_ALL,
397 },
398 /* DMASS Packet DMA Rx flow starvation event */
399 {
400 .start_resource = 6144,
401 .num_resource = 51,
402 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
403 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
404 .host_id = HOST_ID_ALL,
405 },
406 /* DMASS Packet DMA Rx flow firewall event */
407 {
408 .start_resource = 6656,
409 .num_resource = 51,
410 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
411 RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
412 .host_id = HOST_ID_ALL,
413 },
414 /* Block copy DMA BC channel error event */
415 {
416 .start_resource = 8192,
417 .num_resource = 32,
418 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
419 RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
420 .host_id = HOST_ID_ALL,
421 },
422 /* Block copy DMA BC channel data completion event */
423 {
424 .start_resource = 8704,
425 .num_resource = 32,
426 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
427 RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
428 .host_id = HOST_ID_ALL,
429 },
430 /* Block copy DMA BC channel ring completion event */
431 {
432 .start_resource = 9216,
433 .num_resource = 32,
434 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
435 RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
436 .host_id = HOST_ID_ALL,
437 },
438 /* Block copy DMA Tx channel error event */
439 {
440 .start_resource = 9728,
441 .num_resource = 22,
442 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
443 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
444 .host_id = HOST_ID_ALL,
445 },
446 /* Block copy DMA Tx channel data completion event */
447 {
448 .start_resource = 10240,
449 .num_resource = 22,
450 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
451 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
452 .host_id = HOST_ID_ALL,
453 },
454 /* Block copy DMA Tx channel ring completion event */
455 {
456 .start_resource = 10752,
457 .num_resource = 22,
458 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
459 RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
460 .host_id = HOST_ID_ALL,
461 },
462 /* Block copy DMA Rx channel error event */
463 {
464 .start_resource = 11264,
465 .num_resource = 28,
466 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
467 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
468 .host_id = HOST_ID_ALL,
469 },
470 /* Block copy DMA Rx channel data completion event */
471 {
472 .start_resource = 11776,
473 .num_resource = 28,
474 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
475 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
476 .host_id = HOST_ID_ALL,
477 },
478 /* Block copy DMA Rx channel ring completion event */
479 {
480 .start_resource = 12288,
481 .num_resource = 28,
482 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_INTAGGR_0,
483 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
484 .host_id = HOST_ID_ALL,
485 },
486 /* DMASS DMASS UDMA global config */
487 /* Not Applicable for TIFS */
488 /* DMASS Packet DMA Free rings for Tx channel */
489 {
490 .start_resource = 0,
491 .num_resource = 10,
492 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
493 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
494 .host_id = HOST_ID_A53_2,
495 },
496 {
497 .start_resource = 10,
498 .num_resource = 3,
499 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
500 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
501 .host_id = HOST_ID_MAIN_0_R5_0,
502 },
503 {
504 .start_resource = 10,
505 .num_resource = 3,
506 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
507 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
508 .host_id = HOST_ID_MAIN_0_R5_1,
509 },
510 {
511 .start_resource = 13,
512 .num_resource = 3,
513 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
514 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
515 .host_id = HOST_ID_MCU_0_R5_0,
516 },
517 {
518 .start_resource = 16,
519 .num_resource = 3,
520 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
521 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
522 .host_id = HOST_ID_ALL,
523 },
524 /* DMASS Packet DMA Rings for CPSW Tx channel */
525 {
526 .start_resource = 19,
527 .num_resource = 64,
528 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
529 RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
530 .host_id = HOST_ID_A53_2,
531 },
532 {
533 .start_resource = 19,
534 .num_resource = 64,
535 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
536 RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
537 .host_id = HOST_ID_MCU_0_R5_0,
538 },
539 /* DMASS Packet DMA Rings for SA2UL Tx channel0 */
540 {
541 .start_resource = 83,
542 .num_resource = 8,
543 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
544 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
545 .host_id = HOST_ID_A53_2,
546 },
547 /* DMASS Packet DMA Rings for SA2UL Tx channel1 */
548 {
549 .start_resource = 91,
550 .num_resource = 8,
551 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
552 RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
553 .host_id = HOST_ID_A53_2,
554 },
555 /* DMASS Packet DMA Free rings for Rx channel */
556 {
557 .start_resource = 99,
558 .num_resource = 10,
559 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
560 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
561 .host_id = HOST_ID_A53_2,
562 },
563 {
564 .start_resource = 109,
565 .num_resource = 3,
566 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
567 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
568 .host_id = HOST_ID_MAIN_0_R5_0,
569 },
570 {
571 .start_resource = 109,
572 .num_resource = 3,
573 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
574 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
575 .host_id = HOST_ID_MAIN_0_R5_1,
576 },
577 {
578 .start_resource = 112,
579 .num_resource = 3,
580 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
581 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
582 .host_id = HOST_ID_MCU_0_R5_0,
583 },
584 {
585 .start_resource = 115,
586 .num_resource = 3,
587 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
588 RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
589 .host_id = HOST_ID_ALL,
590 },
591 /* DMASS Packet DMA Rings for CPSW Rx channel */
592 {
593 .start_resource = 118,
594 .num_resource = 16,
595 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
596 RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
597 .host_id = HOST_ID_A53_2,
598 },
599 {
600 .start_resource = 118,
601 .num_resource = 16,
602 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
603 RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
604 .host_id = HOST_ID_MCU_0_R5_0,
605 },
606 /* DMASS Packet DMA Rings for SA2UL Rx channel0 */
607 {
608 .start_resource = 134,
609 .num_resource = 8,
610 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
611 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
612 .host_id = HOST_ID_A53_2,
613 },
614 /* DMASS Packet DMA Rings for SA2UL Rx channel1 */
615 {
616 .start_resource = 134,
617 .num_resource = 8,
618 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
619 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
620 .host_id = HOST_ID_A53_2,
621 },
622 /* DMASS Packet DMA Rings for SA2UL Rx channel2 */
623 {
624 .start_resource = 142,
625 .num_resource = 8,
626 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
627 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
628 .host_id = HOST_ID_A53_2,
629 },
630 /* DMASS Packet DMA Rings for SA2UL Rx channel3 */
631 {
632 .start_resource = 142,
633 .num_resource = 8,
634 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
635 RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
636 .host_id = HOST_ID_A53_2,
637 },
638 /* DMASS Packet DMA Free Tx channel */
639 {
640 .start_resource = 0,
641 .num_resource = 10,
642 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
643 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
644 .host_id = HOST_ID_A53_2,
645 },
646 {
647 .start_resource = 10,
648 .num_resource = 3,
649 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
650 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
651 .host_id = HOST_ID_MAIN_0_R5_0,
652 },
653 {
654 .start_resource = 10,
655 .num_resource = 3,
656 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
657 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
658 .host_id = HOST_ID_MAIN_0_R5_1,
659 },
660 {
661 .start_resource = 13,
662 .num_resource = 3,
663 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
664 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
665 .host_id = HOST_ID_MCU_0_R5_0,
666 },
667 {
668 .start_resource = 16,
669 .num_resource = 3,
670 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
671 RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
672 .host_id = HOST_ID_ALL,
673 },
674 /* DMASS Packet DMA CPSW Tx channel */
675 {
676 .start_resource = 19,
677 .num_resource = 8,
678 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
679 RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
680 .host_id = HOST_ID_A53_2,
681 },
682 {
683 .start_resource = 19,
684 .num_resource = 8,
685 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
686 RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
687 .host_id = HOST_ID_MCU_0_R5_0,
688 },
689 /* DMASS Packet DMA SA2UL Tx channel0 */
690 {
691 .start_resource = 27,
692 .num_resource = 1,
693 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
694 RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN),
695 .host_id = HOST_ID_A53_2,
696 },
697 /* DMASS Packet DMA SA2UL Tx channel1 */
698 {
699 .start_resource = 28,
700 .num_resource = 1,
701 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
702 RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
703 .host_id = HOST_ID_A53_2,
704 },
705 /* DMASS Packet DMA Free Rx channel */
706 {
707 .start_resource = 0,
708 .num_resource = 10,
709 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
710 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
711 .host_id = HOST_ID_A53_2,
712 },
713 {
714 .start_resource = 10,
715 .num_resource = 3,
716 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
717 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
718 .host_id = HOST_ID_MAIN_0_R5_0,
719 },
720 {
721 .start_resource = 10,
722 .num_resource = 3,
723 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
724 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
725 .host_id = HOST_ID_MAIN_0_R5_1,
726 },
727 {
728 .start_resource = 13,
729 .num_resource = 3,
730 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
731 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
732 .host_id = HOST_ID_MCU_0_R5_0,
733 },
734 {
735 .start_resource = 16,
736 .num_resource = 3,
737 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
738 RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
739 .host_id = HOST_ID_ALL,
740 },
741 /* DMASS Packet DMA Free flows for Rx channel */
742 {
743 .start_resource = 0,
744 .num_resource = 10,
745 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
746 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
747 .host_id = HOST_ID_A53_2,
748 },
749 {
750 .start_resource = 10,
751 .num_resource = 3,
752 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
753 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
754 .host_id = HOST_ID_MAIN_0_R5_0,
755 },
756 {
757 .start_resource = 10,
758 .num_resource = 3,
759 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
760 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
761 .host_id = HOST_ID_MAIN_0_R5_1,
762 },
763 {
764 .start_resource = 13,
765 .num_resource = 3,
766 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
767 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
768 .host_id = HOST_ID_MCU_0_R5_0,
769 },
770 {
771 .start_resource = 16,
772 .num_resource = 3,
773 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
774 RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
775 .host_id = HOST_ID_ALL,
776 },
777 /* DMASS Packet DMA CPSW Rx channel */
778 {
779 .start_resource = 19,
780 .num_resource = 1,
781 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
782 RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
783 .host_id = HOST_ID_A53_2,
784 },
785 {
786 .start_resource = 19,
787 .num_resource = 1,
788 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
789 RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
790 .host_id = HOST_ID_MCU_0_R5_0,
791 },
792 /* DMASS Packet DMA CPSW Rx flows */
793 {
794 .start_resource = 19,
795 .num_resource = 16,
796 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
797 RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
798 .host_id = HOST_ID_A53_2,
799 },
800 {
801 .start_resource = 19,
802 .num_resource = 16,
803 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
804 RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
805 .host_id = HOST_ID_MCU_0_R5_0,
806 },
807 /* DMASS Packet DMA SA2UL Rx channel0 */
808 {
809 .start_resource = 20,
810 .num_resource = 1,
811 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
812 RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN),
813 .host_id = HOST_ID_A53_2,
814 },
815 /* DMASS Packet DMA SA2UL Rx channel0 flows */
816 {
817 .start_resource = 35,
818 .num_resource = 8,
819 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
820 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
821 .host_id = HOST_ID_A53_2,
822 },
823 /* DMASS Packet DMA SA2UL Rx channel1 */
824 {
825 .start_resource = 21,
826 .num_resource = 1,
827 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
828 RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN),
829 .host_id = HOST_ID_A53_2,
830 },
831 /* DMASS Packet DMA SA2UL Rx channel1 flows */
832 {
833 .start_resource = 35,
834 .num_resource = 8,
835 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
836 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
837 .host_id = HOST_ID_A53_2,
838 },
839 /* DMASS Packet DMA SA2UL Rx channel2 */
840 {
841 .start_resource = 22,
842 .num_resource = 1,
843 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
844 RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
845 .host_id = HOST_ID_A53_2,
846 },
847 /* DMASS Packet DMA SA2UL Rx channel2 flows */
848 {
849 .start_resource = 43,
850 .num_resource = 8,
851 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
852 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
853 .host_id = HOST_ID_A53_2,
854 },
855 /* DMASS Packet DMA SA2UL Rx channel3 */
856 {
857 .start_resource = 23,
858 .num_resource = 1,
859 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
860 RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
861 .host_id = HOST_ID_A53_2,
862 },
863 /* DMASS Packet DMA SA2UL Rx channel3 flows */
864 {
865 .start_resource = 43,
866 .num_resource = 8,
867 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_PKTDMA_0,
868 RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
869 .host_id = HOST_ID_A53_2,
870 },
871 /* DMASS Packet DMA Ring accelerator error event */
872 {
873 .start_resource = 0,
874 .num_resource = 1,
875 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_RINGACC_0,
876 RESASG_SUBTYPE_RA_ERROR_OES),
877 .host_id = HOST_ID_ALL,
878 },
879 /* DMASS Packet DMA virt_id range */
880 {
881 .start_resource = 2,
882 .num_resource = 2,
883 .type = RESASG_UTYPE (AM62A_DEV_DMASS0_RINGACC_0,
884 RESASG_SUBTYPE_RA_VIRTID),
885 .host_id = HOST_ID_A53_2,
886 },
887 /* Block Copy DMA DMASS1 Global event trigger */
888 /* Not Applicable for TIFS */
889 /* Block Copy DMA DMASS1 Global config */
890 /* Not Applicable for TIFS */
891 /* Block Copy DMA Rings DMASS1 for Split TR Rx channel */
892 {
893 .start_resource = 0,
894 .num_resource = 4,
895 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
896 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
897 .host_id = HOST_ID_A53_2,
898 },
899 {
900 .start_resource = 4,
901 .num_resource = 2,
902 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
903 RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
904 .host_id = HOST_ID_ALL,
905 },
906 /* Block Copy DMA DMASS1 Split TR Rx channel */
907 {
908 .start_resource = 0,
909 .num_resource = 4,
910 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
911 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
912 .host_id = HOST_ID_A53_2,
913 },
914 {
915 .start_resource = 4,
916 .num_resource = 2,
917 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_BCDMA_0,
918 RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
919 .host_id = HOST_ID_ALL,
920 },
921 /* DMASS1 Interrupt aggregator Virtual interrupts */
922 {
923 .start_resource = 0,
924 .num_resource = 8,
925 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
926 RESASG_SUBTYPE_IA_VINT),
927 .host_id = HOST_ID_A53_2,
928 },
929 /* DMASS1 Interrupt aggregator Global events */
930 /* Not Applicable for TIFS */
931 /* Block copy DMA DMASS1 Rx channel error event */
932 {
933 .start_resource = 3072,
934 .num_resource = 6,
935 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
936 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
937 .host_id = HOST_ID_ALL,
938 },
939 /* Block copy DMA DMASS1 Rx channel data completion event */
940 {
941 .start_resource = 3584,
942 .num_resource = 6,
943 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
944 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
945 .host_id = HOST_ID_ALL,
946 },
947 /* Block copy DMA DMASS1 Rx channel ring completion event */
948 {
949 .start_resource = 4096,
950 .num_resource = 6,
951 .type = RESASG_UTYPE (AM62A_DEV_DMASS1_INTAGGR_0,
952 RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
953 .host_id = HOST_ID_ALL,
954 },
955 },
956};