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-rw-r--r--soc/j721e/evm/rm-cfg.c38
-rw-r--r--soc/j721e/evm/sysfw_img_cfg.h4
2 files changed, 35 insertions, 7 deletions
diff --git a/soc/j721e/evm/rm-cfg.c b/soc/j721e/evm/rm-cfg.c
index 2a96ee2e7..3330a7dd3 100644
--- a/soc/j721e/evm/rm-cfg.c
+++ b/soc/j721e/evm/rm-cfg.c
@@ -2,7 +2,7 @@
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -982,19 +982,33 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
982 }, 982 },
983 { 983 {
984 .start_resource = 168, 984 .start_resource = 168,
985 .num_resource = 4, 985 .num_resource = 2,
986 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 986 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
987 RESASG_SUBTYPE_RA_UDMAP_TX_EXT), 987 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
988 .host_id = HOST_ID_MAIN_0_R5_0, 988 .host_id = HOST_ID_MAIN_0_R5_0,
989 }, 989 },
990 {
991 .start_resource = 170,
992 .num_resource = 2,
993 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
994 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
995 .host_id = HOST_ID_MAIN_0_R5_2,
996 },
990 /* Main NAVSS Rings for extended Tx channels for HWA */ 997 /* Main NAVSS Rings for extended Tx channels for HWA */
991 { 998 {
992 .start_resource = 172, 999 .start_resource = 172,
993 .num_resource = 128, 1000 .num_resource = 96,
994 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 1001 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
995 RESASG_SUBTYPE_RA_UDMAP_TX_EXT), 1002 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
996 .host_id = HOST_ID_MAIN_0_R5_0, 1003 .host_id = HOST_ID_MAIN_0_R5_0,
997 }, 1004 },
1005 {
1006 .start_resource = 268,
1007 .num_resource = 32,
1008 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1009 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
1010 .host_id = HOST_ID_MAIN_0_R5_2,
1011 },
998 /* Main NAVSS Rings for High capacity Rx channels */ 1012 /* Main NAVSS Rings for High capacity Rx channels */
999 { 1013 {
1000 .start_resource = 304, 1014 .start_resource = 304,
@@ -1439,11 +1453,18 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1439 /* Main NAVSS UDMA extended Tx channels for HWA */ 1453 /* Main NAVSS UDMA extended Tx channels for HWA */
1440 { 1454 {
1441 .start_resource = 172, 1455 .start_resource = 172,
1442 .num_resource = 128, 1456 .num_resource = 96,
1443 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0, 1457 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1444 RESASG_SUBTYPE_UDMAP_TX_ECHAN), 1458 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1445 .host_id = HOST_ID_MAIN_0_R5_0, 1459 .host_id = HOST_ID_MAIN_0_R5_0,
1446 }, 1460 },
1461 {
1462 .start_resource = 268,
1463 .num_resource = 32,
1464 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1465 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1466 .host_id = HOST_ID_MAIN_0_R5_2,
1467 },
1447 /* Main NAVSS UDMA extended Tx channels for DRU */ 1468 /* Main NAVSS UDMA extended Tx channels for DRU */
1448 { 1469 {
1449 .start_resource = 140, 1470 .start_resource = 140,
@@ -1468,11 +1489,18 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1468 }, 1489 },
1469 { 1490 {
1470 .start_resource = 168, 1491 .start_resource = 168,
1471 .num_resource = 4, 1492 .num_resource = 2,
1472 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0, 1493 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1473 RESASG_SUBTYPE_UDMAP_TX_ECHAN), 1494 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1474 .host_id = HOST_ID_MAIN_0_R5_0, 1495 .host_id = HOST_ID_MAIN_0_R5_0,
1475 }, 1496 },
1497 {
1498 .start_resource = 170,
1499 .num_resource = 2,
1500 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1501 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1502 .host_id = HOST_ID_MAIN_0_R5_2,
1503 },
1476 /* Main NAVSS UDMA High capacity Tx channels */ 1504 /* Main NAVSS UDMA High capacity Tx channels */
1477 { 1505 {
1478 .start_resource = 4, 1506 .start_resource = 4,
diff --git a/soc/j721e/evm/sysfw_img_cfg.h b/soc/j721e/evm/sysfw_img_cfg.h
index bfd4e53e7..bfcab2d1a 100644
--- a/soc/j721e/evm/sysfw_img_cfg.h
+++ b/soc/j721e/evm/sysfw_img_cfg.h
@@ -3,7 +3,7 @@
3 * Auto generated from K3 Resource Partitioning tool 3 * Auto generated from K3 Resource Partitioning tool
4 * 4 *
5 * 5 *
6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
@@ -37,6 +37,6 @@
37#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
38#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
39 39
40#define BOARDCFG_RM_RESASG_ENTRIES 342 40#define BOARDCFG_RM_RESASG_ENTRIES 346
41 41
42#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */