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-rw-r--r--soc/j721e/evm/rm-cfg.c328
-rw-r--r--soc/j721e/evm/sysfw_img_cfg.h6
2 files changed, 173 insertions, 161 deletions
diff --git a/soc/j721e/evm/rm-cfg.c b/soc/j721e/evm/rm-cfg.c
index e6ce6b243..51adf7385 100644
--- a/soc/j721e/evm/rm-cfg.c
+++ b/soc/j721e/evm/rm-cfg.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * K3 System Firmware Resource Management Configuration Data 2 * K3 System Firmware Resource Management Configuration Data
3 * Auto generated from K3 Resource Partitioning tool
3 * 4 *
4 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/
5 * Andreas Dannenberg <dannenberg@ti.com>
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
@@ -52,7 +52,96 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM, 52 .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
53 .size = sizeof (struct boardcfg_rm_host_cfg), 53 .size = sizeof (struct boardcfg_rm_host_cfg),
54 }, 54 },
55 .host_cfg_entries = {{0}}, 55 .host_cfg_entries = {
56 {
57 .host_id = HOST_ID_MCU_0_R5_0,
58 .allowed_atype = 0b101010,
59 .allowed_qos = 0xAAAA,
60 .allowed_orderid = 0xAAAAAAAA,
61 .allowed_priority = 0xAAAA,
62 .allowed_sched_priority = 0xAA,
63 },
64 {
65 .host_id = HOST_ID_MCU_0_R5_2,
66 .allowed_atype = 0b101010,
67 .allowed_qos = 0xAAAA,
68 .allowed_orderid = 0xAAAAAAAA,
69 .allowed_priority = 0xAAAA,
70 .allowed_sched_priority = 0xAA,
71 },
72 {
73 .host_id = HOST_ID_A72_2,
74 .allowed_atype = 0b101010,
75 .allowed_qos = 0xAAAA,
76 .allowed_orderid = 0xAAAAAAAA,
77 .allowed_priority = 0xAAAA,
78 .allowed_sched_priority = 0xAA,
79 },
80 {
81 .host_id = HOST_ID_A72_3,
82 .allowed_atype = 0b101010,
83 .allowed_qos = 0xAAAA,
84 .allowed_orderid = 0xAAAAAAAA,
85 .allowed_priority = 0xAAAA,
86 .allowed_sched_priority = 0xAA,
87 },
88 {
89 .host_id = HOST_ID_C7X_1,
90 .allowed_atype = 0b101010,
91 .allowed_qos = 0xAAAA,
92 .allowed_orderid = 0xAAAAAAAA,
93 .allowed_priority = 0xAAAA,
94 .allowed_sched_priority = 0xAA,
95 },
96 {
97 .host_id = HOST_ID_C6X_0_1,
98 .allowed_atype = 0b101010,
99 .allowed_qos = 0xAAAA,
100 .allowed_orderid = 0xAAAAAAAA,
101 .allowed_priority = 0xAAAA,
102 .allowed_sched_priority = 0xAA,
103 },
104 {
105 .host_id = HOST_ID_C6X_1_1,
106 .allowed_atype = 0b101010,
107 .allowed_qos = 0xAAAA,
108 .allowed_orderid = 0xAAAAAAAA,
109 .allowed_priority = 0xAAAA,
110 .allowed_sched_priority = 0xAA,
111 },
112 {
113 .host_id = HOST_ID_MAIN_0_R5_0,
114 .allowed_atype = 0b101010,
115 .allowed_qos = 0xAAAA,
116 .allowed_orderid = 0xAAAAAAAA,
117 .allowed_priority = 0xAAAA,
118 .allowed_sched_priority = 0xAA,
119 },
120 {
121 .host_id = HOST_ID_MAIN_0_R5_2,
122 .allowed_atype = 0b101010,
123 .allowed_qos = 0xAAAA,
124 .allowed_orderid = 0xAAAAAAAA,
125 .allowed_priority = 0xAAAA,
126 .allowed_sched_priority = 0xAA,
127 },
128 {
129 .host_id = HOST_ID_MAIN_1_R5_0,
130 .allowed_atype = 0b101010,
131 .allowed_qos = 0xAAAA,
132 .allowed_orderid = 0xAAAAAAAA,
133 .allowed_priority = 0xAAAA,
134 .allowed_sched_priority = 0xAA,
135 },
136 {
137 .host_id = HOST_ID_MAIN_1_R5_2,
138 .allowed_atype = 0b101010,
139 .allowed_qos = 0xAAAA,
140 .allowed_orderid = 0xAAAAAAAA,
141 .allowed_priority = 0xAAAA,
142 .allowed_sched_priority = 0xAA,
143 },
144 }
56 }, 145 },
57 146
58 /* boardcfg_rm_resasg */ 147 /* boardcfg_rm_resasg */
@@ -71,8 +160,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
71 160
72 /* This is actually part of .resasg */ 161 /* This is actually part of .resasg */
73 .resasg_entries = { 162 .resasg_entries = {
74 163 /* Interrupt router for C6X subsystem0 */
75 /* Interrupt router for C6x_0 */
76 { 164 {
77 .start_resource = 4, 165 .start_resource = 4,
78 .num_resource = 93, 166 .num_resource = 93,
@@ -80,8 +168,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
80 RESASG_SUBTYPE_IR_OUTPUT), 168 RESASG_SUBTYPE_IR_OUTPUT),
81 .host_id = HOST_ID_C6X_0_1, 169 .host_id = HOST_ID_C6X_0_1,
82 }, 170 },
83 171 /* Interrupt router for C6X subsystem1 */
84 /* Interrupt router for C6x_1 */
85 { 172 {
86 .start_resource = 4, 173 .start_resource = 4,
87 .num_resource = 93, 174 .num_resource = 93,
@@ -89,8 +176,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
89 RESASG_SUBTYPE_IR_OUTPUT), 176 RESASG_SUBTYPE_IR_OUTPUT),
90 .host_id = HOST_ID_C6X_1_1, 177 .host_id = HOST_ID_C6X_1_1,
91 }, 178 },
92 179 /* Compare event Interrupt router */
93 /* compare event IR */
94 { 180 {
95 .start_resource = 0, 181 .start_resource = 0,
96 .num_resource = 32, 182 .num_resource = 32,
@@ -98,8 +184,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
98 RESASG_SUBTYPE_IR_OUTPUT), 184 RESASG_SUBTYPE_IR_OUTPUT),
99 .host_id = HOST_ID_ALL, 185 .host_id = HOST_ID_ALL,
100 }, 186 },
101 187 /* Main 2 MCU Level Interrupt router */
102 /* Main 2 MCU level IRQ IR */
103 { 188 {
104 .start_resource = 0, 189 .start_resource = 0,
105 .num_resource = 32, 190 .num_resource = 32,
@@ -121,8 +206,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
121 RESASG_SUBTYPE_IR_OUTPUT), 206 RESASG_SUBTYPE_IR_OUTPUT),
122 .host_id = HOST_ID_MCU_0_R5_2, 207 .host_id = HOST_ID_MCU_0_R5_2,
123 }, 208 },
124 209 /* Main 2 MCU Pulse Interrupt router */
125 /* Main 2 MCU Pulse IRQ IR */
126 { 210 {
127 .start_resource = 0, 211 .start_resource = 0,
128 .num_resource = 24, 212 .num_resource = 24,
@@ -144,8 +228,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
144 RESASG_SUBTYPE_IR_OUTPUT), 228 RESASG_SUBTYPE_IR_OUTPUT),
145 .host_id = HOST_ID_MCU_0_R5_2, 229 .host_id = HOST_ID_MCU_0_R5_2,
146 }, 230 },
147 231 /* Main GPIO Interrupt router */
148 /* Main GPIO IR */
149 { 232 {
150 .start_resource = 0, 233 .start_resource = 0,
151 .num_resource = 8, 234 .num_resource = 8,
@@ -230,8 +313,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
230 RESASG_SUBTYPE_IR_OUTPUT), 313 RESASG_SUBTYPE_IR_OUTPUT),
231 .host_id = HOST_ID_C7X_1, 314 .host_id = HOST_ID_C7X_1,
232 }, 315 },
233 316 /* Interrupt router for Main R5F Subsystem0 */
234 /* Interrupt router for R5FSS0 cluster */
235 { 317 {
236 .start_resource = 0, 318 .start_resource = 0,
237 .num_resource = 128, 319 .num_resource = 128,
@@ -246,8 +328,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
246 RESASG_SUBTYPE_IR_OUTPUT), 328 RESASG_SUBTYPE_IR_OUTPUT),
247 .host_id = HOST_ID_MAIN_0_R5_2, 329 .host_id = HOST_ID_MAIN_0_R5_2,
248 }, 330 },
249 331 /* Interrupt router for Main R5F Subsystem1 */
250 /* Interrupt router for R5FSS1 cluster */
251 { 332 {
252 .start_resource = 0, 333 .start_resource = 0,
253 .num_resource = 128, 334 .num_resource = 128,
@@ -262,8 +343,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
262 RESASG_SUBTYPE_IR_OUTPUT), 343 RESASG_SUBTYPE_IR_OUTPUT),
263 .host_id = HOST_ID_MAIN_1_R5_2, 344 .host_id = HOST_ID_MAIN_1_R5_2,
264 }, 345 },
265 346 /* Timesync Interrupt router */
266 /* Timesync Router */
267 { 347 {
268 .start_resource = 0, 348 .start_resource = 0,
269 .num_resource = 48, 349 .num_resource = 48,
@@ -271,8 +351,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
271 RESASG_SUBTYPE_IR_OUTPUT), 351 RESASG_SUBTYPE_IR_OUTPUT),
272 .host_id = HOST_ID_ALL, 352 .host_id = HOST_ID_ALL,
273 }, 353 },
274 354 /* Wakeup GPIO Interrupt router */
275 /* WKUP GPIO IR */
276 { 355 {
277 .start_resource = 0, 356 .start_resource = 0,
278 .num_resource = 8, 357 .num_resource = 8,
@@ -343,8 +422,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
343 RESASG_SUBTYPE_IR_OUTPUT), 422 RESASG_SUBTYPE_IR_OUTPUT),
344 .host_id = HOST_ID_MAIN_0_R5_2, 423 .host_id = HOST_ID_MAIN_0_R5_2,
345 }, 424 },
346 425 /* MODSS Interrupt aggregator0 Virtual interrupts */
347 /* MODSS INTA0 VINT */
348 { 426 {
349 .start_resource = 0, 427 .start_resource = 0,
350 .num_resource = 64, 428 .num_resource = 64,
@@ -352,8 +430,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
352 RESASG_SUBTYPE_IA_VINT), 430 RESASG_SUBTYPE_IA_VINT),
353 .host_id = HOST_ID_ALL, 431 .host_id = HOST_ID_ALL,
354 }, 432 },
355 433 /* MODSS Interrupt aggregator0 Global events */
356 /* MODSS INTA0 global events */
357 { 434 {
358 .start_resource = 20480, 435 .start_resource = 20480,
359 .num_resource = 1024, 436 .num_resource = 1024,
@@ -361,8 +438,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
361 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 438 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
362 .host_id = HOST_ID_ALL, 439 .host_id = HOST_ID_ALL,
363 }, 440 },
364 441 /* MODSS Interrupt aggregator1 Virtual interrupts */
365 /* MODSS INTA1 VINT */
366 { 442 {
367 .start_resource = 0, 443 .start_resource = 0,
368 .num_resource = 64, 444 .num_resource = 64,
@@ -370,8 +446,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
370 RESASG_SUBTYPE_IA_VINT), 446 RESASG_SUBTYPE_IA_VINT),
371 .host_id = HOST_ID_ALL, 447 .host_id = HOST_ID_ALL,
372 }, 448 },
373 449 /* MODSS Interrupt aggregator1 Global events */
374 /* MODSS INTA1 global events */
375 { 450 {
376 .start_resource = 22528, 451 .start_resource = 22528,
377 .num_resource = 1024, 452 .num_resource = 1024,
@@ -379,8 +454,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
379 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 454 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
380 .host_id = HOST_ID_ALL, 455 .host_id = HOST_ID_ALL,
381 }, 456 },
382 457 /* Main NAVSS UDMA Interrupt aggregator Virtual interrupts */
383 /* Main Nav IA VINT */
384 { 458 {
385 .start_resource = 38, 459 .start_resource = 38,
386 .num_resource = 86, 460 .num_resource = 86,
@@ -451,8 +525,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
451 RESASG_SUBTYPE_IA_VINT), 525 RESASG_SUBTYPE_IA_VINT),
452 .host_id = HOST_ID_ALL, 526 .host_id = HOST_ID_ALL,
453 }, 527 },
454 528 /* Main NAVSS UDMA Interrupt aggregator Global events */
455 /* Main Nav IA global events */
456 { 529 {
457 .start_resource = 38, 530 .start_resource = 38,
458 .num_resource = 1024, 531 .num_resource = 1024,
@@ -544,8 +617,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
544 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 617 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
545 .host_id = HOST_ID_ALL, 618 .host_id = HOST_ID_ALL,
546 }, 619 },
547 620 /* Main NAVSS Non secure proxies */
548 /* Main Nav nonsecure proxies */
549 { 621 {
550 .start_resource = 0, 622 .start_resource = 0,
551 .num_resource = 4, 623 .num_resource = 4,
@@ -637,8 +709,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
637 RESASG_SUBTYPE_PROXY_PROXIES), 709 RESASG_SUBTYPE_PROXY_PROXIES),
638 .host_id = HOST_ID_ALL, 710 .host_id = HOST_ID_ALL,
639 }, 711 },
640 712 /* Main NAVSS Ring accelerator error event config */
641 /* Main Nav Ring Error OES */
642 { 713 {
643 .start_resource = 0, 714 .start_resource = 0,
644 .num_resource = 1, 715 .num_resource = 1,
@@ -646,8 +717,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
646 RESASG_SUBTYPE_RA_ERROR_OES), 717 RESASG_SUBTYPE_RA_ERROR_OES),
647 .host_id = HOST_ID_ALL, 718 .host_id = HOST_ID_ALL,
648 }, 719 },
649 720 /* Main NAVSS Ring accelerator Free rings */
650 /* Main Nav GP Ring / Free Ring */
651 { 721 {
652 .start_resource = 440, 722 .start_resource = 440,
653 .num_resource = 150, 723 .num_resource = 150,
@@ -739,8 +809,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
739 RESASG_SUBTYPE_RA_GP), 809 RESASG_SUBTYPE_RA_GP),
740 .host_id = HOST_ID_ALL, 810 .host_id = HOST_ID_ALL,
741 }, 811 },
742 812 /* Main NAVSS Rings for Normal capacity Rx channels */
743 /* Main Nav Normal Capacity RX ring */
744 { 813 {
745 .start_resource = 316, 814 .start_resource = 316,
746 .num_resource = 36, 815 .num_resource = 36,
@@ -825,8 +894,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
825 RESASG_SUBTYPE_RA_UDMAP_RX), 894 RESASG_SUBTYPE_RA_UDMAP_RX),
826 .host_id = HOST_ID_MAIN_0_R5_2, 895 .host_id = HOST_ID_MAIN_0_R5_2,
827 }, 896 },
828 897 /* Main NAVSS Rings for Normal capacity Tx channels */
829 /* Main Nav Normal Capacity TX ring */
830 { 898 {
831 .start_resource = 16, 899 .start_resource = 16,
832 .num_resource = 36, 900 .num_resource = 36,
@@ -918,8 +986,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
918 RESASG_SUBTYPE_RA_UDMAP_TX), 986 RESASG_SUBTYPE_RA_UDMAP_TX),
919 .host_id = HOST_ID_ALL, 987 .host_id = HOST_ID_ALL,
920 }, 988 },
921 989 /* Main NAVSS Rings for extended Tx channels for DRU */
922 /* Main Nav TX rings for extended channels */
923 { 990 {
924 .start_resource = 140, 991 .start_resource = 140,
925 .num_resource = 16, 992 .num_resource = 16,
@@ -943,13 +1010,20 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
943 }, 1010 },
944 { 1011 {
945 .start_resource = 168, 1012 .start_resource = 168,
946 .num_resource = 132, 1013 .num_resource = 4,
947 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0, 1014 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
948 RESASG_SUBTYPE_RA_UDMAP_TX_EXT), 1015 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
949 .host_id = HOST_ID_MAIN_0_R5_0, 1016 .host_id = HOST_ID_MAIN_0_R5_0,
950 }, 1017 },
951 1018 /* Main NAVSS Rings for extended Tx channels for HWA */
952 /* Main Nav High Capacity RX ring */ 1019 {
1020 .start_resource = 172,
1021 .num_resource = 128,
1022 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1023 RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
1024 .host_id = HOST_ID_MAIN_0_R5_0,
1025 },
1026 /* Main NAVSS Rings for High capacity Rx channels */
953 { 1027 {
954 .start_resource = 304, 1028 .start_resource = 304,
955 .num_resource = 4, 1029 .num_resource = 4,
@@ -971,8 +1045,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
971 RESASG_SUBTYPE_RA_UDMAP_RX_H), 1045 RESASG_SUBTYPE_RA_UDMAP_RX_H),
972 .host_id = HOST_ID_ALL, 1046 .host_id = HOST_ID_ALL,
973 }, 1047 },
974 1048 /* Main NAVSS Rings for Ultra high capacity Rx channels */
975 /* Main Nav Ultra High Capacity RX ring */
976 { 1049 {
977 .start_resource = 300, 1050 .start_resource = 300,
978 .num_resource = 2, 1051 .num_resource = 2,
@@ -987,8 +1060,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
987 RESASG_SUBTYPE_RA_UDMAP_RX_UH), 1060 RESASG_SUBTYPE_RA_UDMAP_RX_UH),
988 .host_id = HOST_ID_MAIN_0_R5_0, 1061 .host_id = HOST_ID_MAIN_0_R5_0,
989 }, 1062 },
990 1063 /* Main NAVSS Rings for High capacity Tx channels */
991 /* Main Nav High Capacity TX ring */
992 { 1064 {
993 .start_resource = 4, 1065 .start_resource = 4,
994 .num_resource = 4, 1066 .num_resource = 4,
@@ -1010,8 +1082,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1010 RESASG_SUBTYPE_RA_UDMAP_TX_H), 1082 RESASG_SUBTYPE_RA_UDMAP_TX_H),
1011 .host_id = HOST_ID_ALL, 1083 .host_id = HOST_ID_ALL,
1012 }, 1084 },
1013 1085 /* Main NAVSS Rings for Ultra high capacity Tx channels */
1014 /* Main Nav Ultra High Capacity TX ring */
1015 { 1086 {
1016 .start_resource = 0, 1087 .start_resource = 0,
1017 .num_resource = 2, 1088 .num_resource = 2,
@@ -1026,8 +1097,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1026 RESASG_SUBTYPE_RA_UDMAP_TX_UH), 1097 RESASG_SUBTYPE_RA_UDMAP_TX_UH),
1027 .host_id = HOST_ID_MAIN_0_R5_0, 1098 .host_id = HOST_ID_MAIN_0_R5_0,
1028 }, 1099 },
1029 1100 /* Main NAVSS Ring accelerator virt_id range */
1030 /* virt_id range */
1031 { 1101 {
1032 .start_resource = 2, 1102 .start_resource = 2,
1033 .num_resource = 1, 1103 .num_resource = 1,
@@ -1042,15 +1112,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1042 RESASG_SUBTYPE_RA_VIRTID), 1112 RESASG_SUBTYPE_RA_VIRTID),
1043 .host_id = HOST_ID_A72_3, 1113 .host_id = HOST_ID_A72_3,
1044 }, 1114 },
1045 { 1115 /* Main NAVSS Ring accelerator ring monitors */
1046 .start_resource = 4,
1047 .num_resource = 4,
1048 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
1049 RESASG_SUBTYPE_RA_VIRTID),
1050 .host_id = HOST_ID_ALL,
1051 },
1052
1053 /* Main Nav ring monitors */
1054 { 1116 {
1055 .start_resource = 0, 1117 .start_resource = 0,
1056 .num_resource = 3, 1118 .num_resource = 3,
@@ -1142,8 +1204,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1142 RESASG_SUBTYPE_RA_MONITORS), 1204 RESASG_SUBTYPE_RA_MONITORS),
1143 .host_id = HOST_ID_ALL, 1205 .host_id = HOST_ID_ALL,
1144 }, 1206 },
1145 1207 /* Main NAVSS UDMA Rx free flows */
1146 /* Main Nav Free RX Flow */
1147 { 1208 {
1148 .start_resource = 140, 1209 .start_resource = 140,
1149 .num_resource = 16, 1210 .num_resource = 16,
@@ -1165,8 +1226,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1165 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), 1226 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
1166 .host_id = HOST_ID_ALL, 1227 .host_id = HOST_ID_ALL,
1167 }, 1228 },
1168 1229 /* Main NAVSS invalid flow event config */
1169 /* Main Nav invalid flow OES */
1170 { 1230 {
1171 .start_resource = 0, 1231 .start_resource = 0,
1172 .num_resource = 1, 1232 .num_resource = 1,
@@ -1174,8 +1234,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1174 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), 1234 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
1175 .host_id = HOST_ID_ALL, 1235 .host_id = HOST_ID_ALL,
1176 }, 1236 },
1177 1237 /* Main NAVSS UDMA global event trigger */
1178 /* Main Nav UDMA global event trigger */
1179 { 1238 {
1180 .start_resource = 49152, 1239 .start_resource = 49152,
1181 .num_resource = 1024, 1240 .num_resource = 1024,
@@ -1183,8 +1242,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1183 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), 1242 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
1184 .host_id = HOST_ID_ALL, 1243 .host_id = HOST_ID_ALL,
1185 }, 1244 },
1186 1245 /* Main NAVSS UDMA global config */
1187 /* Main Nav UDMA global event config */
1188 { 1246 {
1189 .start_resource = 0, 1247 .start_resource = 0,
1190 .num_resource = 1, 1248 .num_resource = 1,
@@ -1192,8 +1250,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1192 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), 1250 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
1193 .host_id = HOST_ID_ALL, 1251 .host_id = HOST_ID_ALL,
1194 }, 1252 },
1195 1253 /* Main NAVSS UDMA Normal capacity Rx channels */
1196 /* Main Nav Normal Capacity RX channel */
1197 { 1254 {
1198 .start_resource = 16, 1255 .start_resource = 16,
1199 .num_resource = 36, 1256 .num_resource = 36,
@@ -1278,8 +1335,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1278 RESASG_SUBTYPE_UDMAP_RX_CHAN), 1335 RESASG_SUBTYPE_UDMAP_RX_CHAN),
1279 .host_id = HOST_ID_MAIN_0_R5_2, 1336 .host_id = HOST_ID_MAIN_0_R5_2,
1280 }, 1337 },
1281 1338 /* Main NAVSS UDMA High capacity Rx channels */
1282 /* Main Nav High Capacity RX channel */
1283 { 1339 {
1284 .start_resource = 4, 1340 .start_resource = 4,
1285 .num_resource = 4, 1341 .num_resource = 4,
@@ -1301,8 +1357,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1301 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 1357 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
1302 .host_id = HOST_ID_ALL, 1358 .host_id = HOST_ID_ALL,
1303 }, 1359 },
1304 1360 /* Main NAVSS UDMA Ultra high capacity Rx channels */
1305 /* Main Nav Ultra High Capacity RX channel */
1306 { 1361 {
1307 .start_resource = 0, 1362 .start_resource = 0,
1308 .num_resource = 2, 1363 .num_resource = 2,
@@ -1317,8 +1372,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1317 RESASG_SUBTYPE_UDMAP_RX_UHCHAN), 1372 RESASG_SUBTYPE_UDMAP_RX_UHCHAN),
1318 .host_id = HOST_ID_MAIN_0_R5_0, 1373 .host_id = HOST_ID_MAIN_0_R5_0,
1319 }, 1374 },
1320 1375 /* Main NAVSS UDMA Normal capacity Tx channels */
1321 /* Main Nav Normal Capacity TX channel */
1322 { 1376 {
1323 .start_resource = 16, 1377 .start_resource = 16,
1324 .num_resource = 36, 1378 .num_resource = 36,
@@ -1410,8 +1464,15 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1410 RESASG_SUBTYPE_UDMAP_TX_CHAN), 1464 RESASG_SUBTYPE_UDMAP_TX_CHAN),
1411 .host_id = HOST_ID_ALL, 1465 .host_id = HOST_ID_ALL,
1412 }, 1466 },
1413 1467 /* Main NAVSS UDMA extended Tx channels for HWA */
1414 /* Main Nav extended TX channels */ 1468 {
1469 .start_resource = 172,
1470 .num_resource = 128,
1471 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1472 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1473 .host_id = HOST_ID_MAIN_0_R5_0,
1474 },
1475 /* Main NAVSS UDMA extended Tx channels for DRU */
1415 { 1476 {
1416 .start_resource = 140, 1477 .start_resource = 140,
1417 .num_resource = 16, 1478 .num_resource = 16,
@@ -1435,13 +1496,12 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1435 }, 1496 },
1436 { 1497 {
1437 .start_resource = 168, 1498 .start_resource = 168,
1438 .num_resource = 132, 1499 .num_resource = 4,
1439 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0, 1500 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
1440 RESASG_SUBTYPE_UDMAP_TX_ECHAN), 1501 RESASG_SUBTYPE_UDMAP_TX_ECHAN),
1441 .host_id = HOST_ID_MAIN_0_R5_0, 1502 .host_id = HOST_ID_MAIN_0_R5_0,
1442 }, 1503 },
1443 1504 /* Main NAVSS UDMA High capacity Tx channels */
1444 /* Main Nav High Capacity TX channel */
1445 { 1505 {
1446 .start_resource = 4, 1506 .start_resource = 4,
1447 .num_resource = 4, 1507 .num_resource = 4,
@@ -1463,8 +1523,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1463 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 1523 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
1464 .host_id = HOST_ID_ALL, 1524 .host_id = HOST_ID_ALL,
1465 }, 1525 },
1466 1526 /* Main NAVSS UDMA Ultra high capacity Tx channels */
1467 /* Main Nav Ultra High Capacity TX channel */
1468 { 1527 {
1469 .start_resource = 0, 1528 .start_resource = 0,
1470 .num_resource = 2, 1529 .num_resource = 2,
@@ -1479,8 +1538,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1479 RESASG_SUBTYPE_UDMAP_TX_UHCHAN), 1538 RESASG_SUBTYPE_UDMAP_TX_UHCHAN),
1480 .host_id = HOST_ID_MAIN_0_R5_0, 1539 .host_id = HOST_ID_MAIN_0_R5_0,
1481 }, 1540 },
1482 1541 /* Main NAVSS Interrupt router */
1483 /* Main Nav IR */
1484 { 1542 {
1485 .start_resource = 10, 1543 .start_resource = 10,
1486 .num_resource = 100, 1544 .num_resource = 100,
@@ -1538,13 +1596,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1538 .host_id = HOST_ID_C6X_0_1, 1596 .host_id = HOST_ID_C6X_0_1,
1539 }, 1597 },
1540 { 1598 {
1541 .start_resource = 348,
1542 .num_resource = 4,
1543 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
1544 RESASG_SUBTYPE_IR_OUTPUT),
1545 .host_id = HOST_ID_C6X_0_1,
1546 },
1547 {
1548 .start_resource = 352, 1599 .start_resource = 352,
1549 .num_resource = 24, 1600 .num_resource = 24,
1550 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0, 1601 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
@@ -1552,13 +1603,6 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1552 .host_id = HOST_ID_C6X_1_1, 1603 .host_id = HOST_ID_C6X_1_1,
1553 }, 1604 },
1554 { 1605 {
1555 .start_resource = 380,
1556 .num_resource = 4,
1557 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
1558 RESASG_SUBTYPE_IR_OUTPUT),
1559 .host_id = HOST_ID_C6X_1_1,
1560 },
1561 {
1562 .start_resource = 400, 1606 .start_resource = 400,
1563 .num_resource = 4, 1607 .num_resource = 4,
1564 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0, 1608 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
@@ -1579,15 +1623,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1579 RESASG_SUBTYPE_IR_OUTPUT), 1623 RESASG_SUBTYPE_IR_OUTPUT),
1580 .host_id = HOST_ID_MCU_0_R5_2, 1624 .host_id = HOST_ID_MCU_0_R5_2,
1581 }, 1625 },
1582 { 1626 /* MCU NAVSS Interrupt aggregator Virtual interrupts */
1583 .start_resource = 408,
1584 .num_resource = 104,
1585 .type = RESASG_UTYPE (J721E_DEV_NAVSS0_INTR_ROUTER_0,
1586 RESASG_SUBTYPE_IR_OUTPUT),
1587 .host_id = HOST_ID_ALL,
1588 },
1589
1590 /* MCU Nav IA VINT */
1591 { 1627 {
1592 .start_resource = 8, 1628 .start_resource = 8,
1593 .num_resource = 32, 1629 .num_resource = 32,
@@ -1679,8 +1715,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1679 RESASG_SUBTYPE_IA_VINT), 1715 RESASG_SUBTYPE_IA_VINT),
1680 .host_id = HOST_ID_ALL, 1716 .host_id = HOST_ID_ALL,
1681 }, 1717 },
1682 1718 /* MCU NAVSS Interrupt aggregator Global events */
1683 /* MCU Nav IA global events */
1684 { 1719 {
1685 .start_resource = 16392, 1720 .start_resource = 16392,
1686 .num_resource = 128, 1721 .num_resource = 128,
@@ -1772,8 +1807,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1772 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), 1807 RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
1773 .host_id = HOST_ID_ALL, 1808 .host_id = HOST_ID_ALL,
1774 }, 1809 },
1775 1810 /* MCU NAVSS Non secure proxies */
1776 /* MCU Nav nonsecure proxies */
1777 { 1811 {
1778 .start_resource = 1, 1812 .start_resource = 1,
1779 .num_resource = 4, 1813 .num_resource = 4,
@@ -1865,8 +1899,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1865 RESASG_SUBTYPE_PROXY_PROXIES), 1899 RESASG_SUBTYPE_PROXY_PROXIES),
1866 .host_id = HOST_ID_ALL, 1900 .host_id = HOST_ID_ALL,
1867 }, 1901 },
1868 1902 /* MCU NAVSS Ring accelerator error event config */
1869 /* MCU Nav Ring Error OES */
1870 { 1903 {
1871 .start_resource = 0, 1904 .start_resource = 0,
1872 .num_resource = 1, 1905 .num_resource = 1,
@@ -1874,8 +1907,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1874 RESASG_SUBTYPE_RA_ERROR_OES), 1907 RESASG_SUBTYPE_RA_ERROR_OES),
1875 .host_id = HOST_ID_ALL, 1908 .host_id = HOST_ID_ALL,
1876 }, 1909 },
1877 1910 /* MCU NAVSS Ring accelerator Free rings */
1878 /* MCU Nav GP Ring / Free Ring */
1879 { 1911 {
1880 .start_resource = 96, 1912 .start_resource = 96,
1881 .num_resource = 20, 1913 .num_resource = 20,
@@ -1967,8 +1999,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
1967 RESASG_SUBTYPE_RA_GP), 1999 RESASG_SUBTYPE_RA_GP),
1968 .host_id = HOST_ID_ALL, 2000 .host_id = HOST_ID_ALL,
1969 }, 2001 },
1970 2002 /* MCU NAVSS Rings for Normal capacity Rx channels */
1971 /* MCU Nav Normal Capacity Rx ring */
1972 { 2003 {
1973 .start_resource = 50, 2004 .start_resource = 50,
1974 .num_resource = 12, 2005 .num_resource = 12,
@@ -2060,8 +2091,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2060 RESASG_SUBTYPE_RA_UDMAP_RX), 2091 RESASG_SUBTYPE_RA_UDMAP_RX),
2061 .host_id = HOST_ID_ALL, 2092 .host_id = HOST_ID_ALL,
2062 }, 2093 },
2063 2094 /* MCU NAVSS Rings for Normal capacity Tx channels */
2064 /* MCU Nav Normal Capacity Tx ring */
2065 { 2095 {
2066 .start_resource = 2, 2096 .start_resource = 2,
2067 .num_resource = 12, 2097 .num_resource = 12,
@@ -2153,8 +2183,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2153 RESASG_SUBTYPE_RA_UDMAP_TX), 2183 RESASG_SUBTYPE_RA_UDMAP_TX),
2154 .host_id = HOST_ID_ALL, 2184 .host_id = HOST_ID_ALL,
2155 }, 2185 },
2156 2186 /* MCU NAVSS Rings for High capacity Rx channels */
2157 /* MCU Nav High Capacity Rx ring */
2158 { 2187 {
2159 .start_resource = 48, 2188 .start_resource = 48,
2160 .num_resource = 2, 2189 .num_resource = 2,
@@ -2169,8 +2198,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2169 RESASG_SUBTYPE_RA_UDMAP_RX_H), 2198 RESASG_SUBTYPE_RA_UDMAP_RX_H),
2170 .host_id = HOST_ID_MCU_0_R5_1, 2199 .host_id = HOST_ID_MCU_0_R5_1,
2171 }, 2200 },
2172 2201 /* MCU NAVSS Rings for High capacity Tx channels */
2173 /* MCU Nav High Capacity Tx ring */
2174 { 2202 {
2175 .start_resource = 0, 2203 .start_resource = 0,
2176 .num_resource = 2, 2204 .num_resource = 2,
@@ -2185,8 +2213,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2185 RESASG_SUBTYPE_RA_UDMAP_TX_H), 2213 RESASG_SUBTYPE_RA_UDMAP_TX_H),
2186 .host_id = HOST_ID_MCU_0_R5_1, 2214 .host_id = HOST_ID_MCU_0_R5_1,
2187 }, 2215 },
2188 2216 /* MCU NAVSS Ring accelerator virt_id range */
2189 /* virt_id range */
2190 { 2217 {
2191 .start_resource = 2, 2218 .start_resource = 2,
2192 .num_resource = 1, 2219 .num_resource = 1,
@@ -2201,15 +2228,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2201 RESASG_SUBTYPE_RA_VIRTID), 2228 RESASG_SUBTYPE_RA_VIRTID),
2202 .host_id = HOST_ID_A72_3, 2229 .host_id = HOST_ID_A72_3,
2203 }, 2230 },
2204 { 2231 /* MCU NAVSS Ring accelerator ring monitors */
2205 .start_resource = 4,
2206 .num_resource = 4,
2207 .type = RESASG_UTYPE (J721E_DEV_MCU_NAVSS0_RINGACC_0,
2208 RESASG_SUBTYPE_RA_VIRTID),
2209 .host_id = HOST_ID_ALL,
2210 },
2211
2212 /* MCU Nav ring monitors */
2213 { 2232 {
2214 .start_resource = 0, 2233 .start_resource = 0,
2215 .num_resource = 3, 2234 .num_resource = 3,
@@ -2294,8 +2313,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2294 RESASG_SUBTYPE_RA_MONITORS), 2313 RESASG_SUBTYPE_RA_MONITORS),
2295 .host_id = HOST_ID_MAIN_0_R5_2, 2314 .host_id = HOST_ID_MAIN_0_R5_2,
2296 }, 2315 },
2297 2316 /* MCU NAVSS UDMA Rx free flows */
2298 /* MCU Nav Free RX Flow */
2299 { 2317 {
2300 .start_resource = 48, 2318 .start_resource = 48,
2301 .num_resource = 8, 2319 .num_resource = 8,
@@ -2366,8 +2384,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2366 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), 2384 RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
2367 .host_id = HOST_ID_ALL, 2385 .host_id = HOST_ID_ALL,
2368 }, 2386 },
2369 2387 /* MCU NAVSS invalid flow event config */
2370 /* MCU Nav invalid flow OES */
2371 { 2388 {
2372 .start_resource = 0, 2389 .start_resource = 0,
2373 .num_resource = 1, 2390 .num_resource = 1,
@@ -2375,8 +2392,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2375 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), 2392 RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
2376 .host_id = HOST_ID_ALL, 2393 .host_id = HOST_ID_ALL,
2377 }, 2394 },
2378 2395 /* MCU NAVSS UDMA global event trigger */
2379 /* MCU Nav UDMA global event trigger */
2380 { 2396 {
2381 .start_resource = 56320, 2397 .start_resource = 56320,
2382 .num_resource = 256, 2398 .num_resource = 256,
@@ -2384,8 +2400,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2384 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), 2400 RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
2385 .host_id = HOST_ID_ALL, 2401 .host_id = HOST_ID_ALL,
2386 }, 2402 },
2387 2403 /* MCU NAVSS UDMA global config */
2388 /* MCU Nav UDMA global event config */
2389 { 2404 {
2390 .start_resource = 0, 2405 .start_resource = 0,
2391 .num_resource = 1, 2406 .num_resource = 1,
@@ -2393,8 +2408,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2393 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), 2408 RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
2394 .host_id = HOST_ID_ALL, 2409 .host_id = HOST_ID_ALL,
2395 }, 2410 },
2396 2411 /* MCU NAVSS UDMA Normal capacity Rx channels */
2397 /* MCU Nav Normal Capacity RX channel */
2398 { 2412 {
2399 .start_resource = 2, 2413 .start_resource = 2,
2400 .num_resource = 12, 2414 .num_resource = 12,
@@ -2486,8 +2500,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2486 RESASG_SUBTYPE_UDMAP_RX_CHAN), 2500 RESASG_SUBTYPE_UDMAP_RX_CHAN),
2487 .host_id = HOST_ID_ALL, 2501 .host_id = HOST_ID_ALL,
2488 }, 2502 },
2489 2503 /* MCU NAVSS UDMA High capacity Rx channels */
2490 /* MCU Nav High Capacity RX channel */
2491 { 2504 {
2492 .start_resource = 0, 2505 .start_resource = 0,
2493 .num_resource = 2, 2506 .num_resource = 2,
@@ -2502,8 +2515,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2502 RESASG_SUBTYPE_UDMAP_RX_HCHAN), 2515 RESASG_SUBTYPE_UDMAP_RX_HCHAN),
2503 .host_id = HOST_ID_MCU_0_R5_1, 2516 .host_id = HOST_ID_MCU_0_R5_1,
2504 }, 2517 },
2505 2518 /* MCU NAVSS UDMA Normal capacity Tx channels */
2506 /* MCU Nav Normal Capacity TX channel */
2507 { 2519 {
2508 .start_resource = 2, 2520 .start_resource = 2,
2509 .num_resource = 12, 2521 .num_resource = 12,
@@ -2595,8 +2607,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2595 RESASG_SUBTYPE_UDMAP_TX_CHAN), 2607 RESASG_SUBTYPE_UDMAP_TX_CHAN),
2596 .host_id = HOST_ID_ALL, 2608 .host_id = HOST_ID_ALL,
2597 }, 2609 },
2598 2610 /* MCU NAVSS UDMA High capacity Tx channels */
2599 /* MCU Nav High Capacity TX channel */
2600 { 2611 {
2601 .start_resource = 0, 2612 .start_resource = 0,
2602 .num_resource = 2, 2613 .num_resource = 2,
@@ -2611,8 +2622,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
2611 RESASG_SUBTYPE_UDMAP_TX_HCHAN), 2622 RESASG_SUBTYPE_UDMAP_TX_HCHAN),
2612 .host_id = HOST_ID_MCU_0_R5_1, 2623 .host_id = HOST_ID_MCU_0_R5_1,
2613 }, 2624 },
2614 2625 /* MCU NAVSS Interrupt router */
2615 /* MCU Nav IR */
2616 { 2626 {
2617 .start_resource = 4, 2627 .start_resource = 4,
2618 .num_resource = 28, 2628 .num_resource = 28,
diff --git a/soc/j721e/evm/sysfw_img_cfg.h b/soc/j721e/evm/sysfw_img_cfg.h
index 8b8988b96..e539d9808 100644
--- a/soc/j721e/evm/sysfw_img_cfg.h
+++ b/soc/j721e/evm/sysfw_img_cfg.h
@@ -1,5 +1,7 @@
1/* 1/*
2 * K3 System Firmware Configuration Data 2 * K3 System Firmware Resource Management Board Config Data
3 * Auto generated from K3 Resource Partitioning tool
4 *
3 * 5 *
4 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/ 6 * Copyright (C) 2019-2020 Texas Instruments Incorporated - http://www.ti.com/
5 * 7 *
@@ -35,6 +37,6 @@
35#ifndef SYSFW_IMG_CFG_H 37#ifndef SYSFW_IMG_CFG_H
36#define SYSFW_IMG_CFG_H 38#define SYSFW_IMG_CFG_H
37 39
38#define BOARDCFG_RM_RESASG_ENTRIES 349 40#define BOARDCFG_RM_RESASG_ENTRIES 346
39 41
40#endif /* SYSFW_IMG_CFG_H */ 42#endif /* SYSFW_IMG_CFG_H */
generated by cgit v1.2.3 (git 2.39.2)