diff options
Diffstat (limited to 'soc/am65x_sr2')
-rw-r--r-- | soc/am65x_sr2/evm/rm-cfg.c | 1565 | ||||
-rw-r--r-- | soc/am65x_sr2/evm/sysfw_img_cfg.h | 8 |
2 files changed, 1367 insertions, 206 deletions
diff --git a/soc/am65x_sr2/evm/rm-cfg.c b/soc/am65x_sr2/evm/rm-cfg.c index 0a4f13a5f..eb0111b43 100644 --- a/soc/am65x_sr2/evm/rm-cfg.c +++ b/soc/am65x_sr2/evm/rm-cfg.c | |||
@@ -1,8 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * K3 System Firmware Resource Management Configuration Data | 2 | * K3 System Firmware Resource Management Configuration Data |
3 | * Auto generated from K3 Resource Partitioning tool | ||
3 | * | 4 | * |
4 | * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/ | 5 | * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/ |
5 | * Andreas Dannenberg <dannenberg@ti.com> | ||
6 | * | 6 | * |
7 | * Redistribution and use in source and binary forms, with or without | 7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions | 8 | * modification, are permitted provided that the following conditions |
@@ -34,8 +34,11 @@ | |||
34 | */ | 34 | */ |
35 | 35 | ||
36 | #include "common.h" | 36 | #include "common.h" |
37 | #include <hosts.h> | ||
38 | #include <devices.h> | ||
39 | #include <resasg_types.h> | ||
37 | 40 | ||
38 | const struct boardcfg_rm_local am65_boardcfg_rm_data = { | 41 | const struct boardcfg_rm_local am65x_boardcfg_rm_data = { |
39 | .rm_boardcfg = { | 42 | .rm_boardcfg = { |
40 | /* boardcfg_abi_rev */ | 43 | /* boardcfg_abi_rev */ |
41 | .rev = { | 44 | .rev = { |
@@ -47,19 +50,53 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = { | |||
47 | .host_cfg = { | 50 | .host_cfg = { |
48 | .subhdr = { | 51 | .subhdr = { |
49 | .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM, | 52 | .magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM, |
50 | .size = sizeof(struct boardcfg_rm_host_cfg), | 53 | .size = sizeof (struct boardcfg_rm_host_cfg), |
51 | }, | 54 | }, |
52 | .host_cfg_entries = {{ 0 } }, | 55 | .host_cfg_entries = { |
56 | { | ||
57 | .host_id = HOST_ID_R5_0, | ||
58 | .allowed_atype = 0b101010, | ||
59 | .allowed_qos = 0xAAAA, | ||
60 | .allowed_orderid = 0xAAAAAAAA, | ||
61 | .allowed_priority = 0xAAAA, | ||
62 | .allowed_sched_priority = 0xAA, | ||
63 | }, | ||
64 | { | ||
65 | .host_id = HOST_ID_R5_2, | ||
66 | .allowed_atype = 0b101010, | ||
67 | .allowed_qos = 0xAAAA, | ||
68 | .allowed_orderid = 0xAAAAAAAA, | ||
69 | .allowed_priority = 0xAAAA, | ||
70 | .allowed_sched_priority = 0xAA, | ||
71 | }, | ||
72 | { | ||
73 | .host_id = HOST_ID_A53_2, | ||
74 | .allowed_atype = 0b101010, | ||
75 | .allowed_qos = 0xAAAA, | ||
76 | .allowed_orderid = 0xAAAAAAAA, | ||
77 | .allowed_priority = 0xAAAA, | ||
78 | .allowed_sched_priority = 0xAA, | ||
79 | }, | ||
80 | { | ||
81 | .host_id = HOST_ID_A53_3, | ||
82 | .allowed_atype = 0b101010, | ||
83 | .allowed_qos = 0xAAAA, | ||
84 | .allowed_orderid = 0xAAAAAAAA, | ||
85 | .allowed_priority = 0xAAAA, | ||
86 | .allowed_sched_priority = 0xAA, | ||
87 | }, | ||
88 | } | ||
53 | }, | 89 | }, |
54 | 90 | ||
55 | /* boardcfg_rm_resasg */ | 91 | /* boardcfg_rm_resasg */ |
56 | .resasg = { | 92 | .resasg = { |
57 | .subhdr = { | 93 | .subhdr = { |
58 | .magic = BOARDCFG_RM_RESASG_MAGIC_NUM, | 94 | .magic = BOARDCFG_RM_RESASG_MAGIC_NUM, |
59 | .size = sizeof(struct boardcfg_rm_resasg), | 95 | .size = sizeof (struct boardcfg_rm_resasg), |
60 | }, | 96 | }, |
61 | .resasg_entries_size = BOARDCFG_RM_RESASG_ENTRIES * | 97 | .resasg_entries_size = |
62 | sizeof(struct boardcfg_rm_resasg_entry), | 98 | BOARDCFG_RM_RESASG_ENTRIES * |
99 | sizeof (struct boardcfg_rm_resasg_entry), | ||
63 | .reserved = 0, | 100 | .reserved = 0, |
64 | /* .resasg_entries is set via boardcfg_rm_local */ | 101 | /* .resasg_entries is set via boardcfg_rm_local */ |
65 | }, | 102 | }, |
@@ -67,391 +104,1513 @@ const struct boardcfg_rm_local am65_boardcfg_rm_data = { | |||
67 | 104 | ||
68 | /* This is actually part of .resasg */ | 105 | /* This is actually part of .resasg */ |
69 | .resasg_entries = { | 106 | .resasg_entries = { |
107 | /* Compare event Interrupt router */ | ||
108 | { | ||
109 | .start_resource = 0, | ||
110 | .num_resource = 12, | ||
111 | .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0, | ||
112 | RESASG_SUBTYPE_IR_OUTPUT), | ||
113 | .host_id = HOST_ID_A53_2, | ||
114 | }, | ||
115 | { | ||
116 | .start_resource = 12, | ||
117 | .num_resource = 4, | ||
118 | .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0, | ||
119 | RESASG_SUBTYPE_IR_OUTPUT), | ||
120 | .host_id = HOST_ID_A53_3, | ||
121 | }, | ||
70 | { | 122 | { |
71 | .start_resource = 16, | 123 | .start_resource = 16, |
72 | .num_resource = 240, | 124 | .num_resource = 8, |
73 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, | 125 | .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0, |
74 | RESASG_SUBTYPE_IA_VINT), | 126 | RESASG_SUBTYPE_IR_OUTPUT), |
127 | .host_id = HOST_ID_R5_0, | ||
128 | }, | ||
129 | { | ||
130 | .start_resource = 24, | ||
131 | .num_resource = 8, | ||
132 | .type = RESASG_UTYPE (AM6_DEV_CMPEVENT_INTRTR0, | ||
133 | RESASG_SUBTYPE_IR_OUTPUT), | ||
134 | .host_id = HOST_ID_R5_2, | ||
135 | }, | ||
136 | /* Main 2 MCU Level Interrupt Router */ | ||
137 | { | ||
138 | .start_resource = 0, | ||
139 | .num_resource = 32, | ||
140 | .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_LVL_INTRTR0, | ||
141 | RESASG_SUBTYPE_IR_OUTPUT), | ||
142 | .host_id = HOST_ID_R5_0, | ||
143 | }, | ||
144 | { | ||
145 | .start_resource = 32, | ||
146 | .num_resource = 32, | ||
147 | .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_LVL_INTRTR0, | ||
148 | RESASG_SUBTYPE_IR_OUTPUT), | ||
149 | .host_id = HOST_ID_R5_2, | ||
150 | }, | ||
151 | /* Main 2 MCU Pulse Interrupt Router */ | ||
152 | { | ||
153 | .start_resource = 0, | ||
154 | .num_resource = 24, | ||
155 | .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_PLS_INTRTR0, | ||
156 | RESASG_SUBTYPE_IR_OUTPUT), | ||
157 | .host_id = HOST_ID_R5_0, | ||
158 | }, | ||
159 | { | ||
160 | .start_resource = 24, | ||
161 | .num_resource = 24, | ||
162 | .type = RESASG_UTYPE (AM6_DEV_MAIN2MCU_PLS_INTRTR0, | ||
163 | RESASG_SUBTYPE_IR_OUTPUT), | ||
164 | .host_id = HOST_ID_R5_2, | ||
165 | }, | ||
166 | /* Main GPIO Interrupt Router */ | ||
167 | { | ||
168 | .start_resource = 0, | ||
169 | .num_resource = 20, | ||
170 | .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0, | ||
171 | RESASG_SUBTYPE_IR_OUTPUT), | ||
75 | .host_id = HOST_ID_A53_2, | 172 | .host_id = HOST_ID_A53_2, |
76 | }, | 173 | }, |
77 | { | 174 | { |
175 | .start_resource = 20, | ||
176 | .num_resource = 4, | ||
177 | .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0, | ||
178 | RESASG_SUBTYPE_IR_OUTPUT), | ||
179 | .host_id = HOST_ID_A53_3, | ||
180 | }, | ||
181 | { | ||
182 | .start_resource = 24, | ||
183 | .num_resource = 4, | ||
184 | .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0, | ||
185 | RESASG_SUBTYPE_IR_OUTPUT), | ||
186 | .host_id = HOST_ID_R5_0, | ||
187 | }, | ||
188 | { | ||
189 | .start_resource = 28, | ||
190 | .num_resource = 4, | ||
191 | .type = RESASG_UTYPE (AM6_DEV_GPIOMUX_INTRTR0, | ||
192 | RESASG_SUBTYPE_IR_OUTPUT), | ||
193 | .host_id = HOST_ID_R5_2, | ||
194 | }, | ||
195 | /* Timesync Interrupt router */ | ||
196 | { | ||
197 | .start_resource = 0, | ||
198 | .num_resource = 16, | ||
199 | .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0, | ||
200 | RESASG_SUBTYPE_IR_OUTPUT), | ||
201 | .host_id = HOST_ID_R5_0, | ||
202 | }, | ||
203 | { | ||
204 | .start_resource = 16, | ||
205 | .num_resource = 16, | ||
206 | .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0, | ||
207 | RESASG_SUBTYPE_IR_OUTPUT), | ||
208 | .host_id = HOST_ID_R5_2, | ||
209 | }, | ||
210 | { | ||
211 | .start_resource = 32, | ||
212 | .num_resource = 8, | ||
213 | .type = RESASG_UTYPE (AM6_DEV_TIMESYNC_INTRTR0, | ||
214 | RESASG_SUBTYPE_IR_OUTPUT), | ||
215 | .host_id = HOST_ID_ALL, | ||
216 | }, | ||
217 | /* Wakeup GPIO Interrupt router */ | ||
218 | { | ||
219 | .start_resource = 0, | ||
220 | .num_resource = 4, | ||
221 | .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0, | ||
222 | RESASG_SUBTYPE_IR_OUTPUT), | ||
223 | .host_id = HOST_ID_A53_2, | ||
224 | }, | ||
225 | { | ||
226 | .start_resource = 4, | ||
227 | .num_resource = 4, | ||
228 | .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0, | ||
229 | RESASG_SUBTYPE_IR_OUTPUT), | ||
230 | .host_id = HOST_ID_A53_3, | ||
231 | }, | ||
232 | { | ||
233 | .start_resource = 8, | ||
234 | .num_resource = 4, | ||
235 | .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0, | ||
236 | RESASG_SUBTYPE_IR_OUTPUT), | ||
237 | .host_id = HOST_ID_R5_0, | ||
238 | }, | ||
239 | { | ||
240 | .start_resource = 12, | ||
241 | .num_resource = 4, | ||
242 | .type = RESASG_UTYPE (AM6_DEV_WKUP_GPIOMUX_INTRTR0, | ||
243 | RESASG_SUBTYPE_IR_OUTPUT), | ||
244 | .host_id = HOST_ID_R5_2, | ||
245 | }, | ||
246 | /* Main NAVSS UDMA Interrupt aggregator Virtual interrupts */ | ||
247 | { | ||
248 | .start_resource = 16, | ||
249 | .num_resource = 80, | ||
250 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
251 | RESASG_SUBTYPE_IA_VINT), | ||
252 | .host_id = HOST_ID_A53_2, | ||
253 | }, | ||
254 | { | ||
255 | .start_resource = 96, | ||
256 | .num_resource = 30, | ||
257 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
258 | RESASG_SUBTYPE_IA_VINT), | ||
259 | .host_id = HOST_ID_A53_3, | ||
260 | }, | ||
261 | { | ||
262 | .start_resource = 126, | ||
263 | .num_resource = 50, | ||
264 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
265 | RESASG_SUBTYPE_IA_VINT), | ||
266 | .host_id = HOST_ID_R5_0, | ||
267 | }, | ||
268 | { | ||
269 | .start_resource = 176, | ||
270 | .num_resource = 50, | ||
271 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
272 | RESASG_SUBTYPE_IA_VINT), | ||
273 | .host_id = HOST_ID_R5_2, | ||
274 | }, | ||
275 | { | ||
276 | .start_resource = 226, | ||
277 | .num_resource = 30, | ||
278 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
279 | RESASG_SUBTYPE_IA_VINT), | ||
280 | .host_id = HOST_ID_ALL, | ||
281 | }, | ||
282 | /* Main NAVSS UDMA Interrupt aggregator Global events */ | ||
283 | { | ||
78 | .start_resource = 16, | 284 | .start_resource = 16, |
79 | .num_resource = 4592, | 285 | .num_resource = 1024, |
80 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, | 286 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, |
81 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 287 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), |
82 | .host_id = HOST_ID_A53_2, | 288 | .host_id = HOST_ID_A53_2, |
83 | }, | 289 | }, |
84 | { | 290 | { |
291 | .start_resource = 1040, | ||
292 | .num_resource = 512, | ||
293 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
294 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
295 | .host_id = HOST_ID_A53_3, | ||
296 | }, | ||
297 | { | ||
298 | .start_resource = 1552, | ||
299 | .num_resource = 512, | ||
300 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
301 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
302 | .host_id = HOST_ID_R5_0, | ||
303 | }, | ||
304 | { | ||
305 | .start_resource = 2064, | ||
306 | .num_resource = 512, | ||
307 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
308 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
309 | .host_id = HOST_ID_R5_2, | ||
310 | }, | ||
311 | { | ||
312 | .start_resource = 2576, | ||
313 | .num_resource = 2032, | ||
314 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMASS_INTA0, | ||
315 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
316 | .host_id = HOST_ID_ALL, | ||
317 | }, | ||
318 | /* MODSS Interrupt aggregator0 Virtual interrupts */ | ||
319 | { | ||
85 | .start_resource = 0, | 320 | .start_resource = 0, |
86 | .num_resource = 64, | 321 | .num_resource = 64, |
87 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, | 322 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA0, |
88 | RESASG_SUBTYPE_IA_VINT), | 323 | RESASG_SUBTYPE_IA_VINT), |
89 | .host_id = HOST_ID_A53_2, | 324 | .host_id = HOST_ID_ALL, |
90 | }, | 325 | }, |
326 | /* MODSS Interrupt aggregator0 Global events */ | ||
91 | { | 327 | { |
92 | .start_resource = 20480, | 328 | .start_resource = 20480, |
93 | .num_resource = 1024, | 329 | .num_resource = 1024, |
94 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, | 330 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA0, |
95 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 331 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), |
96 | .host_id = HOST_ID_A53_2, | 332 | .host_id = HOST_ID_ALL, |
97 | }, | 333 | }, |
334 | /* MODSS Interrupt aggregator1 Virtual interrupts */ | ||
98 | { | 335 | { |
99 | .start_resource = 0, | 336 | .start_resource = 0, |
100 | .num_resource = 64, | 337 | .num_resource = 64, |
101 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, | 338 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA1, |
102 | RESASG_SUBTYPE_IA_VINT), | 339 | RESASG_SUBTYPE_IA_VINT), |
103 | .host_id = HOST_ID_A53_2, | 340 | .host_id = HOST_ID_ALL, |
104 | }, | 341 | }, |
342 | /* MODSS Interrupt aggregator1 Global events */ | ||
105 | { | 343 | { |
106 | .start_resource = 22528, | 344 | .start_resource = 22528, |
107 | .num_resource = 1024, | 345 | .num_resource = 1024, |
108 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, | 346 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_MODSS_INTA1, |
109 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 347 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), |
348 | .host_id = HOST_ID_ALL, | ||
349 | }, | ||
350 | /* Main NAVSS Interrupt Router */ | ||
351 | { | ||
352 | .start_resource = 16, | ||
353 | .num_resource = 64, | ||
354 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0, | ||
355 | RESASG_SUBTYPE_IR_OUTPUT), | ||
110 | .host_id = HOST_ID_A53_2, | 356 | .host_id = HOST_ID_A53_2, |
111 | }, | 357 | }, |
112 | { | 358 | { |
113 | .start_resource = 8, | 359 | .start_resource = 80, |
114 | .num_resource = 248, | 360 | .num_resource = 40, |
115 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | 361 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0, |
116 | RESASG_SUBTYPE_IA_VINT), | 362 | RESASG_SUBTYPE_IR_OUTPUT), |
363 | .host_id = HOST_ID_A53_3, | ||
364 | }, | ||
365 | { | ||
366 | .start_resource = 120, | ||
367 | .num_resource = 4, | ||
368 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0, | ||
369 | RESASG_SUBTYPE_IR_OUTPUT), | ||
117 | .host_id = HOST_ID_R5_0, | 370 | .host_id = HOST_ID_R5_0, |
118 | }, | 371 | }, |
119 | { | 372 | { |
120 | .start_resource = 16392, | 373 | .start_resource = 124, |
121 | .num_resource = 992, | 374 | .num_resource = 4, |
122 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | 375 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0, |
123 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 376 | RESASG_SUBTYPE_IR_OUTPUT), |
377 | .host_id = HOST_ID_R5_2, | ||
378 | }, | ||
379 | { | ||
380 | .start_resource = 128, | ||
381 | .num_resource = 24, | ||
382 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_INTR_ROUTER_0, | ||
383 | RESASG_SUBTYPE_IR_OUTPUT), | ||
384 | .host_id = HOST_ID_ALL, | ||
385 | }, | ||
386 | /* Main NAVSS Non secure proxies */ | ||
387 | { | ||
388 | .start_resource = 1, | ||
389 | .num_resource = 12, | ||
390 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0, | ||
391 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
392 | .host_id = HOST_ID_A53_2, | ||
393 | }, | ||
394 | { | ||
395 | .start_resource = 13, | ||
396 | .num_resource = 4, | ||
397 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0, | ||
398 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
399 | .host_id = HOST_ID_A53_3, | ||
400 | }, | ||
401 | { | ||
402 | .start_resource = 17, | ||
403 | .num_resource = 16, | ||
404 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0, | ||
405 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
124 | .host_id = HOST_ID_R5_0, | 406 | .host_id = HOST_ID_R5_0, |
125 | }, | 407 | }, |
126 | { | 408 | { |
127 | .start_resource = 17384, | 409 | .start_resource = 33, |
128 | .num_resource = 536, | 410 | .num_resource = 16, |
129 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | 411 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0, |
130 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | 412 | RESASG_SUBTYPE_PROXY_PROXIES), |
413 | .host_id = HOST_ID_R5_2, | ||
414 | }, | ||
415 | { | ||
416 | .start_resource = 49, | ||
417 | .num_resource = 15, | ||
418 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_PROXY0, | ||
419 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
420 | .host_id = HOST_ID_ALL, | ||
421 | }, | ||
422 | /* Main NAVSS Ring accelerator Error event config */ | ||
423 | { | ||
424 | .start_resource = 0, | ||
425 | .num_resource = 1, | ||
426 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
427 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
428 | .host_id = HOST_ID_ALL, | ||
429 | }, | ||
430 | /* Main NAVSS Ring accelerator Free rings */ | ||
431 | { | ||
432 | .start_resource = 304, | ||
433 | .num_resource = 100, | ||
434 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
435 | RESASG_SUBTYPE_RA_GP), | ||
436 | .host_id = HOST_ID_A53_2, | ||
437 | }, | ||
438 | { | ||
439 | .start_resource = 404, | ||
440 | .num_resource = 50, | ||
441 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
442 | RESASG_SUBTYPE_RA_GP), | ||
443 | .host_id = HOST_ID_A53_3, | ||
444 | }, | ||
445 | { | ||
446 | .start_resource = 454, | ||
447 | .num_resource = 256, | ||
448 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
449 | RESASG_SUBTYPE_RA_GP), | ||
131 | .host_id = HOST_ID_R5_0, | 450 | .host_id = HOST_ID_R5_0, |
132 | }, | 451 | }, |
133 | { | 452 | { |
134 | .start_resource = 49152, | 453 | .start_resource = 710, |
135 | .num_resource = 1024, | 454 | .num_resource = 32, |
136 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 455 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
137 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | 456 | RESASG_SUBTYPE_RA_GP), |
457 | .host_id = HOST_ID_R5_2, | ||
458 | }, | ||
459 | { | ||
460 | .start_resource = 742, | ||
461 | .num_resource = 26, | ||
462 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
463 | RESASG_SUBTYPE_RA_GP), | ||
464 | .host_id = HOST_ID_ALL, | ||
465 | }, | ||
466 | /* Main NAVSS Rings for Normal capacity Rx channels */ | ||
467 | { | ||
468 | .start_resource = 160, | ||
469 | .num_resource = 12, | ||
470 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
471 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
138 | .host_id = HOST_ID_A53_2, | 472 | .host_id = HOST_ID_A53_2, |
139 | }, | 473 | }, |
140 | { | 474 | { |
141 | .start_resource = 1, | 475 | .start_resource = 172, |
142 | .num_resource = 7, | 476 | .num_resource = 4, |
143 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 477 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
144 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | 478 | RESASG_SUBTYPE_RA_UDMAP_RX), |
479 | .host_id = HOST_ID_R5_0, | ||
480 | }, | ||
481 | { | ||
482 | .start_resource = 172, | ||
483 | .num_resource = 0, | ||
484 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
485 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
486 | .host_id = HOST_ID_A53_3, | ||
487 | }, | ||
488 | { | ||
489 | .start_resource = 176, | ||
490 | .num_resource = 2, | ||
491 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
492 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
493 | .host_id = HOST_ID_R5_2, | ||
494 | }, | ||
495 | { | ||
496 | .start_resource = 178, | ||
497 | .num_resource = 52, | ||
498 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
499 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
145 | .host_id = HOST_ID_A53_2, | 500 | .host_id = HOST_ID_A53_2, |
146 | }, | 501 | }, |
147 | { | 502 | { |
503 | .start_resource = 230, | ||
504 | .num_resource = 8, | ||
505 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
506 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
507 | .host_id = HOST_ID_A53_3, | ||
508 | }, | ||
509 | { | ||
510 | .start_resource = 238, | ||
511 | .num_resource = 32, | ||
512 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
513 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
514 | .host_id = HOST_ID_R5_0, | ||
515 | }, | ||
516 | { | ||
517 | .start_resource = 270, | ||
518 | .num_resource = 14, | ||
519 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
520 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
521 | .host_id = HOST_ID_R5_2, | ||
522 | }, | ||
523 | { | ||
524 | .start_resource = 284, | ||
525 | .num_resource = 18, | ||
526 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
527 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
528 | .host_id = HOST_ID_ALL, | ||
529 | }, | ||
530 | /* Main NAVSS Rings for Normal capacity Tx channels */ | ||
531 | { | ||
148 | .start_resource = 8, | 532 | .start_resource = 8, |
149 | .num_resource = 112, | 533 | .num_resource = 12, |
150 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 534 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
151 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | 535 | RESASG_SUBTYPE_RA_UDMAP_TX), |
152 | .host_id = HOST_ID_A53_2, | 536 | .host_id = HOST_ID_A53_2, |
153 | }, | 537 | }, |
154 | { | 538 | { |
155 | .start_resource = 120, | 539 | .start_resource = 20, |
540 | .num_resource = 4, | ||
541 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
542 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
543 | .host_id = HOST_ID_R5_0, | ||
544 | }, | ||
545 | { | ||
546 | .start_resource = 20, | ||
547 | .num_resource = 0, | ||
548 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
549 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
550 | .host_id = HOST_ID_A53_3, | ||
551 | }, | ||
552 | { | ||
553 | .start_resource = 24, | ||
554 | .num_resource = 2, | ||
555 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
556 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
557 | .host_id = HOST_ID_R5_2, | ||
558 | }, | ||
559 | { | ||
560 | .start_resource = 26, | ||
561 | .num_resource = 38, | ||
562 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
563 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
564 | .host_id = HOST_ID_A53_2, | ||
565 | }, | ||
566 | { | ||
567 | .start_resource = 64, | ||
568 | .num_resource = 8, | ||
569 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
570 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
571 | .host_id = HOST_ID_A53_3, | ||
572 | }, | ||
573 | { | ||
574 | .start_resource = 72, | ||
156 | .num_resource = 32, | 575 | .num_resource = 32, |
157 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 576 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
158 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | 577 | RESASG_SUBTYPE_RA_UDMAP_TX), |
578 | .host_id = HOST_ID_R5_0, | ||
579 | }, | ||
580 | { | ||
581 | .start_resource = 104, | ||
582 | .num_resource = 14, | ||
583 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
584 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
585 | .host_id = HOST_ID_R5_2, | ||
586 | }, | ||
587 | { | ||
588 | .start_resource = 118, | ||
589 | .num_resource = 2, | ||
590 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
591 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
592 | .host_id = HOST_ID_ALL, | ||
593 | }, | ||
594 | /* Main NAVSS Rings for extended Tx channels */ | ||
595 | { | ||
596 | .start_resource = 120, | ||
597 | .num_resource = 4, | ||
598 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
599 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
600 | .host_id = HOST_ID_A53_2, | ||
601 | }, | ||
602 | { | ||
603 | .start_resource = 124, | ||
604 | .num_resource = 4, | ||
605 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
606 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
607 | .host_id = HOST_ID_A53_3, | ||
608 | }, | ||
609 | { | ||
610 | .start_resource = 128, | ||
611 | .num_resource = 12, | ||
612 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
613 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
614 | .host_id = HOST_ID_R5_0, | ||
615 | }, | ||
616 | { | ||
617 | .start_resource = 140, | ||
618 | .num_resource = 12, | ||
619 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
620 | RESASG_SUBTYPE_RA_UDMAP_TX_EXT), | ||
621 | .host_id = HOST_ID_R5_2, | ||
622 | }, | ||
623 | /* Main NAVSS Rings for High capacity Rx channels */ | ||
624 | { | ||
625 | .start_resource = 154, | ||
626 | .num_resource = 0, | ||
627 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
628 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
629 | .host_id = HOST_ID_R5_0, | ||
630 | }, | ||
631 | { | ||
632 | .start_resource = 154, | ||
633 | .num_resource = 0, | ||
634 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
635 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
636 | .host_id = HOST_ID_R5_2, | ||
637 | }, | ||
638 | { | ||
639 | .start_resource = 154, | ||
640 | .num_resource = 0, | ||
641 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
642 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
643 | .host_id = HOST_ID_A53_2, | ||
644 | }, | ||
645 | { | ||
646 | .start_resource = 154, | ||
647 | .num_resource = 2, | ||
648 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
649 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
159 | .host_id = HOST_ID_A53_2, | 650 | .host_id = HOST_ID_A53_2, |
160 | }, | 651 | }, |
161 | { | 652 | { |
653 | .start_resource = 156, | ||
654 | .num_resource = 2, | ||
655 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
656 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
657 | .host_id = HOST_ID_R5_0, | ||
658 | }, | ||
659 | { | ||
660 | .start_resource = 158, | ||
661 | .num_resource = 2, | ||
662 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
663 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
664 | .host_id = HOST_ID_R5_2, | ||
665 | }, | ||
666 | /* Main NAVSS Rings for High capacity Tx channels */ | ||
667 | { | ||
668 | .start_resource = 1, | ||
669 | .num_resource = 0, | ||
670 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
671 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
672 | .host_id = HOST_ID_R5_0, | ||
673 | }, | ||
674 | { | ||
675 | .start_resource = 1, | ||
676 | .num_resource = 0, | ||
677 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
678 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
679 | .host_id = HOST_ID_R5_2, | ||
680 | }, | ||
681 | { | ||
682 | .start_resource = 1, | ||
683 | .num_resource = 0, | ||
684 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
685 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
686 | .host_id = HOST_ID_A53_2, | ||
687 | }, | ||
688 | { | ||
689 | .start_resource = 1, | ||
690 | .num_resource = 3, | ||
691 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
692 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
693 | .host_id = HOST_ID_A53_2, | ||
694 | }, | ||
695 | { | ||
696 | .start_resource = 4, | ||
697 | .num_resource = 2, | ||
698 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
699 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
700 | .host_id = HOST_ID_R5_0, | ||
701 | }, | ||
702 | { | ||
703 | .start_resource = 6, | ||
704 | .num_resource = 2, | ||
705 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
706 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
707 | .host_id = HOST_ID_R5_2, | ||
708 | }, | ||
709 | /* Main NAVSS Ring accelerator virt_id range */ | ||
710 | { | ||
162 | .start_resource = 2, | 711 | .start_resource = 2, |
163 | .num_resource = 6, | 712 | .num_resource = 1, |
164 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 713 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
165 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | 714 | RESASG_SUBTYPE_RA_VIRTID), |
166 | .host_id = HOST_ID_A53_2, | 715 | .host_id = HOST_ID_A53_2, |
167 | }, | 716 | }, |
168 | { | 717 | { |
169 | .start_resource = 8, | 718 | .start_resource = 3, |
170 | .num_resource = 142, | 719 | .num_resource = 1, |
171 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 720 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, |
172 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | 721 | RESASG_SUBTYPE_RA_VIRTID), |
722 | .host_id = HOST_ID_A53_3, | ||
723 | }, | ||
724 | /* Main NAVSS Ring monitors */ | ||
725 | { | ||
726 | .start_resource = 0, | ||
727 | .num_resource = 8, | ||
728 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
729 | RESASG_SUBTYPE_RA_MONITORS), | ||
173 | .host_id = HOST_ID_A53_2, | 730 | .host_id = HOST_ID_A53_2, |
174 | }, | 731 | }, |
175 | { | 732 | { |
733 | .start_resource = 8, | ||
734 | .num_resource = 4, | ||
735 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
736 | RESASG_SUBTYPE_RA_MONITORS), | ||
737 | .host_id = HOST_ID_A53_3, | ||
738 | }, | ||
739 | { | ||
740 | .start_resource = 12, | ||
741 | .num_resource = 8, | ||
742 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
743 | RESASG_SUBTYPE_RA_MONITORS), | ||
744 | .host_id = HOST_ID_R5_0, | ||
745 | }, | ||
746 | { | ||
747 | .start_resource = 20, | ||
748 | .num_resource = 8, | ||
749 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
750 | RESASG_SUBTYPE_RA_MONITORS), | ||
751 | .host_id = HOST_ID_R5_2, | ||
752 | }, | ||
753 | { | ||
754 | .start_resource = 28, | ||
755 | .num_resource = 4, | ||
756 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_RINGACC0, | ||
757 | RESASG_SUBTYPE_RA_MONITORS), | ||
758 | .host_id = HOST_ID_ALL, | ||
759 | }, | ||
760 | /* Main NAVSS UDMA Rx Free flows */ | ||
761 | { | ||
176 | .start_resource = 150, | 762 | .start_resource = 150, |
177 | .num_resource = 150, | 763 | .num_resource = 64, |
178 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 764 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
179 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 765 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), |
180 | .host_id = HOST_ID_A53_2, | 766 | .host_id = HOST_ID_A53_2, |
181 | }, | 767 | }, |
182 | { | 768 | { |
769 | .start_resource = 214, | ||
770 | .num_resource = 8, | ||
771 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
772 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
773 | .host_id = HOST_ID_A53_3, | ||
774 | }, | ||
775 | { | ||
776 | .start_resource = 222, | ||
777 | .num_resource = 64, | ||
778 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
779 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
780 | .host_id = HOST_ID_R5_0, | ||
781 | }, | ||
782 | { | ||
783 | .start_resource = 286, | ||
784 | .num_resource = 8, | ||
785 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
786 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
787 | .host_id = HOST_ID_R5_2, | ||
788 | }, | ||
789 | { | ||
790 | .start_resource = 294, | ||
791 | .num_resource = 6, | ||
792 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
793 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
794 | .host_id = HOST_ID_ALL, | ||
795 | }, | ||
796 | /* Main NAVSS UDMA invalid flow event config */ | ||
797 | { | ||
183 | .start_resource = 0, | 798 | .start_resource = 0, |
184 | .num_resource = 1, | 799 | .num_resource = 1, |
185 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, | 800 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
186 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | 801 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), |
187 | .host_id = HOST_ID_A53_2, | 802 | .host_id = HOST_ID_ALL, |
188 | }, | 803 | }, |
804 | /* Main NAVSS UDMA global event trigger */ | ||
189 | { | 805 | { |
190 | .start_resource = 56320, | 806 | .start_resource = 49152, |
191 | .num_resource = 256, | 807 | .num_resource = 1024, |
192 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 808 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
193 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | 809 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), |
194 | .host_id = HOST_ID_A53_2, | 810 | .host_id = HOST_ID_ALL, |
195 | }, | 811 | }, |
812 | /* Main NAVSS UDMA global config */ | ||
196 | { | 813 | { |
197 | .start_resource = 0, | 814 | .start_resource = 0, |
815 | .num_resource = 1, | ||
816 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
817 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), | ||
818 | .host_id = HOST_ID_ALL, | ||
819 | }, | ||
820 | /* Main NAVSS UDMA Normal capacity Rx channels */ | ||
821 | { | ||
822 | .start_resource = 8, | ||
823 | .num_resource = 12, | ||
824 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
825 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
826 | .host_id = HOST_ID_A53_2, | ||
827 | }, | ||
828 | { | ||
829 | .start_resource = 20, | ||
830 | .num_resource = 4, | ||
831 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
832 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
833 | .host_id = HOST_ID_R5_0, | ||
834 | }, | ||
835 | { | ||
836 | .start_resource = 20, | ||
837 | .num_resource = 0, | ||
838 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
839 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
840 | .host_id = HOST_ID_A53_3, | ||
841 | }, | ||
842 | { | ||
843 | .start_resource = 24, | ||
198 | .num_resource = 2, | 844 | .num_resource = 2, |
199 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 845 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
200 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | 846 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
847 | .host_id = HOST_ID_R5_2, | ||
848 | }, | ||
849 | { | ||
850 | .start_resource = 26, | ||
851 | .num_resource = 52, | ||
852 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
853 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
854 | .host_id = HOST_ID_A53_2, | ||
855 | }, | ||
856 | { | ||
857 | .start_resource = 78, | ||
858 | .num_resource = 8, | ||
859 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
860 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
861 | .host_id = HOST_ID_A53_3, | ||
862 | }, | ||
863 | { | ||
864 | .start_resource = 86, | ||
865 | .num_resource = 32, | ||
866 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
867 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
868 | .host_id = HOST_ID_R5_0, | ||
869 | }, | ||
870 | { | ||
871 | .start_resource = 118, | ||
872 | .num_resource = 14, | ||
873 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
874 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
875 | .host_id = HOST_ID_R5_2, | ||
876 | }, | ||
877 | { | ||
878 | .start_resource = 132, | ||
879 | .num_resource = 18, | ||
880 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
881 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
882 | .host_id = HOST_ID_ALL, | ||
883 | }, | ||
884 | /* Main NAVSS UDMA High capacity Rx channels */ | ||
885 | { | ||
886 | .start_resource = 2, | ||
887 | .num_resource = 0, | ||
888 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
889 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
890 | .host_id = HOST_ID_R5_0, | ||
891 | }, | ||
892 | { | ||
893 | .start_resource = 2, | ||
894 | .num_resource = 0, | ||
895 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
896 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
897 | .host_id = HOST_ID_R5_2, | ||
898 | }, | ||
899 | { | ||
900 | .start_resource = 2, | ||
901 | .num_resource = 0, | ||
902 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
903 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
201 | .host_id = HOST_ID_A53_2, | 904 | .host_id = HOST_ID_A53_2, |
202 | }, | 905 | }, |
203 | { | 906 | { |
204 | .start_resource = 2, | 907 | .start_resource = 2, |
205 | .num_resource = 46, | 908 | .num_resource = 2, |
206 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 909 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
207 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | 910 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), |
208 | .host_id = HOST_ID_A53_2, | 911 | .host_id = HOST_ID_A53_2, |
209 | }, | 912 | }, |
210 | { | 913 | { |
211 | .start_resource = 0, | 914 | .start_resource = 4, |
915 | .num_resource = 2, | ||
916 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
917 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | ||
918 | .host_id = HOST_ID_R5_0, | ||
919 | }, | ||
920 | { | ||
921 | .start_resource = 6, | ||
212 | .num_resource = 2, | 922 | .num_resource = 2, |
213 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 923 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
214 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), | 924 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), |
925 | .host_id = HOST_ID_R5_2, | ||
926 | }, | ||
927 | /* Main NAVSS UDMA Normal capacity Tx channels */ | ||
928 | { | ||
929 | .start_resource = 8, | ||
930 | .num_resource = 12, | ||
931 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
932 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
215 | .host_id = HOST_ID_A53_2, | 933 | .host_id = HOST_ID_A53_2, |
216 | }, | 934 | }, |
217 | { | 935 | { |
218 | .start_resource = 2, | 936 | .start_resource = 20, |
219 | .num_resource = 46, | 937 | .num_resource = 4, |
220 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 938 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
221 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | 939 | RESASG_SUBTYPE_UDMAP_TX_CHAN), |
940 | .host_id = HOST_ID_R5_0, | ||
941 | }, | ||
942 | { | ||
943 | .start_resource = 20, | ||
944 | .num_resource = 0, | ||
945 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
946 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
947 | .host_id = HOST_ID_A53_3, | ||
948 | }, | ||
949 | { | ||
950 | .start_resource = 24, | ||
951 | .num_resource = 2, | ||
952 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
953 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
954 | .host_id = HOST_ID_R5_2, | ||
955 | }, | ||
956 | { | ||
957 | .start_resource = 26, | ||
958 | .num_resource = 38, | ||
959 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
960 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
222 | .host_id = HOST_ID_A53_2, | 961 | .host_id = HOST_ID_A53_2, |
223 | }, | 962 | }, |
224 | { | 963 | { |
225 | .start_resource = 48, | 964 | .start_resource = 64, |
226 | .num_resource = 48, | 965 | .num_resource = 8, |
227 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 966 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
228 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 967 | RESASG_SUBTYPE_UDMAP_TX_CHAN), |
968 | .host_id = HOST_ID_A53_3, | ||
969 | }, | ||
970 | { | ||
971 | .start_resource = 72, | ||
972 | .num_resource = 32, | ||
973 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
974 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
975 | .host_id = HOST_ID_R5_0, | ||
976 | }, | ||
977 | { | ||
978 | .start_resource = 104, | ||
979 | .num_resource = 14, | ||
980 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
981 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
982 | .host_id = HOST_ID_R5_2, | ||
983 | }, | ||
984 | { | ||
985 | .start_resource = 118, | ||
986 | .num_resource = 2, | ||
987 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
988 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
989 | .host_id = HOST_ID_ALL, | ||
990 | }, | ||
991 | /* Main NAVSS UDMA extended Tx channels */ | ||
992 | { | ||
993 | .start_resource = 120, | ||
994 | .num_resource = 4, | ||
995 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
996 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), | ||
229 | .host_id = HOST_ID_A53_2, | 997 | .host_id = HOST_ID_A53_2, |
230 | }, | 998 | }, |
231 | { | 999 | { |
232 | .start_resource = 2, | 1000 | .start_resource = 124, |
233 | .num_resource = 46, | 1001 | .num_resource = 4, |
234 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 1002 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
235 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | 1003 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), |
236 | .host_id = HOST_ID_R5_1, | 1004 | .host_id = HOST_ID_A53_3, |
237 | }, | 1005 | }, |
238 | { | 1006 | { |
239 | .start_resource = 2, | 1007 | .start_resource = 128, |
240 | .num_resource = 46, | 1008 | .num_resource = 12, |
241 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 1009 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
242 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | 1010 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), |
243 | .host_id = HOST_ID_R5_1, | 1011 | .host_id = HOST_ID_R5_0, |
244 | }, | 1012 | }, |
245 | { | 1013 | { |
246 | .start_resource = 48, | 1014 | .start_resource = 140, |
247 | .num_resource = 48, | 1015 | .num_resource = 12, |
248 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 1016 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
249 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | 1017 | RESASG_SUBTYPE_UDMAP_TX_ECHAN), |
250 | .host_id = HOST_ID_R5_1, | 1018 | .host_id = HOST_ID_R5_2, |
251 | }, | 1019 | }, |
1020 | /* Main NAVSS UDMA High capacity Tx channels */ | ||
252 | { | 1021 | { |
253 | .start_resource = 0, | 1022 | .start_resource = 1, |
254 | .num_resource = 1, | 1023 | .num_resource = 0, |
255 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, | 1024 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
256 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), | 1025 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), |
1026 | .host_id = HOST_ID_R5_0, | ||
1027 | }, | ||
1028 | { | ||
1029 | .start_resource = 1, | ||
1030 | .num_resource = 0, | ||
1031 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
1032 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1033 | .host_id = HOST_ID_R5_2, | ||
1034 | }, | ||
1035 | { | ||
1036 | .start_resource = 1, | ||
1037 | .num_resource = 0, | ||
1038 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
1039 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
257 | .host_id = HOST_ID_A53_2, | 1040 | .host_id = HOST_ID_A53_2, |
258 | }, | 1041 | }, |
259 | { | 1042 | { |
260 | .start_resource = 1, | 1043 | .start_resource = 1, |
261 | .num_resource = 7, | 1044 | .num_resource = 3, |
262 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1045 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, |
263 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | 1046 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), |
264 | .host_id = HOST_ID_A53_2, | 1047 | .host_id = HOST_ID_A53_2, |
265 | }, | 1048 | }, |
266 | { | 1049 | { |
1050 | .start_resource = 4, | ||
1051 | .num_resource = 2, | ||
1052 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
1053 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1054 | .host_id = HOST_ID_R5_0, | ||
1055 | }, | ||
1056 | { | ||
1057 | .start_resource = 6, | ||
1058 | .num_resource = 2, | ||
1059 | .type = RESASG_UTYPE (AM6_DEV_NAVSS0_UDMAP0, | ||
1060 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
1061 | .host_id = HOST_ID_R5_2, | ||
1062 | }, | ||
1063 | /* MCU NAVSS Interrupt aggregator Virtual interrupts */ | ||
1064 | { | ||
267 | .start_resource = 8, | 1065 | .start_resource = 8, |
268 | .num_resource = 112, | 1066 | .num_resource = 80, |
269 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1067 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
270 | RESASG_SUBTYPE_RA_UDMAP_TX), | 1068 | RESASG_SUBTYPE_IA_VINT), |
271 | .host_id = HOST_ID_A53_2, | 1069 | .host_id = HOST_ID_A53_2, |
272 | }, | 1070 | }, |
273 | { | 1071 | { |
274 | .start_resource = 154, | 1072 | .start_resource = 88, |
275 | .num_resource = 6, | 1073 | .num_resource = 30, |
276 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1074 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
277 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | 1075 | RESASG_SUBTYPE_IA_VINT), |
1076 | .host_id = HOST_ID_A53_3, | ||
1077 | }, | ||
1078 | { | ||
1079 | .start_resource = 118, | ||
1080 | .num_resource = 50, | ||
1081 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1082 | RESASG_SUBTYPE_IA_VINT), | ||
1083 | .host_id = HOST_ID_R5_0, | ||
1084 | }, | ||
1085 | { | ||
1086 | .start_resource = 168, | ||
1087 | .num_resource = 50, | ||
1088 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1089 | RESASG_SUBTYPE_IA_VINT), | ||
1090 | .host_id = HOST_ID_R5_2, | ||
1091 | }, | ||
1092 | { | ||
1093 | .start_resource = 218, | ||
1094 | .num_resource = 38, | ||
1095 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1096 | RESASG_SUBTYPE_IA_VINT), | ||
1097 | .host_id = HOST_ID_ALL, | ||
1098 | }, | ||
1099 | /* MCU NAVSS Interrupt aggregator Global events */ | ||
1100 | { | ||
1101 | .start_resource = 16392, | ||
1102 | .num_resource = 512, | ||
1103 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1104 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
278 | .host_id = HOST_ID_A53_2, | 1105 | .host_id = HOST_ID_A53_2, |
279 | }, | 1106 | }, |
280 | { | 1107 | { |
281 | .start_resource = 160, | 1108 | .start_resource = 16904, |
282 | .num_resource = 142, | 1109 | .num_resource = 128, |
283 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1110 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, |
284 | RESASG_SUBTYPE_RA_UDMAP_RX), | 1111 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), |
1112 | .host_id = HOST_ID_A53_3, | ||
1113 | }, | ||
1114 | { | ||
1115 | .start_resource = 17032, | ||
1116 | .num_resource = 256, | ||
1117 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1118 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1119 | .host_id = HOST_ID_R5_0, | ||
1120 | }, | ||
1121 | { | ||
1122 | .start_resource = 17288, | ||
1123 | .num_resource = 256, | ||
1124 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1125 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1126 | .host_id = HOST_ID_R5_2, | ||
1127 | }, | ||
1128 | { | ||
1129 | .start_resource = 17544, | ||
1130 | .num_resource = 376, | ||
1131 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, | ||
1132 | RESASG_SUBTYPE_GLOBAL_EVENT_SEVT), | ||
1133 | .host_id = HOST_ID_ALL, | ||
1134 | }, | ||
1135 | /* MCU NAVSS Interrupt router */ | ||
1136 | { | ||
1137 | .start_resource = 4, | ||
1138 | .num_resource = 28, | ||
1139 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, | ||
1140 | RESASG_SUBTYPE_IR_OUTPUT), | ||
1141 | .host_id = HOST_ID_R5_0, | ||
1142 | }, | ||
1143 | { | ||
1144 | .start_resource = 36, | ||
1145 | .num_resource = 28, | ||
1146 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, | ||
1147 | RESASG_SUBTYPE_IR_OUTPUT), | ||
1148 | .host_id = HOST_ID_R5_2, | ||
1149 | }, | ||
1150 | /* MCU NAVSS Non secure proxies */ | ||
1151 | { | ||
1152 | .start_resource = 0, | ||
1153 | .num_resource = 12, | ||
1154 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0, | ||
1155 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
285 | .host_id = HOST_ID_A53_2, | 1156 | .host_id = HOST_ID_A53_2, |
286 | }, | 1157 | }, |
287 | { | 1158 | { |
288 | .start_resource = 304, | 1159 | .start_resource = 12, |
289 | .num_resource = 464, | 1160 | .num_resource = 4, |
290 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1161 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0, |
291 | RESASG_SUBTYPE_RA_GP), | 1162 | RESASG_SUBTYPE_PROXY_PROXIES), |
1163 | .host_id = HOST_ID_A53_3, | ||
1164 | }, | ||
1165 | { | ||
1166 | .start_resource = 16, | ||
1167 | .num_resource = 24, | ||
1168 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0, | ||
1169 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1170 | .host_id = HOST_ID_R5_0, | ||
1171 | }, | ||
1172 | { | ||
1173 | .start_resource = 40, | ||
1174 | .num_resource = 24, | ||
1175 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_PROXY0, | ||
1176 | RESASG_SUBTYPE_PROXY_PROXIES), | ||
1177 | .host_id = HOST_ID_R5_2, | ||
1178 | }, | ||
1179 | /* MCU NAVSS UDMA Rx free flows */ | ||
1180 | { | ||
1181 | .start_resource = 48, | ||
1182 | .num_resource = 16, | ||
1183 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1184 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
292 | .host_id = HOST_ID_A53_2, | 1185 | .host_id = HOST_ID_A53_2, |
293 | }, | 1186 | }, |
294 | { | 1187 | { |
1188 | .start_resource = 64, | ||
1189 | .num_resource = 4, | ||
1190 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1191 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1192 | .host_id = HOST_ID_A53_3, | ||
1193 | }, | ||
1194 | { | ||
1195 | .start_resource = 68, | ||
1196 | .num_resource = 16, | ||
1197 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1198 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1199 | .host_id = HOST_ID_R5_0, | ||
1200 | }, | ||
1201 | { | ||
1202 | .start_resource = 84, | ||
1203 | .num_resource = 8, | ||
1204 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1205 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1206 | .host_id = HOST_ID_R5_2, | ||
1207 | }, | ||
1208 | { | ||
1209 | .start_resource = 92, | ||
1210 | .num_resource = 4, | ||
1211 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1212 | RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON), | ||
1213 | .host_id = HOST_ID_ALL, | ||
1214 | }, | ||
1215 | /* MCU NAVSS invalid flow event config */ | ||
1216 | { | ||
295 | .start_resource = 0, | 1217 | .start_resource = 0, |
296 | .num_resource = 1, | 1218 | .num_resource = 1, |
297 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, | 1219 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
298 | RESASG_SUBTYPE_RA_ERROR_OES), | 1220 | RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES), |
299 | .host_id = HOST_ID_A53_2, | 1221 | .host_id = HOST_ID_ALL, |
1222 | }, | ||
1223 | /* MCU NAVSS UDMA global event trigger */ | ||
1224 | { | ||
1225 | .start_resource = 56320, | ||
1226 | .num_resource = 256, | ||
1227 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1228 | RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER), | ||
1229 | .host_id = HOST_ID_ALL, | ||
300 | }, | 1230 | }, |
1231 | /* MCU NAVSS UDMA global config */ | ||
301 | { | 1232 | { |
302 | .start_resource = 0, | 1233 | .start_resource = 0, |
303 | .num_resource = 2, | 1234 | .num_resource = 1, |
304 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1235 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
305 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | 1236 | RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG), |
306 | .host_id = HOST_ID_A53_2, | 1237 | .host_id = HOST_ID_ALL, |
307 | }, | 1238 | }, |
1239 | /* MCU NAVSS UDMA Normal capacity Rx channels */ | ||
308 | { | 1240 | { |
309 | .start_resource = 2, | 1241 | .start_resource = 2, |
310 | .num_resource = 46, | 1242 | .num_resource = 2, |
311 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1243 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
312 | RESASG_SUBTYPE_RA_UDMAP_TX), | 1244 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
313 | .host_id = HOST_ID_A53_2, | 1245 | .host_id = HOST_ID_A53_2, |
314 | }, | 1246 | }, |
315 | { | 1247 | { |
316 | .start_resource = 48, | 1248 | .start_resource = 4, |
1249 | .num_resource = 4, | ||
1250 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1251 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1252 | .host_id = HOST_ID_R5_0, | ||
1253 | }, | ||
1254 | { | ||
1255 | .start_resource = 4, | ||
1256 | .num_resource = 0, | ||
1257 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1258 | RESASG_SUBTYPE_UDMAP_RX_CHAN), | ||
1259 | .host_id = HOST_ID_A53_3, | ||
1260 | }, | ||
1261 | { | ||
1262 | .start_resource = 8, | ||
317 | .num_resource = 2, | 1263 | .num_resource = 2, |
318 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1264 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
319 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | 1265 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
320 | .host_id = HOST_ID_A53_2, | 1266 | .host_id = HOST_ID_R5_2, |
321 | }, | 1267 | }, |
322 | { | 1268 | { |
323 | .start_resource = 50, | 1269 | .start_resource = 10, |
324 | .num_resource = 46, | 1270 | .num_resource = 12, |
325 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1271 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
326 | RESASG_SUBTYPE_RA_UDMAP_RX), | 1272 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
327 | .host_id = HOST_ID_A53_2, | 1273 | .host_id = HOST_ID_A53_2, |
328 | }, | 1274 | }, |
329 | { | 1275 | { |
330 | .start_resource = 96, | 1276 | .start_resource = 22, |
331 | .num_resource = 160, | 1277 | .num_resource = 4, |
332 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1278 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
333 | RESASG_SUBTYPE_RA_GP), | 1279 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
334 | .host_id = HOST_ID_A53_2, | 1280 | .host_id = HOST_ID_A53_3, |
335 | }, | 1281 | }, |
336 | { | 1282 | { |
337 | .start_resource = 2, | 1283 | .start_resource = 26, |
338 | .num_resource = 46, | 1284 | .num_resource = 10, |
339 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1285 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
340 | RESASG_SUBTYPE_RA_UDMAP_TX), | 1286 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
341 | .host_id = HOST_ID_R5_1, | 1287 | .host_id = HOST_ID_R5_0, |
342 | }, | 1288 | }, |
343 | { | 1289 | { |
344 | .start_resource = 50, | 1290 | .start_resource = 36, |
345 | .num_resource = 46, | 1291 | .num_resource = 12, |
346 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1292 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
347 | RESASG_SUBTYPE_RA_UDMAP_RX), | 1293 | RESASG_SUBTYPE_UDMAP_RX_CHAN), |
348 | .host_id = HOST_ID_R5_1, | 1294 | .host_id = HOST_ID_R5_2, |
349 | }, | 1295 | }, |
1296 | /* MCU NAVSS UDMA High capacity Rx channels */ | ||
350 | { | 1297 | { |
351 | .start_resource = 96, | 1298 | .start_resource = 0, |
352 | .num_resource = 160, | 1299 | .num_resource = 0, |
353 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1300 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
354 | RESASG_SUBTYPE_RA_GP), | 1301 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), |
355 | .host_id = HOST_ID_R5_1, | 1302 | .host_id = HOST_ID_R5_0, |
356 | }, | 1303 | }, |
357 | { | 1304 | { |
358 | .start_resource = 0, | 1305 | .start_resource = 0, |
359 | .num_resource = 1, | 1306 | .num_resource = 2, |
360 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, | 1307 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
361 | RESASG_SUBTYPE_RA_ERROR_OES), | 1308 | RESASG_SUBTYPE_UDMAP_RX_HCHAN), |
1309 | .host_id = HOST_ID_R5_0, | ||
1310 | }, | ||
1311 | /* MCU NAVSS UDMA Normal capacity Tx channels */ | ||
1312 | { | ||
1313 | .start_resource = 2, | ||
1314 | .num_resource = 2, | ||
1315 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1316 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
362 | .host_id = HOST_ID_A53_2, | 1317 | .host_id = HOST_ID_A53_2, |
363 | }, | 1318 | }, |
364 | { | 1319 | { |
365 | .type = RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1320 | .start_resource = 4, |
366 | .start_resource = 0, | 1321 | .num_resource = 4, |
367 | .num_resource = 32, | 1322 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
1323 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1324 | .host_id = HOST_ID_R5_0, | ||
1325 | }, | ||
1326 | { | ||
1327 | .start_resource = 4, | ||
1328 | .num_resource = 0, | ||
1329 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1330 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1331 | .host_id = HOST_ID_A53_3, | ||
1332 | }, | ||
1333 | { | ||
1334 | .start_resource = 8, | ||
1335 | .num_resource = 2, | ||
1336 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1337 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1338 | .host_id = HOST_ID_R5_2, | ||
1339 | }, | ||
1340 | { | ||
1341 | .start_resource = 10, | ||
1342 | .num_resource = 12, | ||
1343 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1344 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
368 | .host_id = HOST_ID_A53_2, | 1345 | .host_id = HOST_ID_A53_2, |
369 | }, | 1346 | }, |
370 | /* Main 2 MCU level IRQ IR */ | ||
371 | { | 1347 | { |
372 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1348 | .start_resource = 22, |
373 | .start_resource = 0, | 1349 | .num_resource = 4, |
374 | .num_resource = 32, | 1350 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
1351 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
1352 | .host_id = HOST_ID_A53_3, | ||
1353 | }, | ||
1354 | { | ||
1355 | .start_resource = 26, | ||
1356 | .num_resource = 10, | ||
1357 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1358 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
375 | .host_id = HOST_ID_R5_0, | 1359 | .host_id = HOST_ID_R5_0, |
376 | }, | 1360 | }, |
377 | { | 1361 | { |
378 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1362 | .start_resource = 36, |
379 | .start_resource = 32, | 1363 | .num_resource = 12, |
380 | .num_resource = 32, | 1364 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
1365 | RESASG_SUBTYPE_UDMAP_TX_CHAN), | ||
381 | .host_id = HOST_ID_R5_2, | 1366 | .host_id = HOST_ID_R5_2, |
382 | }, | 1367 | }, |
383 | /* Main 2 MCU Pulse IRQ IR */ | 1368 | /* MCU NAVSS UDMA High capacity Tx channels */ |
384 | { | 1369 | { |
385 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | ||
386 | .start_resource = 0, | 1370 | .start_resource = 0, |
387 | .num_resource = 24, | 1371 | .num_resource = 0, |
1372 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, | ||
1373 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), | ||
388 | .host_id = HOST_ID_R5_0, | 1374 | .host_id = HOST_ID_R5_0, |
389 | }, | 1375 | }, |
390 | { | 1376 | { |
391 | .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1377 | .start_resource = 0, |
392 | .start_resource = 24, | 1378 | .num_resource = 2, |
393 | .num_resource = 24, | 1379 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_UDMAP0, |
394 | .host_id = HOST_ID_R5_2, | 1380 | RESASG_SUBTYPE_UDMAP_TX_HCHAN), |
1381 | .host_id = HOST_ID_R5_0, | ||
395 | }, | 1382 | }, |
1383 | /* MCU NAVSS Ring accelerator error event config */ | ||
396 | { | 1384 | { |
397 | .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | ||
398 | .start_resource = 0, | 1385 | .start_resource = 0, |
1386 | .num_resource = 1, | ||
1387 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1388 | RESASG_SUBTYPE_RA_ERROR_OES), | ||
1389 | .host_id = HOST_ID_ALL, | ||
1390 | }, | ||
1391 | /* MCU NAVSS Ring accelerator Free rings */ | ||
1392 | { | ||
1393 | .start_resource = 96, | ||
399 | .num_resource = 32, | 1394 | .num_resource = 32, |
1395 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1396 | RESASG_SUBTYPE_RA_GP), | ||
400 | .host_id = HOST_ID_A53_2, | 1397 | .host_id = HOST_ID_A53_2, |
401 | }, | 1398 | }, |
402 | { | 1399 | { |
403 | .type = RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1400 | .start_resource = 128, |
404 | .start_resource = 0, | 1401 | .num_resource = 8, |
405 | .num_resource = 40, | 1402 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1403 | RESASG_SUBTYPE_RA_GP), | ||
1404 | .host_id = HOST_ID_A53_3, | ||
1405 | }, | ||
1406 | { | ||
1407 | .start_resource = 136, | ||
1408 | .num_resource = 60, | ||
1409 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1410 | RESASG_SUBTYPE_RA_GP), | ||
1411 | .host_id = HOST_ID_R5_0, | ||
1412 | }, | ||
1413 | { | ||
1414 | .start_resource = 196, | ||
1415 | .num_resource = 60, | ||
1416 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1417 | RESASG_SUBTYPE_RA_GP), | ||
1418 | .host_id = HOST_ID_R5_2, | ||
1419 | }, | ||
1420 | /* MCU NAVSS Rings for Normal capacity Rx channels */ | ||
1421 | { | ||
1422 | .start_resource = 50, | ||
1423 | .num_resource = 2, | ||
1424 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1425 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
406 | .host_id = HOST_ID_A53_2, | 1426 | .host_id = HOST_ID_A53_2, |
407 | }, | 1427 | }, |
408 | { | 1428 | { |
409 | .type = RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT), | 1429 | .start_resource = 52, |
410 | .start_resource = 0, | 1430 | .num_resource = 4, |
411 | .num_resource = 16, | 1431 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1432 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1433 | .host_id = HOST_ID_R5_0, | ||
1434 | }, | ||
1435 | { | ||
1436 | .start_resource = 52, | ||
1437 | .num_resource = 0, | ||
1438 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1439 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1440 | .host_id = HOST_ID_A53_3, | ||
1441 | }, | ||
1442 | { | ||
1443 | .start_resource = 56, | ||
1444 | .num_resource = 2, | ||
1445 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1446 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1447 | .host_id = HOST_ID_R5_2, | ||
1448 | }, | ||
1449 | { | ||
1450 | .start_resource = 58, | ||
1451 | .num_resource = 12, | ||
1452 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1453 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
412 | .host_id = HOST_ID_A53_2, | 1454 | .host_id = HOST_ID_A53_2, |
413 | }, | 1455 | }, |
414 | { | 1456 | { |
415 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1457 | .start_resource = 70, |
416 | .start_resource = 16, | 1458 | .num_resource = 4, |
417 | .num_resource = 104, | 1459 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1460 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1461 | .host_id = HOST_ID_A53_3, | ||
1462 | }, | ||
1463 | { | ||
1464 | .start_resource = 74, | ||
1465 | .num_resource = 10, | ||
1466 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1467 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1468 | .host_id = HOST_ID_R5_0, | ||
1469 | }, | ||
1470 | { | ||
1471 | .start_resource = 84, | ||
1472 | .num_resource = 12, | ||
1473 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1474 | RESASG_SUBTYPE_RA_UDMAP_RX), | ||
1475 | .host_id = HOST_ID_R5_2, | ||
1476 | }, | ||
1477 | /* MCU NAVSS Rings for Normal capacity Tx channels */ | ||
1478 | { | ||
1479 | .start_resource = 2, | ||
1480 | .num_resource = 2, | ||
1481 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1482 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
418 | .host_id = HOST_ID_A53_2, | 1483 | .host_id = HOST_ID_A53_2, |
419 | }, | 1484 | }, |
420 | { | 1485 | { |
421 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1486 | .start_resource = 4, |
422 | .start_resource = 120, | ||
423 | .num_resource = 4, | 1487 | .num_resource = 4, |
1488 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1489 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
424 | .host_id = HOST_ID_R5_0, | 1490 | .host_id = HOST_ID_R5_0, |
425 | }, | 1491 | }, |
426 | { | 1492 | { |
427 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1493 | .start_resource = 4, |
428 | .start_resource = 124, | 1494 | .num_resource = 0, |
1495 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1496 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
1497 | .host_id = HOST_ID_A53_3, | ||
1498 | }, | ||
1499 | { | ||
1500 | .start_resource = 8, | ||
1501 | .num_resource = 2, | ||
1502 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1503 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
1504 | .host_id = HOST_ID_R5_2, | ||
1505 | }, | ||
1506 | { | ||
1507 | .start_resource = 10, | ||
1508 | .num_resource = 12, | ||
1509 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1510 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
1511 | .host_id = HOST_ID_A53_2, | ||
1512 | }, | ||
1513 | { | ||
1514 | .start_resource = 22, | ||
429 | .num_resource = 4, | 1515 | .num_resource = 4, |
1516 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1517 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
1518 | .host_id = HOST_ID_A53_3, | ||
1519 | }, | ||
1520 | { | ||
1521 | .start_resource = 26, | ||
1522 | .num_resource = 10, | ||
1523 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1524 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
1525 | .host_id = HOST_ID_R5_0, | ||
1526 | }, | ||
1527 | { | ||
1528 | .start_resource = 36, | ||
1529 | .num_resource = 12, | ||
1530 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1531 | RESASG_SUBTYPE_RA_UDMAP_TX), | ||
430 | .host_id = HOST_ID_R5_2, | 1532 | .host_id = HOST_ID_R5_2, |
431 | }, | 1533 | }, |
1534 | /* MCU NAVSS Rings for High capacity Rx channels */ | ||
432 | { | 1535 | { |
433 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1536 | .start_resource = 48, |
434 | .start_resource = 128, | 1537 | .num_resource = 0, |
1538 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1539 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
1540 | .host_id = HOST_ID_R5_0, | ||
1541 | }, | ||
1542 | { | ||
1543 | .start_resource = 48, | ||
1544 | .num_resource = 2, | ||
1545 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1546 | RESASG_SUBTYPE_RA_UDMAP_RX_H), | ||
1547 | .host_id = HOST_ID_R5_0, | ||
1548 | }, | ||
1549 | /* MCU NAVSS Rings for High capacity Tx channels */ | ||
1550 | { | ||
1551 | .start_resource = 0, | ||
1552 | .num_resource = 0, | ||
1553 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1554 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1555 | .host_id = HOST_ID_R5_0, | ||
1556 | }, | ||
1557 | { | ||
1558 | .start_resource = 0, | ||
1559 | .num_resource = 2, | ||
1560 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1561 | RESASG_SUBTYPE_RA_UDMAP_TX_H), | ||
1562 | .host_id = HOST_ID_R5_0, | ||
1563 | }, | ||
1564 | /* MCU NAVSS Ring accelerator virt_id range */ | ||
1565 | { | ||
1566 | .start_resource = 2, | ||
1567 | .num_resource = 1, | ||
1568 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1569 | RESASG_SUBTYPE_RA_VIRTID), | ||
1570 | .host_id = HOST_ID_A53_2, | ||
1571 | }, | ||
1572 | { | ||
1573 | .start_resource = 3, | ||
1574 | .num_resource = 1, | ||
1575 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1576 | RESASG_SUBTYPE_RA_VIRTID), | ||
1577 | .host_id = HOST_ID_A53_3, | ||
1578 | }, | ||
1579 | /* MCU NAVSS Ring monitors */ | ||
1580 | { | ||
1581 | .start_resource = 0, | ||
435 | .num_resource = 8, | 1582 | .num_resource = 8, |
436 | .host_id = HOST_ID_ICSSG_0, | 1583 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1584 | RESASG_SUBTYPE_RA_MONITORS), | ||
1585 | .host_id = HOST_ID_A53_2, | ||
437 | }, | 1586 | }, |
438 | { | 1587 | { |
439 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1588 | .start_resource = 8, |
440 | .start_resource = 136, | 1589 | .num_resource = 4, |
1590 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, | ||
1591 | RESASG_SUBTYPE_RA_MONITORS), | ||
1592 | .host_id = HOST_ID_A53_3, | ||
1593 | }, | ||
1594 | { | ||
1595 | .start_resource = 12, | ||
441 | .num_resource = 8, | 1596 | .num_resource = 8, |
442 | .host_id = HOST_ID_ICSSG_1, | 1597 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1598 | RESASG_SUBTYPE_RA_MONITORS), | ||
1599 | .host_id = HOST_ID_R5_0, | ||
443 | }, | 1600 | }, |
444 | { | 1601 | { |
445 | .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1602 | .start_resource = 20, |
446 | .start_resource = 144, | ||
447 | .num_resource = 8, | 1603 | .num_resource = 8, |
448 | .host_id = HOST_ID_ICSSG_2, | 1604 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
1605 | RESASG_SUBTYPE_RA_MONITORS), | ||
1606 | .host_id = HOST_ID_R5_2, | ||
449 | }, | 1607 | }, |
450 | { | 1608 | { |
451 | .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT), | 1609 | .start_resource = 28, |
452 | .start_resource = 4, | 1610 | .num_resource = 4, |
453 | .num_resource = 28, | 1611 | .type = RESASG_UTYPE (AM6_DEV_MCU_NAVSS0_RINGACC0, |
454 | .host_id = HOST_ID_R5_0, | 1612 | RESASG_SUBTYPE_RA_MONITORS), |
1613 | .host_id = HOST_ID_ALL, | ||
455 | }, | 1614 | }, |
456 | }, | 1615 | }, |
457 | }; | 1616 | }; |
diff --git a/soc/am65x_sr2/evm/sysfw_img_cfg.h b/soc/am65x_sr2/evm/sysfw_img_cfg.h index 2f8203fad..e5eb40335 100644 --- a/soc/am65x_sr2/evm/sysfw_img_cfg.h +++ b/soc/am65x_sr2/evm/sysfw_img_cfg.h | |||
@@ -1,7 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * K3 System Firmware Configuration Data | 2 | * K3 System Firmware Resource Management Board Config Data |
3 | * Auto generated from K3 Resource Partitioning tool | ||
3 | * | 4 | * |
4 | * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ | 5 | * |
6 | * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
5 | * | 7 | * |
6 | * Redistribution and use in source and binary forms, with or without | 8 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions | 9 | * modification, are permitted provided that the following conditions |
@@ -35,6 +37,6 @@ | |||
35 | #ifndef SYSFW_IMG_CFG_H | 37 | #ifndef SYSFW_IMG_CFG_H |
36 | #define SYSFW_IMG_CFG_H | 38 | #define SYSFW_IMG_CFG_H |
37 | 39 | ||
38 | #define BOARDCFG_RM_RESASG_ENTRIES 57 | 40 | #define BOARDCFG_RM_RESASG_ENTRIES 208 |
39 | 41 | ||
40 | #endif /* SYSFW_IMG_CFG_H */ | 42 | #endif /* SYSFW_IMG_CFG_H */ |