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* Makefile: Update firmware for all devices to v2021.01a07.03.00.00507.03.00.00407.03.00.003Praneeth Bajjuri2021-03-171-1/+1
| | | | | | | | | | | | | Update the commit hash for linux-firmware to pick up * sysfw upgrade to v2020.01a for all platforms. commit 5f4b0da944b4 ("ti-sysfw: Update System Firmwares to v2020.01a") * associated dm upgrades for j7200 and j721e * 07.03.00.21 commit 306e8b92bcce ("ti-dm: Update firmware to 07.03.00.21") Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* Makefile: Update firmware for all devices to v2021.0107.03.00.00207.03.00.001Dave Gerlach2021-02-231-1/+1
| | | | | | | | | | | | | | Update the commit hash for linux-firmware to pick up * sysfw upgrade to v2020.01 for all platforms. commit ada0cc1bf918 ("ti-sysfw: Update System Firmwares to v2020.01") * associated dm upgrades: * j7200 - 07.03.00.10 * j721e - 07.03.00.12 commit b7e5d159fd4a ("ti-dm: Update firmware to 07.02.00.1x") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* Makefile: Append RM and PM board cfgs to TIFS in combined img boot flowVignesh Raghavendra2021-02-151-1/+1
| | | | | | | TIFS needs RM board config to be sent in order to validate UDMA firewall configuration requests from DM. This means PM cfg also to be present. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* Makefile: Update firmware for all devices to v2020.12a07.03.00.00007.02.00.004Praneeth Bajjuri2021-01-201-1/+1
| | | | | | | | | | | | | Update the commit hash for linux-firmware to pick up * sysfw upgrade to v2020.12a for am65x, j721e, j7200. commit 5e620449329d ("ti-sysfw: Update System Firmwares to v2020.12a") * associated dm upgrade for j721e and j7200 to 07.02.00.10 commit b66ee9ae020c ("ti-dm: Update firmware to 07.02.00.10") Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Tested-by: Dave Gerlach <d-gerlach@ti.com>
* Makefile: Update firmware for all devices to v2020.1207.02.00.003Praneeth Bajjuri2021-01-141-1/+1
| | | | | | | | | | | | | | Update the commit hash for linux-firmware to pick up * sysfw upgrade to v2020.12 for am65x, j721e, j7200. commit 1c17cc11cc79 ("ti-sysfw: Update System Firmwares to v2020.12") * associated dm upgrade for j721e and j7200 to 07.02.00.05 commit 183b487f02ce ("ti-dm: Update firmware to 07.02.00.05") Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Praneeth Bajjuri <praneeth@ti.com>
* Makefile: Update am64x firmware to v2020.1207.02.00.002Praneeth Bajjuri2021-01-061-1/+1
| | | | | | | Update the commit hash to pick up the am64x v2020.12 from the linux-firmware repo. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* soc: am64x: Add data to enable combined boot flowDave Gerlach2021-01-051-0/+6
| | | | | | | Add the required variables and build steps to allow ROM combined boot image to be generated if SBL variable is provided during build. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* build: Introduce COMBINED_TIFS_BRDCFG build variable for split boardcfgDave Gerlach2021-01-052-3/+12
| | | | | | | | | | | | | | | | | | J7200 supports using a split firmware where TIFS firmware runs on the DMSC and DM firmware runs on an R5, and each are able to receive their own boardcfg loaded from the tiboot3.bin image. Currently COMBINED_SYSFW_BRDCFG can represent both a full set of boardcfg for platforms using a single DMSC firmware or only the TIFS boardcfg when using split firmware. To make this less confusing, introduce a COMBINED_TIFS_BRDCFG build variable to be used only for TIFS BOARDCFG when using split firmware so that COMBINED_SYSFW_BRDCFG always represents a complete set of boardcfg. This allows SoCs to build bootable binaries supporting ROM combined boot images with both splt TIFS/DM firmware or complete DMSC firmware. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* scripts: gen_x509_combined_cert: Make DM boardcfg optionalDave Gerlach2021-01-051-22/+34
| | | | | | | | | | | | | | Upon introduction of support for using DM firmware and providing DM boardcfg through tiboot3.bin, support for providing ALL boardcfg as part of one common boardcfg binary was lost. Modify the gen_x509_combined_cert script so that the DM boardcfg can provided optionally. This allows all boardcfgs to be provided as part of a single binary to look more like the traditional combined boot flow on platforms that do not support a separate DM firmware. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* Makefile: Update commit hash to pick up AM64 binary07.02.00.001Dan Murphy2020-12-171-1/+1
| | | | | | | Update the commit hash to pick up the AM64 binary version w2020.23 from the linux-firmware repo. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* scripts: sysfw_boardcfg_validator: Add substitution for am65x to am6Dave Gerlach2020-12-161-0/+3
| | | | | | | | The sysfw_boardcfg_validator refers to am65x as am6 internally for legacy reasons so add a check to use 'am6' as the SoC name in the script when 'am65x' is passed. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* soc: am64x: Introduce support for evmDave Gerlach2020-12-149-0/+2208
| | | | | | | | Add support for AM64x SoCs. Base the baseport, PM, and security boardcfg off of other platforms and use generated RM config provided by the sysconfig tool. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* scripts: sysfw_boardcfg_*: Update scripts and rules to latestDave Gerlach2020-12-142-4/+871
| | | | | | | Update to the latest boardcfg validator script and rules corresponding to System Firmware v2020.08b Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* HACK: soc: j721e: Adjust MCU NAVSSS UDMA channel allocation07.01.00.006Nikhil Devshatwar2020-11-091-104/+104
| | | | | | | | | | | | | | MCU R5 is facing hang when using channel no 5 and corresponding rings. The transfer finishes, but the TR responce is not generated, ring occupancy does not change. Somehow, MCU R5 is having trouble to use channel no 5. UDMA works fine with channel no 6 onwards. As a workaround, increase the channel allocation for A72 and adjust the allocation for all other cores. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Introduce SCIFS variable to account for SYSFW name variations07.01.00.005Suman Anna2020-11-065-5/+9
| | | | | | | | | | | | The System Firmware functionality on K3 J721E and J7200 SoCs has been reduced to only cater to the foundational security pieces starting from SYSFW 2020.08, and the binaries have been renamed accordingly. Introduce a Makefile variable SCIFS to account for these changes. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Dan Murphy <dmurphy@ti.com>
* soc: j7200: Update block copy allocation for UDMA channelsNikhil Devshatwar2020-10-192-25/+193
| | | | | | | | | | | | | | | | | | To use UDMA channels for block copy, the Tx and Rx channel number has to be the same. When UDMA channels are allocated with just a single range, sometimes it is not possible to allocate the ranges such that the channels can be used for block copy usecase. Fix this by allocating the channels in two ranges, first range for block copy and second range for other usage. When there are no channels for block copy, an entry with 0 count is added. This is to maintain consistency when querying SYSFW about the ranges allocated for a host. Also adjust the MCU NAVSS INTA/INTR allocation after the HSM re architecture Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j721e: Update block copy allocation for UDMA channelsNikhil Devshatwar2020-10-192-179/+935
| | | | | | | | | | | | | | | | | | To use UDMA channels for block copy, the Tx and Rx channel number has to be the same. When UDMA channels are allocated with just a single range, sometimes it is not possible to allocate the ranges such that the channels can be used for block copy usecase. Fix this by allocating the channels in two ranges, first range for block copy and second range for other usage. When there are no channels for block copy, an entry with 0 count is added. This is to maintain consistency when querying SYSFW about the ranges allocated for a host. Also adjust the MCU NAVSS interrupt router allocation after the HSM re architecture Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* scripts: Update board configuration validation files from v2020.08-RC3Nikhil Devshatwar2020-10-192-31/+40
| | | | | | | | | | Update the board config validation script and rules json from v2020.08-RC3 This allows to pass more number of entries in the RM board config updates the resource constraints for MCU NAVSS Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Update firmware binaries to v2020.08-RC307.01.00.004Dave Gerlach2020-10-161-1/+1
| | | | | | | | | | | | | Update the Makefile to automatically fetch and build the v2020.08-RC3 version of the sysfw binaries for all supported SoCs from ti-linux-firmware. Note that this is the first version that will only support split firmware architecture for j721e and j7200, so firmware with SciServer enabled must be used with both SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Suman Anna <s-anna@ti.com>
* scripts: gen_x509_combined_cert: modify to support multiple boardcfg imagesDave Gerlach2020-10-163-10/+43
| | | | | | | | | | | | With the new bootflows being introduced, it is possible for boards to have multiple boardcfg images provided. Modify the gen_x509_combined_cert script to accept two different boardcfg binaries and load them to the defined addresses. This mandates that all platforms using combined bootflow will use the split boardcfg images. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* scripts: sysfw_boardcfg_blob_creator: Take any combination of boardcfgsDave Gerlach2020-10-161-14/+20
| | | | | | | | | With the new bootflows being introduced, it is possible for different combinations of boardcfgs to be needed in different blobs. To account for this, allow any combination of boardcfgs to be specified for the sysfw_boardcfg_blob_creator script and generate binaries as needed. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* sec-cfg: Add secure_handover_config sectionDave Gerlach2020-10-165-0/+53
| | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.08. Starting from SYSFW v2020.08, a secure_handover_config section is mandatory in the security config. Otherwise the boot fails on all SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* Makefile: Set LOADADDR in each SOC MakefileDave Gerlach2020-10-165-3/+10
| | | | | | | | | Each SOC has its own Makefile and some SOCs may have a need for a different load address, so define the LOADADDR variable in the SOC specific Makefile. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* soc: j7200: rm-cfg: Allocate one HC channel pair for A7207.01.00.003Vignesh Raghavendra2020-09-212-17/+73
| | | | | | | | Allocate 1 HC channel pair each in MAIN UDMA and MCU UDMA for A72 so as to enable Linux/U-Boot to demonstrate max performance with HyperFlash and OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* soc: j721e: Reallocate extended channels for R507.01.00.002Nikhil Devshatwar2020-09-152-7/+35
| | | | | | | | | Allocate 2 DRU channels for each of Main R5_0 core0/1 Allocate all the DMPAC channels (last 32) for Main R5 core1 RM config auto generated from the k3-resource-partitioning tool Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Update firmware binaries to v2020.07-RC307.01.00.001Dave Gerlach2020-09-011-1/+1
| | | | | | | | | Update the Makefile to automatically fetch and build the v2020.07-RC3 version of the sysfw binaries for all supported K3 SoCs from the ti-linux-firmware repo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Praneeth Bajjuri <praneeth@ti.com>
* soc: j7200: Update RM board config with latest dataNikhil Devshatwar2020-08-192-198/+520
| | | | | | | | | | * Increase resource allocation for meeting RTOS use cases * Add block copy channel allocation Auto generated from k3-resource-partitioning tool commit ID 8e058012d5bcc457ae1f9212425d0d0ccd534752 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j721e: Update RM board config after SYSFW 2020.07Nikhil Devshatwar2020-08-191-128/+128
| | | | | | | | | | | * Move to new resource subtype names for proxy, ring accelerator and interrupt routers * Adjust VINTs and global event allocation after HSM re architecture Auto generated from k3-resource-partitioning tool commit ID 8e058012d5bcc457ae1f9212425d0d0ccd534752 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* include: j721e: j7200: Update headers from SYSFW 2020.07-RC2Nikhil Devshatwar2020-08-193-30/+51
| | | | | | | Update header files from System firmware 2020.07. This includes many renames for the device macros. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* sec-cfg: Add secure_debug_config sectionSuman Anna2020-08-145-0/+62
| | | | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.07-rc1. Starting from SYSFW v2020.07-rc1, a secure_debug_config section is mandatory in the security config. Otherwise the boot fails on all SoCs. Fix this by adding a section for secure_debug_config with appropriate parameters configured on all on AM65x, AM65x SR2.0, J721E and J7200 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com>
* soc: Introduce SoC specific MakefilesLokesh Vutla2020-08-145-4/+146
| | | | | | | | | | | Now that SoCs have different boot image targets, introduce SOC specific Makefiles to represent boot targets. Below are boot targets: - AM65x: sysfw.itb - AM65x SR2: sysfw.itb - J721E: sysfw.itb - J7200: tiboot3.bin, sysfw.itb Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* scripts: gen_x509_combined_cert: Introduce script for generating combined ↵Lokesh Vutla2020-08-142-0/+285
| | | | | | | | | | | | | boot image New Combined ROM image format consists of the following images: - R5 SBL - SYSFW image - SYSFW data Introduce script for creating this combined ROM image format Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* scripts: sysfw_boardcfg_blob_creator: Add support for combining board ↵Anand Balagopalakrishnan2020-08-142-0/+108
| | | | | | | | | | | configurations files The sysfw data in the new Combined ROM image format should be a single file containing all the four board configurations. Add support for combining all the four board configurations. Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* scripts: Update board configuration validation files for J7200Lokesh Vutla2020-08-142-1/+352
| | | | | | | | | Add the SoC data for J7200 SoCs to the sysfw_boardcfg_rules file, and update the the validator script to include the checking for J7200 SoCs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* soc: j7200: rm-cfg: Auto generate from host-toolsNikhil Devshatwar2020-08-142-3/+1613
| | | | | | | | | | Auto generated from the host-tools with: Commit ID: 1f48ea8844cff145d6b12fee3d8a0b19e0602a66 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: j7200: Add sysfw board config dataLokesh Vutla2020-08-145-0/+342
| | | | | | | | | | | Add the following board configurations specific to j7200 SoC: - board-cfg - pm-cfg - rm-cfg - sec-cfg Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* include: j7200: Add sysfw board config data definitionsLokesh Vutla2020-08-143-0/+480
| | | | | | | | | | Add the following board config data definitions for j7200: - Devices - hosts - RM assignment types Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* scripts: sysfw_boardcfg_validator: Update to validate resasg entriesLokesh Vutla2020-08-142-27/+60
| | | | | | | | | | | Update the sysfw_boardcfg_validator to the latest version to validate the number of resasg entries using the 'max_resource_entries' constraint. The sysfw_boardcfg_rules file is also updated to add the constraint value for each of the existing AM65x, AM65x SR2.0 and J721E SoCs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [s-anna@ti.com: refactor patch] Signed-off-by: Suman Anna <s-anna@ti.com>
* am65x,am65x_sr2: Fix Main NavSS Rings for UDMAP HC Rx channelsSuman Anna2020-08-143-8/+8
| | | | | | | | | | The number of Main NavSS rings reserved by DMSC for High capacity Rx channels is off by one. Update the board configuration validation script and fix the RM cfg resource entries for the same on both AM65x and AM65x SR2.0 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Makefile: Update firmware binaries to v2020.07-RC2Suman Anna2020-08-141-1/+1
| | | | | | | | | | | Update the Makefile to automatically fetch and build the v2020.07-RC2 version of the sysfw binaries for all supported K3 SoCs from the ti-linux-firmware repo. This commit also supports fetching in the binaries for J7200 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com>
* soc: j721e: rm-cfg: Reassign GPIO interrupt routersNikhil Devshatwar2020-08-112-35/+7
| | | | | | | | | | | | | Linux GPIO driver requests all the bank interrupts at the time of probe itself. J721e needs minimum of 11 interrupts for the Main GPIO instances and minimum of 6 interrups for the WKUP GPIO instances. Reassign the allocation to increase the counts for A72 hosts while removing them from unused C7X and R5 cores. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* soc: j721e: rm-cfg: Auto generate from the K3 Resource Partitioning toolNikhil Devshatwar2020-08-112-161/+173
| | | | | | | | | | | | | | | | | | Update the board config using the K3 Resource Partitioning tool * Add the host_cfg_entries section which allows to define capabilities for each host * Updates to comments for readability * Create separate entries for extended channels for HWA and DRU * Remove the HOST_ID_ALL entries for virt_id ranges * Remove the interrupt allocation for slots which are not connected * Remove the 2nd range of C6X NAVSS interrupts The K3 Resource Partitioning tool does not support allocating same resource split across multiple ranges currently. Drop the 2nd range of NAVSS interrupt router for C6X for now Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* soc: j721e: board-cfg: Set MSMC cache size to 0Nikhil Devshatwar2020-06-191-1/+1
| | | | | | | | | For j721e, most of the usecases required MSMC memory to be used as SRAM instead of the cache. Set the msmc_cache_size = 0 for j721e core board config. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Update firmware binaries to v2020.04a07.00.00.00507.00.00.004Praneeth Bajjuri2020-05-281-1/+1
| | | | | | | | Update the Makefile to automatically fetch and build the v2020.04a version of the sysfw binaries for all supported SoCs from ti-linux-firmware. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* j721e: rm-cfg: Switch back to non-secure host for C7x resourcesSuman Anna2020-05-191-23/+23
| | | | | | | | | | | | | The C7x core comes up in secure mode by default, and all the resources reserved for C7x are currently using the secure context id HOST_ID_C7X_0. The latest SYS/BIOS 6.82.00.16 adds the support for properly switching the C7x applications to non-secure mode, so switch back all the resources to use the non-secure context id HOST_ID_C7X_1. All the application firmwares are expected to perform the necessary steps to switch from secure to non-secure context from now on. Signed-off-by: Suman Anna <s-anna@ti.com>
* j721e: rm-cfg: Reassign resources for Main R5FSS0ti2020.01.0007.00.00.00307.00.00.002Nikhil Devshatwar2020-05-062-107/+468
| | | | | | | | | | | | | | | | Auto generated from https://git.ti.com/cgit/glsdk/host-tools Ethernet firmware and PSDKRA will be merged into single image running on Main R5FSS0 core0 leaving the core1 unused for customer. To accomodate this, update the resource partitioning to combine the resources and adjust few to be left free for Main R5FSS0 core1. Also add non secure proxy allocation for both MCU and Main, the C7x resources are also switched to using the secure context. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* scripts: Update boardconfig rules for 2020.04 releaseNikhil Devshatwar2020-05-061-12/+35
| | | | | | | Update the boarconfig rules from latest 2020.04 release This fixes validation errors with virtid resources Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Switch to secure context for C7X resourcesSuman Anna2020-05-061-20/+20
| | | | | | | | | | | | The C7x core comes up in secure mode by default, and all the current firmwares continue to run in this context until the necessary support is added to SYS/BIOS to switch the context. All the C7x RM resources are currently assigned using the non-secure context id HOST_ID_C7X_1. Switch these to the secure context id HOST_ID_C7X_0 to match the usage in PDK and current RTOS firmwares. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* j721e: rm-cfg: Assign unallocated Main NavSS IR GIC_SPI lines to C71xSuman Anna2020-05-051-1/+1
| | | | | | | | | | | The Main NavSS IR has 192 output lines routed to both the GIC and CLEC within the Compute Cluster. The first 10 and the last 4 interrupts are reserved for System Firmware, while the remaining are split up between the HOST_ID_A72_2, HOST_ID_A72_3 and HOST_ID_C7X_1 contexts. The Main NavSS IR output lines [174:187] are currently not allocated to any context, so assign these to the C71x non-secure context. Signed-off-by: Suman Anna <s-anna@ti.com>
* j721e: rm-cfg: Add NavSS IR resources for R5Fs and C66x DSPsSuman Anna2020-05-052-2/+72
| | | | | | | | | | | | | | | | | | | | | | | The ABI 3.0 resource updates haven't added any Main NavSS IR output lines for the MCU and MAIN domain R5Fs, and the MAIN domain C66x remote processors. Add the corresponding resource entries to restore the IPC functionality with these cores. Following is the main summary of resource partitioning: - The 8 interrupts from Main NavSS IR towards MCU domain are split equally between the MCU R5F0 and MCU R5F1. - The first 4 interrupts from each group of 32 interrupts from Main NavSS IR towards a MAIN R5F core are reserved for System Firmware, so the remaining 28 interrupts are added for the corresponding non-secure R5F host contexts. - The 32 interrupts from Main NavSS IR towards each of the C66x DSP cores are split into two sets of 24 interrupts and 8 interrupts, with the first 4 interrupts from the latter set reserved for System Firmware. Add the remaining interrupts from each set to each of the corresponding C66x non-secure contexts. Signed-off-by: Suman Anna <s-anna@ti.com>