path: root/soc/am65x
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* Makefile: Move all target dependency selection to toplevelAndrew Davis2022-05-311-3/+0
| | | | | | | | | Do not duplicate this in SoC specific Makefiles, it is more clear which types of images work with which SoCs if it is one location. AM65x and J721e cannot do combined, AM62x cannot do split, others can do both. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* Makefile: Only build tiboot3.bin for combined image otherwise only sysfw.itbAndrew Davis2022-05-311-1/+1
| | | | | | | | | When building a combined image, do not generate a standalone sysfw.itb. Vice-versa for split image and tiboot3.bin. There is no need to generate the other image and for HS it will be non-functional. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* soc:*: evm: sec-cfg: Fix build warningsVignesh Raghavendra2022-05-311-1/+3
| | | | | | | | | | | Fix below build warnings due to change in defintion of boardcfg_sa2ul_cfg struct ./soc/j721s2/evm/sec-cfg.c:92:18: warning: excess elements in array initializer 92 | .rsvd = {0, 0, 0, 0}, | ^ Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* soc: am65x: rm-cfg: Allocate resources for MCU R5_1Vignesh Raghavendra2021-06-082-15/+379
| | | | | | | | | | | | | R5 SPL on AM65x still uses MCU R5_1 as host ID for requesting DMA resources. Therefore mark resources b/w MCU R5_0 as shared with MCU R5_1. In order to keep number of entries under 260, drop Ring_monitors allocation fro A53_3 Without this OSPI boot cannot use DMA in R5 SPL stage Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* soc: am65x*: rm-cfg; Sync RM cfg to common board cfg2021.00.0032021.00.002Vignesh Raghavendra2021-04-292-206/+1367
| | | | | | | | | Update rm-cfg to ensure DMA resources are shared consistently across RTOS and Linux SDKs. This mainly reduces DMA channels, Rings and GPIO interrupts available for A53 host, but should be sufficient to meet Linux requirements. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* Makefile: Introduce SCIFS variable to account for SYSFW name variations07.01.00.005Suman Anna2020-11-061-0/+1
| | | | | | | | | | | | The System Firmware functionality on K3 J721E and J7200 SoCs has been reduced to only cater to the foundational security pieces starting from SYSFW 2020.08, and the binaries have been renamed accordingly. Introduce a Makefile variable SCIFS to account for these changes. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Dan Murphy <dmurphy@ti.com>
* sec-cfg: Add secure_handover_config sectionDave Gerlach2020-10-161-0/+11
| | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.08. Starting from SYSFW v2020.08, a secure_handover_config section is mandatory in the security config. Otherwise the boot fails on all SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* Makefile: Set LOADADDR in each SOC MakefileDave Gerlach2020-10-161-0/+2
| | | | | | | | | Each SOC has its own Makefile and some SOCs may have a need for a different load address, so define the LOADADDR variable in the SOC specific Makefile. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* sec-cfg: Add secure_debug_config sectionSuman Anna2020-08-141-0/+12
| | | | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.07-rc1. Starting from SYSFW v2020.07-rc1, a secure_debug_config section is mandatory in the security config. Otherwise the boot fails on all SoCs. Fix this by adding a section for secure_debug_config with appropriate parameters configured on all on AM65x, AM65x SR2.0, J721E and J7200 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com>
* soc: Introduce SoC specific MakefilesLokesh Vutla2020-08-141-0/+34
| | | | | | | | | | | Now that SoCs have different boot image targets, introduce SOC specific Makefiles to represent boot targets. Below are boot targets: - AM65x: sysfw.itb - AM65x SR2: sysfw.itb - J721E: sysfw.itb - J7200: tiboot3.bin, sysfw.itb Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am65x,am65x_sr2: Fix Main NavSS Rings for UDMAP HC Rx channelsSuman Anna2020-08-141-2/+2
| | | | | | | | | | The number of Main NavSS rings reserved by DMSC for High capacity Rx channels is off by one. Update the board configuration validation script and fix the RM cfg resource entries for the same on both AM65x and AM65x SR2.0 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am65x,am65x_sr2: Fix MAIN2MCU interrupt routers for both R5F coresSuman Anna2020-05-052-3/+17
| | | | | | | | | | | | | Each of the MCU R5F cores are represented by different HOST_IDs, and the ABI 3.0 RM changes have reassigned all the MAIN2MCU interrupt router outputs back to only the MCU R5F Core0. This breaks the IPC use-cases when the MCU R5FSS cluster is configured for Split-mode. Partition both the MAIN2MCU_LVL and MAIN2MCU_PLS Interrupt Router outputs equally between the non-secure contexts of both the MCU R5F cores. Signed-off-by: Suman Anna <s-anna@ti.com>
* am65x,am65x_sr2: rm-cfg: Fix Main NavSS IR outputs after ABI 3.0Suman Anna2020-05-052-4/+34
| | | | | | | | | | | | | | | | | | The Main NavSS IR on AM65x SoCs has a total of 152 output interrupt lines, out of which the first 16 are reserved for System Firmware. The ABI 3.0 resource updates have assigned all the remaining IR output lines to the A53 host context HOST_ID_A53_2, which is wrong. The Main NavSS IR also supports some interrupt lines for the MCU R5F cores (connected through MAIN2MCU LVL IR) and for each of the 3 ICSSG subsystems. Fix up the Main NavSS IR outputs properly by adding resources for each of the processor subsystems. The output lines [120:127] are split equally for each of the MCU R5F cores (to support Split-mode), leaving only 104 usable interrupts for the A53 core. The output lines [128:151] are associated with the ICSSG subsystems. Signed-off-by: Suman Anna <s-anna@ti.com>
* sec-cfg: Add sa2ul_config sectionDave Gerlach2020-05-041-0/+9
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.04. Starting from SYSFW v2020.04, an sa2ul_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for sa2ul_config with all parameters configured to 0. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* sec-cfg: Add dkek_config sectionDave Gerlach2020-04-231-0/+11
| | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.03. Starting from SYSFW v2020.03, a dkek_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for dkek_config with HOST_ID_ALL in allowed_hosts and allow_dkek_export_tisci set. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* am65x: Update to ABI 3.0 resource typesLokesh Vutla2020-04-032-249/+136
| | | | | | | Update the AM65x RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* j721e: am65x: sec-cfg: Add otp_config sectionNikhil Devshatwar2020-01-211-1/+13
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2019.12. Starting from SYSFW v2019.12, an otp_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for opt_config with no other host having permission to OTP array. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x: Correct R5F core 1 Host IDSam Nelson2019-08-301-1/+1
| | | | | | | | | HOST_ID_R5_1 is to be used only with secure context. HOST_ID_R5_2 is the right Host Id to use for R5F core 1 Fixes: 54933d505c4d ("rm-cfg: Partition interrupt resources between R5F contexts") Signed-off-by: Sam Nelson <sam.nelson@ti.com> Acked-by: Suman Anna <s-anna@ti.com>
* build: Add support for enabling sysfw tracesLokesh Vutla2019-08-291-0/+11
| | | | | | | | | | | | | Sysfw provides a provision for enabling sysfw traces while booting. This has to be enabled in board-cfg. In order to ease debug, enable the sysfw trace support with the help of a build option. Use the option to enable it: $ make ENABLE_TRACE=1 Reported-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* am65x: rm-cfg: Add resources for secure context of MCU R5Vignesh Raghavendra2019-08-052-1/+43
| | | | | | | | | | ROM boots up MCU R5 in secure context and R5 SPL continues to run in the same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU NAVSS resources with MCU R5 secure host ID that is used by R5 SPL. Resources allocated are same as those allocated for A53. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* Makefile: Allow for builds for multiple SoCsAndreas Dannenberg2019-06-105-0/+712
Allow for multiple SoCs to be built and object file names per SoC. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>