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* soc: j7200: rm-cfg: Allocate one HC channel pair for A7207.01.00.003Vignesh Raghavendra2020-09-212-17/+73
| | | | | | | | Allocate 1 HC channel pair each in MAIN UDMA and MCU UDMA for A72 so as to enable Linux/U-Boot to demonstrate max performance with HyperFlash and OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* soc: j721e: Reallocate extended channels for R507.01.00.002Nikhil Devshatwar2020-09-152-7/+35
| | | | | | | | | Allocate 2 DRU channels for each of Main R5_0 core0/1 Allocate all the DMPAC channels (last 32) for Main R5 core1 RM config auto generated from the k3-resource-partitioning tool Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j7200: Update RM board config with latest dataNikhil Devshatwar2020-08-192-198/+520
| | | | | | | | | | * Increase resource allocation for meeting RTOS use cases * Add block copy channel allocation Auto generated from k3-resource-partitioning tool commit ID 8e058012d5bcc457ae1f9212425d0d0ccd534752 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j721e: Update RM board config after SYSFW 2020.07Nikhil Devshatwar2020-08-191-128/+128
| | | | | | | | | | | * Move to new resource subtype names for proxy, ring accelerator and interrupt routers * Adjust VINTs and global event allocation after HSM re architecture Auto generated from k3-resource-partitioning tool commit ID 8e058012d5bcc457ae1f9212425d0d0ccd534752 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* sec-cfg: Add secure_debug_config sectionSuman Anna2020-08-144-0/+48
| | | | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.07-rc1. Starting from SYSFW v2020.07-rc1, a secure_debug_config section is mandatory in the security config. Otherwise the boot fails on all SoCs. Fix this by adding a section for secure_debug_config with appropriate parameters configured on all on AM65x, AM65x SR2.0, J721E and J7200 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com>
* soc: Introduce SoC specific MakefilesLokesh Vutla2020-08-144-0/+143
| | | | | | | | | | | Now that SoCs have different boot image targets, introduce SOC specific Makefiles to represent boot targets. Below are boot targets: - AM65x: sysfw.itb - AM65x SR2: sysfw.itb - J721E: sysfw.itb - J7200: tiboot3.bin, sysfw.itb Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: j7200: rm-cfg: Auto generate from host-toolsNikhil Devshatwar2020-08-142-3/+1613
| | | | | | | | | | Auto generated from the host-tools with: Commit ID: 1f48ea8844cff145d6b12fee3d8a0b19e0602a66 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: j7200: Add sysfw board config dataLokesh Vutla2020-08-145-0/+342
| | | | | | | | | | | Add the following board configurations specific to j7200 SoC: - board-cfg - pm-cfg - rm-cfg - sec-cfg Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x,am65x_sr2: Fix Main NavSS Rings for UDMAP HC Rx channelsSuman Anna2020-08-142-4/+4
| | | | | | | | | | The number of Main NavSS rings reserved by DMSC for High capacity Rx channels is off by one. Update the board configuration validation script and fix the RM cfg resource entries for the same on both AM65x and AM65x SR2.0 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: j721e: rm-cfg: Reassign GPIO interrupt routersNikhil Devshatwar2020-08-112-35/+7
| | | | | | | | | | | | | Linux GPIO driver requests all the bank interrupts at the time of probe itself. J721e needs minimum of 11 interrupts for the Main GPIO instances and minimum of 6 interrups for the WKUP GPIO instances. Reassign the allocation to increase the counts for A72 hosts while removing them from unused C7X and R5 cores. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* soc: j721e: rm-cfg: Auto generate from the K3 Resource Partitioning toolNikhil Devshatwar2020-08-112-161/+173
| | | | | | | | | | | | | | | | | | Update the board config using the K3 Resource Partitioning tool * Add the host_cfg_entries section which allows to define capabilities for each host * Updates to comments for readability * Create separate entries for extended channels for HWA and DRU * Remove the HOST_ID_ALL entries for virt_id ranges * Remove the interrupt allocation for slots which are not connected * Remove the 2nd range of C6X NAVSS interrupts The K3 Resource Partitioning tool does not support allocating same resource split across multiple ranges currently. Drop the 2nd range of NAVSS interrupt router for C6X for now Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* soc: j721e: board-cfg: Set MSMC cache size to 0Nikhil Devshatwar2020-06-191-1/+1
| | | | | | | | | For j721e, most of the usecases required MSMC memory to be used as SRAM instead of the cache. Set the msmc_cache_size = 0 for j721e core board config. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Switch back to non-secure host for C7x resourcesSuman Anna2020-05-191-23/+23
| | | | | | | | | | | | | The C7x core comes up in secure mode by default, and all the resources reserved for C7x are currently using the secure context id HOST_ID_C7X_0. The latest SYS/BIOS 6.82.00.16 adds the support for properly switching the C7x applications to non-secure mode, so switch back all the resources to use the non-secure context id HOST_ID_C7X_1. All the application firmwares are expected to perform the necessary steps to switch from secure to non-secure context from now on. Signed-off-by: Suman Anna <s-anna@ti.com>
* j721e: rm-cfg: Reassign resources for Main R5FSS0ti2020.01.0007.00.00.00307.00.00.002Nikhil Devshatwar2020-05-062-107/+468
| | | | | | | | | | | | | | | | Auto generated from https://git.ti.com/cgit/glsdk/host-tools Ethernet firmware and PSDKRA will be merged into single image running on Main R5FSS0 core0 leaving the core1 unused for customer. To accomodate this, update the resource partitioning to combine the resources and adjust few to be left free for Main R5FSS0 core1. Also add non secure proxy allocation for both MCU and Main, the C7x resources are also switched to using the secure context. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* j721e: rm-cfg: Switch to secure context for C7X resourcesSuman Anna2020-05-061-20/+20
| | | | | | | | | | | | The C7x core comes up in secure mode by default, and all the current firmwares continue to run in this context until the necessary support is added to SYS/BIOS to switch the context. All the C7x RM resources are currently assigned using the non-secure context id HOST_ID_C7X_1. Switch these to the secure context id HOST_ID_C7X_0 to match the usage in PDK and current RTOS firmwares. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* j721e: rm-cfg: Assign unallocated Main NavSS IR GIC_SPI lines to C71xSuman Anna2020-05-051-1/+1
| | | | | | | | | | | The Main NavSS IR has 192 output lines routed to both the GIC and CLEC within the Compute Cluster. The first 10 and the last 4 interrupts are reserved for System Firmware, while the remaining are split up between the HOST_ID_A72_2, HOST_ID_A72_3 and HOST_ID_C7X_1 contexts. The Main NavSS IR output lines [174:187] are currently not allocated to any context, so assign these to the C71x non-secure context. Signed-off-by: Suman Anna <s-anna@ti.com>
* j721e: rm-cfg: Add NavSS IR resources for R5Fs and C66x DSPsSuman Anna2020-05-052-2/+72
| | | | | | | | | | | | | | | | | | | | | | | The ABI 3.0 resource updates haven't added any Main NavSS IR output lines for the MCU and MAIN domain R5Fs, and the MAIN domain C66x remote processors. Add the corresponding resource entries to restore the IPC functionality with these cores. Following is the main summary of resource partitioning: - The 8 interrupts from Main NavSS IR towards MCU domain are split equally between the MCU R5F0 and MCU R5F1. - The first 4 interrupts from each group of 32 interrupts from Main NavSS IR towards a MAIN R5F core are reserved for System Firmware, so the remaining 28 interrupts are added for the corresponding non-secure R5F host contexts. - The 32 interrupts from Main NavSS IR towards each of the C66x DSP cores are split into two sets of 24 interrupts and 8 interrupts, with the first 4 interrupts from the latter set reserved for System Firmware. Add the remaining interrupts from each set to each of the corresponding C66x non-secure contexts. Signed-off-by: Suman Anna <s-anna@ti.com>
* am65x,am65x_sr2: Fix MAIN2MCU interrupt routers for both R5F coresSuman Anna2020-05-054-6/+34
| | | | | | | | | | | | | Each of the MCU R5F cores are represented by different HOST_IDs, and the ABI 3.0 RM changes have reassigned all the MAIN2MCU interrupt router outputs back to only the MCU R5F Core0. This breaks the IPC use-cases when the MCU R5FSS cluster is configured for Split-mode. Partition both the MAIN2MCU_LVL and MAIN2MCU_PLS Interrupt Router outputs equally between the non-secure contexts of both the MCU R5F cores. Signed-off-by: Suman Anna <s-anna@ti.com>
* am65x,am65x_sr2: rm-cfg: Fix Main NavSS IR outputs after ABI 3.0Suman Anna2020-05-054-7/+67
| | | | | | | | | | | | | | | | | | The Main NavSS IR on AM65x SoCs has a total of 152 output interrupt lines, out of which the first 16 are reserved for System Firmware. The ABI 3.0 resource updates have assigned all the remaining IR output lines to the A53 host context HOST_ID_A53_2, which is wrong. The Main NavSS IR also supports some interrupt lines for the MCU R5F cores (connected through MAIN2MCU LVL IR) and for each of the 3 ICSSG subsystems. Fix up the Main NavSS IR outputs properly by adding resources for each of the processor subsystems. The output lines [120:127] are split equally for each of the MCU R5F cores (to support Split-mode), leaving only 104 usable interrupts for the A53 core. The output lines [128:151] are associated with the ICSSG subsystems. Signed-off-by: Suman Anna <s-anna@ti.com>
* sec-cfg: Add sa2ul_config sectionDave Gerlach2020-05-043-0/+27
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.04. Starting from SYSFW v2020.04, an sa2ul_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for sa2ul_config with all parameters configured to 0. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* sec-cfg: Add dkek_config sectionDave Gerlach2020-04-233-0/+33
| | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.03. Starting from SYSFW v2020.03, a dkek_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for dkek_config with HOST_ID_ALL in allowed_hosts and allow_dkek_export_tisci set. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* am65x_sr2: Update to ABI 3.0 resource typesDave Gerlach2020-04-222-159/+112
| | | | | | | Update the AM65x SR2 RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* j721e: Update to ABI 3.0 resource typesNikhil Devshatwar2020-04-032-1019/+1172
| | | | | | | | Update the J721E RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am65x: Update to ABI 3.0 resource typesLokesh Vutla2020-04-032-249/+136
| | | | | | | Update the AM65x RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: am65x_sr2: Introduce support for evmDave Gerlach2020-03-265-0/+708
| | | | | | | | | | | Add support for AM65x SR2 SoCs which have slightly different board configuration requirements than AM65x and also require a specific firmware image. Also update the SYSFW_GIT_HASH to point to the latest ti-linux-firmware repo which contains v2019.12b SR2 binary. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* rm-cfg: j721e: Partition generic IR resource across core0/core1ti2020.00-rc1ti2020-rc1ti2019.06-rc5ti2019.06Nikhil Devshatwar2020-01-241-3/+3
| | | | | | | | | | | | | | | | | Main NAVSS interrupt router for MCU R5 subsystem is shared between both CPU cores. However, SYSFW models them to core specific devices where it appears that the interrupt router is dedicated for each core. MCU NAVSS IR is dedicated per MCU core but main NAVSS IR is not. Due to this, drivers calling GET_RANGE gets the same range on both cores, causing conflict in the interrupt partitioning. Fix this by partitioning the shared interrupt pool between MCU R5 core0 and core1. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* HACK: soc: j721e: Do not cross max limit for RM entriesNikhil Devshatwar2020-01-212-251/+6
| | | | | | | | | | | | | | Maximum number of entries supported in RM board config is currently limited to 276 (2 * RESASG_UTYPE_CNT) Any board config with more entries than this count will be rejected and causes boot failure. This needs to be fixed by increasing the max limit in SYSFW. In the absence of this bugfix, restrict the number of entries by folding all of R5, C6x, C7x host_id entries into single entry. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j721e: Partition nonsecure proxy and ring monitorsNikhil Devshatwar2020-01-212-3/+340
| | | | | | | | Define the resources for non secure proxy and ring monitor allocation across different hosts. Update the total count of resources. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: am65x: sec-cfg: Add otp_config sectionNikhil Devshatwar2020-01-212-2/+26
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2019.12. Starting from SYSFW v2019.12, an otp_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for opt_config with no other host having permission to OTP array. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x: Correct R5F core 1 Host IDSam Nelson2019-08-301-1/+1
| | | | | | | | | HOST_ID_R5_1 is to be used only with secure context. HOST_ID_R5_2 is the right Host Id to use for R5F core 1 Fixes: 54933d505c4d ("rm-cfg: Partition interrupt resources between R5F contexts") Signed-off-by: Sam Nelson <sam.nelson@ti.com> Acked-by: Suman Anna <s-anna@ti.com>
* build: Add support for enabling sysfw tracesLokesh Vutla2019-08-292-0/+22
| | | | | | | | | | | | | Sysfw provides a provision for enabling sysfw traces while booting. This has to be enabled in board-cfg. In order to ease debug, enable the sysfw trace support with the help of a build option. Use the option to enable it: $ make ENABLE_TRACE=1 Reported-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* HACK: j721e: rm-cfg: Use HOST_ALL for ethernet firmware flowsti2019.03-rc4ti2019.03-rc3ti2019.03-rc2ti2019.03Nikhil Devshatwar2019-08-132-9/+2
| | | | | | | | | | | | | | | Ethernet firmware acts as server for providing networking functionality to other clients. It allocates few flows from its pool for the client and then retuns the same to the client. Client does not own the resource it is borrowing from server and currently SYSFW lacks any APIs to allow shared ownership of this resource dyanmically. In absence of such an API, mark the ethernet firmware flows are HOST_ALL so that clients can call FLOW_CONFIG with the borrowed flow. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Partition GPIO interrupt routerNikhil Devshatwar2019-08-122-2/+9
| | | | | | | | Currently the Main GPIO interrupt router is only assigned to A72_2. Partition the IR lines such that few lines are assigned to A72_3 for usage from another Virtual machine. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x: rm-cfg: Add resources for secure context of MCU R5Vignesh Raghavendra2019-08-052-1/+43
| | | | | | | | | | ROM boots up MCU R5 in secure context and R5 SPL continues to run in the same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU NAVSS resources with MCU R5 secure host ID that is used by R5 SPL. Resources allocated are same as those allocated for A53. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* j721e: rm-cfg: Add resources for secure context of MCU R5Vignesh Raghavendra2019-07-312-1/+43
| | | | | | | | | | ROM boots up MCU R5 in secure context and R5 SPL continues to run in the same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU NAVSS resources with MCU R5 secure host ID that is used by R5 SPL. Resources allocated are same as those allocated for non secure context. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* j721e: board-cfg: Drop MSMC cache size from 4MB to 3MBti2019.02-rc4ti2019.02Andreas Dannenberg2019-07-111-1/+1
| | | | | | | | | | Reduce the amount of MSMC memory allocated by System Firmware for the main compute cluster's L3 cache from 4MB to 3MB. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Sunita Nadampalli <sunitan@ti.com> Acked-by: Carlos Hernandez <ceh@ti.com>
* j721e: rm-cfg: Start MAIN_0_R5_2 Tx and Rx at same levelNikhil Devshatwar2019-07-082-22/+7
| | | | | | | | | | | | | | | Channel allocation for MAIN_0_R5_2 is done such that Main NAV UDMA Tx and Rx channels start with different offsets. This cannot be used for block copy carveout since the Tx and Rx channels are not overlapping at start or end of the range. Fix this by allocating more channels to MAIN_0_R5_0 so that the MAIN_0_R5_2 channel ranges start at same value. Autogen table takes care of the corresponding ring allocations as well. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Updated 2019.02 RM configNikhil Devshatwar2019-07-082-734/+941
| | | | | | | | | | | | | | This is auto generated RM config file to describe the resource partitioning for 2019.02 use cases. * Assign few channels/rings for A72_3 to be used by VMs * Assign extended channels for DRU/VPAC/DMPAC * Adjust resources for Main R5_0_1 for ethernet firmware * Reduce resources for R5_1_* cores since nothing is running there * Update the resource entry count Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
* Introduce initial J721E EVM supportAndreas Dannenberg2019-06-105-0/+1956
| | | | | | | | | | | | | | | | Add the consolidated configuration files that were arrived at during J721E silicon wakeup. Note that SYSFW debug trace both to memory as well as to the UART is disabled in alignment with the production configuration used on AM65x. If debug trace output is desired during development refer to the SYSFW release documentation (referenced in the included README.md file) discussion related to 'trace_dst_enables' and 'trace_src_enables'. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Allow for builds for multiple SoCsAndreas Dannenberg2019-06-105-0/+712
Allow for multiple SoCs to be built and object file names per SoC. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>