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* am65x,am65x_sr2: Fix MAIN2MCU interrupt routers for both R5F coresSuman Anna2020-05-054-6/+34
| | | | | | | | | | | | | Each of the MCU R5F cores are represented by different HOST_IDs, and the ABI 3.0 RM changes have reassigned all the MAIN2MCU interrupt router outputs back to only the MCU R5F Core0. This breaks the IPC use-cases when the MCU R5FSS cluster is configured for Split-mode. Partition both the MAIN2MCU_LVL and MAIN2MCU_PLS Interrupt Router outputs equally between the non-secure contexts of both the MCU R5F cores. Signed-off-by: Suman Anna <s-anna@ti.com>
* am65x,am65x_sr2: rm-cfg: Fix Main NavSS IR outputs after ABI 3.0Suman Anna2020-05-054-7/+67
| | | | | | | | | | | | | | | | | | The Main NavSS IR on AM65x SoCs has a total of 152 output interrupt lines, out of which the first 16 are reserved for System Firmware. The ABI 3.0 resource updates have assigned all the remaining IR output lines to the A53 host context HOST_ID_A53_2, which is wrong. The Main NavSS IR also supports some interrupt lines for the MCU R5F cores (connected through MAIN2MCU LVL IR) and for each of the 3 ICSSG subsystems. Fix up the Main NavSS IR outputs properly by adding resources for each of the processor subsystems. The output lines [120:127] are split equally for each of the MCU R5F cores (to support Split-mode), leaving only 104 usable interrupts for the A53 core. The output lines [128:151] are associated with the ICSSG subsystems. Signed-off-by: Suman Anna <s-anna@ti.com>
* sec-cfg: Add sa2ul_config sectionDave Gerlach2020-05-043-0/+27
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.04. Starting from SYSFW v2020.04, an sa2ul_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for sa2ul_config with all parameters configured to 0. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* sec-cfg: Add dkek_config sectionDave Gerlach2020-04-233-0/+33
| | | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2020.03. Starting from SYSFW v2020.03, a dkek_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for dkek_config with HOST_ID_ALL in allowed_hosts and allow_dkek_export_tisci set. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Tested-by: Suman Anna <s-anna@ti.com>
* am65x_sr2: Update to ABI 3.0 resource typesDave Gerlach2020-04-222-159/+112
| | | | | | | Update the AM65x SR2 RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* j721e: Update to ABI 3.0 resource typesNikhil Devshatwar2020-04-032-1019/+1172
| | | | | | | | Update the J721E RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am65x: Update to ABI 3.0 resource typesLokesh Vutla2020-04-032-249/+136
| | | | | | | Update the AM65x RM board configuration to use ABI 3.0 resource type definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* soc: am65x_sr2: Introduce support for evmDave Gerlach2020-03-265-0/+708
| | | | | | | | | | | Add support for AM65x SR2 SoCs which have slightly different board configuration requirements than AM65x and also require a specific firmware image. Also update the SYSFW_GIT_HASH to point to the latest ti-linux-firmware repo which contains v2019.12b SR2 binary. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* rm-cfg: j721e: Partition generic IR resource across core0/core1ti2020.00-rc1ti2020-rc1ti2019.06-rc5ti2019.06Nikhil Devshatwar2020-01-241-3/+3
| | | | | | | | | | | | | | | | | Main NAVSS interrupt router for MCU R5 subsystem is shared between both CPU cores. However, SYSFW models them to core specific devices where it appears that the interrupt router is dedicated for each core. MCU NAVSS IR is dedicated per MCU core but main NAVSS IR is not. Due to this, drivers calling GET_RANGE gets the same range on both cores, causing conflict in the interrupt partitioning. Fix this by partitioning the shared interrupt pool between MCU R5 core0 and core1. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* HACK: soc: j721e: Do not cross max limit for RM entriesNikhil Devshatwar2020-01-212-251/+6
| | | | | | | | | | | | | | Maximum number of entries supported in RM board config is currently limited to 276 (2 * RESASG_UTYPE_CNT) Any board config with more entries than this count will be rejected and causes boot failure. This needs to be fixed by increasing the max limit in SYSFW. In the absence of this bugfix, restrict the number of entries by folding all of R5, C6x, C7x host_id entries into single entry. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* soc: j721e: Partition nonsecure proxy and ring monitorsNikhil Devshatwar2020-01-212-3/+340
| | | | | | | | Define the resources for non secure proxy and ring monitor allocation across different hosts. Update the total count of resources. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: am65x: sec-cfg: Add otp_config sectionNikhil Devshatwar2020-01-212-2/+26
| | | | | | | | | | | | Update the common.h headers to add new defines from SYSFW 2019.12. Starting from SYSFW v2019.12, an otp_config section is mandatory in the security config. Otherwise the boot fails. Fix this by adding a section for opt_config with no other host having permission to OTP array. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x: Correct R5F core 1 Host IDSam Nelson2019-08-301-1/+1
| | | | | | | | | HOST_ID_R5_1 is to be used only with secure context. HOST_ID_R5_2 is the right Host Id to use for R5F core 1 Fixes: 54933d505c4d ("rm-cfg: Partition interrupt resources between R5F contexts") Signed-off-by: Sam Nelson <sam.nelson@ti.com> Acked-by: Suman Anna <s-anna@ti.com>
* build: Add support for enabling sysfw tracesLokesh Vutla2019-08-292-0/+22
| | | | | | | | | | | | | Sysfw provides a provision for enabling sysfw traces while booting. This has to be enabled in board-cfg. In order to ease debug, enable the sysfw trace support with the help of a build option. Use the option to enable it: $ make ENABLE_TRACE=1 Reported-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* HACK: j721e: rm-cfg: Use HOST_ALL for ethernet firmware flowsti2019.03-rc4ti2019.03-rc3ti2019.03-rc2ti2019.03Nikhil Devshatwar2019-08-132-9/+2
| | | | | | | | | | | | | | | Ethernet firmware acts as server for providing networking functionality to other clients. It allocates few flows from its pool for the client and then retuns the same to the client. Client does not own the resource it is borrowing from server and currently SYSFW lacks any APIs to allow shared ownership of this resource dyanmically. In absence of such an API, mark the ethernet firmware flows are HOST_ALL so that clients can call FLOW_CONFIG with the borrowed flow. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Partition GPIO interrupt routerNikhil Devshatwar2019-08-122-2/+9
| | | | | | | | Currently the Main GPIO interrupt router is only assigned to A72_2. Partition the IR lines such that few lines are assigned to A72_3 for usage from another Virtual machine. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* am65x: rm-cfg: Add resources for secure context of MCU R5Vignesh Raghavendra2019-08-052-1/+43
| | | | | | | | | | ROM boots up MCU R5 in secure context and R5 SPL continues to run in the same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU NAVSS resources with MCU R5 secure host ID that is used by R5 SPL. Resources allocated are same as those allocated for A53. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* j721e: rm-cfg: Add resources for secure context of MCU R5Vignesh Raghavendra2019-07-312-1/+43
| | | | | | | | | | ROM boots up MCU R5 in secure context and R5 SPL continues to run in the same context. In order for R5 SPL to use DMA (e.g: with OSPI) add MCU NAVSS resources with MCU R5 secure host ID that is used by R5 SPL. Resources allocated are same as those allocated for non secure context. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* j721e: board-cfg: Drop MSMC cache size from 4MB to 3MBti2019.02-rc4ti2019.02Andreas Dannenberg2019-07-111-1/+1
| | | | | | | | | | Reduce the amount of MSMC memory allocated by System Firmware for the main compute cluster's L3 cache from 4MB to 3MB. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Sunita Nadampalli <sunitan@ti.com> Acked-by: Carlos Hernandez <ceh@ti.com>
* j721e: rm-cfg: Start MAIN_0_R5_2 Tx and Rx at same levelNikhil Devshatwar2019-07-082-22/+7
| | | | | | | | | | | | | | | Channel allocation for MAIN_0_R5_2 is done such that Main NAV UDMA Tx and Rx channels start with different offsets. This cannot be used for block copy carveout since the Tx and Rx channels are not overlapping at start or end of the range. Fix this by allocating more channels to MAIN_0_R5_0 so that the MAIN_0_R5_2 channel ranges start at same value. Autogen table takes care of the corresponding ring allocations as well. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
* j721e: rm-cfg: Updated 2019.02 RM configNikhil Devshatwar2019-07-082-734/+941
| | | | | | | | | | | | | | This is auto generated RM config file to describe the resource partitioning for 2019.02 use cases. * Assign few channels/rings for A72_3 to be used by VMs * Assign extended channels for DRU/VPAC/DMPAC * Adjust resources for Main R5_0_1 for ethernet firmware * Reduce resources for R5_1_* cores since nothing is running there * Update the resource entry count Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
* Introduce initial J721E EVM supportAndreas Dannenberg2019-06-105-0/+1956
| | | | | | | | | | | | | | | | Add the consolidated configuration files that were arrived at during J721E silicon wakeup. Note that SYSFW debug trace both to memory as well as to the UART is disabled in alignment with the production configuration used on AM65x. If debug trace output is desired during development refer to the SYSFW release documentation (referenced in the included README.md file) discussion related to 'trace_dst_enables' and 'trace_src_enables'. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Nikhil Devshatwar <nikhil.nd@ti.com>
* Makefile: Allow for builds for multiple SoCsAndreas Dannenberg2019-06-105-0/+712
Allow for multiple SoCs to be built and object file names per SoC. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
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