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authorLokesh Vutla2020-07-09 23:56:08 -0500
committerLokesh Vutla2020-09-28 04:46:13 -0500
commitc22e61c514e3ead1b508da584f9381926e9b2cef (patch)
treeadb93875336b14cd482ccaad582611a48ce72abd
parent9ad5e4f750145defdd5cac20c2edb4ea796e654b (diff)
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soc: j7200: Add clocks information
Add TISCI clock information for J7200 devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat
-rw-r--r--Makefile3
-rw-r--r--common/socinfo.c3
-rw-r--r--soc/j7200/j7200_clocks_info.c1465
-rw-r--r--soc/j7200/j7200_clocks_info.h42
4 files changed, 1512 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index b163b07..c5d0880 100644
--- a/Makefile
+++ b/Makefile
@@ -94,7 +94,8 @@ J721ESOURCES =\
94 soc/j7200/j7200_host_info.c \ 94 soc/j7200/j7200_host_info.c \
95 soc/j7200/j7200_sec_proxy_info.c \ 95 soc/j7200/j7200_sec_proxy_info.c \
96 soc/j7200/j7200_processors_info.c \ 96 soc/j7200/j7200_processors_info.c \
97 soc/j7200/j7200_devices_info.c 97 soc/j7200/j7200_devices_info.c \
98 soc/j7200/j7200_clocks_info.c
98 99
99 100
100COMMONOBJECTS= $(COMMONSOURCES:.c=.o) 101COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
diff --git a/common/socinfo.c b/common/socinfo.c
index 4485c11..d7624f6 100644
--- a/common/socinfo.c
+++ b/common/socinfo.c
@@ -56,6 +56,7 @@
56#include <soc/j7200/j7200_sec_proxy_info.h> 56#include <soc/j7200/j7200_sec_proxy_info.h>
57#include <soc/j7200/j7200_processors_info.h> 57#include <soc/j7200/j7200_processors_info.h>
58#include <soc/j7200/j7200_devices_info.h> 58#include <soc/j7200/j7200_devices_info.h>
59#include <soc/j7200/j7200_clocks_info.h>
59 60
60/* Assuming these addresses and definitions stay common across K3 devices */ 61/* Assuming these addresses and definitions stay common across K3 devices */
61#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 62#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
@@ -157,6 +158,8 @@ static void j7200_init(void)
157 sci_info->num_processors = J7200_MAX_PROCESSORS_IDS; 158 sci_info->num_processors = J7200_MAX_PROCESSORS_IDS;
158 sci_info->devices_info = j7200_devices_info; 159 sci_info->devices_info = j7200_devices_info;
159 sci_info->num_devices = J7200_MAX_DEVICES; 160 sci_info->num_devices = J7200_MAX_DEVICES;
161 sci_info->clocks_info = j7200_clocks_info;
162 sci_info->num_clocks = J7200_MAX_CLOCKS;
160} 163}
161 164
162int soc_init(uint32_t host_id) 165int soc_init(uint32_t host_id)
diff --git a/soc/j7200/j7200_clocks_info.c b/soc/j7200/j7200_clocks_info.c
new file mode 100644
index 0000000..b58a667
--- /dev/null
+++ b/soc/j7200/j7200_clocks_info.c
@@ -0,0 +1,1465 @@
1/*
2 * J7200 Clocks Info
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <tisci.h>
36#include <socinfo.h>
37
38struct ti_sci_clocks_info j7200_clocks_info[] = {
39 [0] = {4, 0, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
40 [1] = {4, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"},
41 [2] = {4, 2, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"},
42 [3] = {202, 2, "DEV_A72SS0_CORE0_0_ARM_CLK_CLK", "Input clock"},
43 [4] = {203, 0, "DEV_A72SS0_CORE0_1_ARM_CLK_CLK", "Input clock"},
44 [5] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
45 [6] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
46 [7] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
47 [8] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
48 [9] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
49 [10] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
50 [11] = {2, 8, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
51 [12] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
52 [13] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
53 [14] = {2, 12, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
54 [15] = {2, 13, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"},
55 [16] = {157, 1, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
56 [17] = {157, 2, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
57 [18] = {157, 3, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
58 [19] = {157, 4, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
59 [20] = {157, 5, "DEV_BOARD0_OBSCLK2_IN", "Input clock"},
60 [21] = {157, 6, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
61 [22] = {157, 7, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
62 [23] = {157, 8, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
63 [24] = {157, 9, "DEV_BOARD0_RGMII3_TXC_IN", "Input clock"},
64 [25] = {157, 11, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
65 [26] = {157, 12, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
66 [27] = {157, 13, "DEV_BOARD0_GPMC0_CLKOUT_IN", "Input clock"},
67 [28] = {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
68 [29] = {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
69 [30] = {157, 16, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
70 [31] = {157, 31, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
71 [32] = {157, 32, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
72 [33] = {157, 33, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
73 [34] = {157, 34, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
74 [35] = {157, 35, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
75 [36] = {157, 36, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
76 [37] = {157, 37, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
77 [38] = {157, 38, "DEV_BOARD0_OBSCLK1_IN", "Input clock"},
78 [39] = {157, 39, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
79 [40] = {157, 40, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
80 [41] = {157, 41, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
81 [42] = {157, 43, "DEV_BOARD0_TCK_OUT", "Output clock"},
82 [43] = {157, 44, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
83 [44] = {157, 45, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
84 [45] = {157, 46, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
85 [46] = {157, 48, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
86 [47] = {157, 49, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
87 [48] = {157, 52, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"},
88 [49] = {157, 53, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
89 [50] = {157, 54, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
90 [51] = {157, 57, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
91 [52] = {157, 59, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
92 [53] = {157, 61, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
93 [54] = {157, 62, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
94 [55] = {157, 63, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"},
95 [56] = {157, 65, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
96 [57] = {157, 66, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
97 [58] = {157, 68, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
98 [59] = {157, 69, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
99 [60] = {157, 70, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
100 [61] = {157, 71, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
101 [62] = {157, 73, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
102 [63] = {157, 74, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
103 [64] = {157, 77, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
104 [65] = {157, 78, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
105 [66] = {157, 79, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
106 [67] = {157, 80, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
107 [68] = {157, 90, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
108 [69] = {157, 91, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
109 [70] = {157, 92, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
110 [71] = {157, 102, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
111 [72] = {157, 103, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
112 [73] = {157, 104, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
113 [74] = {157, 105, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
114 [75] = {157, 106, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
115 [76] = {157, 110, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
116 [77] = {157, 114, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
117 [78] = {157, 115, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"},
118 [79] = {157, 116, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
119 [80] = {157, 118, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"},
120 [81] = {157, 119, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
121 [82] = {157, 120, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
122 [83] = {157, 122, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
123 [84] = {157, 123, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
124 [85] = {157, 124, "DEV_BOARD0_WKUP_LF_CLKIN_OUT", "Output clock"},
125 [86] = {157, 126, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
126 [87] = {157, 127, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
127 [88] = {157, 128, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
128 [89] = {157, 130, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
129 [90] = {157, 131, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
130 [91] = {157, 132, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
131 [92] = {157, 133, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
132 [93] = {157, 134, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
133 [94] = {157, 144, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
134 [95] = {157, 145, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
135 [96] = {157, 146, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
136 [97] = {157, 156, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
137 [98] = {157, 157, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
138 [99] = {157, 158, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
139 [100] = {157, 159, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
140 [101] = {157, 160, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
141 [102] = {157, 164, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
142 [103] = {157, 165, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
143 [104] = {157, 166, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
144 [105] = {157, 168, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
145 [106] = {157, 169, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
146 [107] = {157, 170, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
147 [108] = {157, 171, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
148 [109] = {157, 172, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
149 [110] = {157, 174, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
150 [111] = {157, 176, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
151 [112] = {157, 177, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
152 [113] = {157, 178, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
153 [114] = {157, 179, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
154 [115] = {157, 180, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
155 [116] = {157, 181, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
156 [117] = {157, 183, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
157 [118] = {157, 184, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
158 [119] = {157, 185, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
159 [120] = {157, 186, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
160 [121] = {157, 187, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
161 [122] = {157, 189, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
162 [123] = {157, 190, "DEV_BOARD0_RGMII4_TXC_IN", "Input clock"},
163 [124] = {157, 191, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
164 [125] = {157, 192, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
165 [126] = {157, 193, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
166 [127] = {157, 194, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
167 [128] = {157, 195, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
168 [129] = {157, 196, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
169 [130] = {157, 197, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
170 [131] = {157, 205, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
171 [132] = {157, 206, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
172 [133] = {157, 207, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
173 [134] = {157, 219, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
174 [135] = {157, 220, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
175 [136] = {157, 221, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
176 [137] = {157, 222, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
177 [138] = {157, 223, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
178 [139] = {157, 224, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
179 [140] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
180 [141] = {3, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK", "Input clock"},
181 [142] = {3, 2, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK", "Input clock"},
182 [143] = {3, 3, "DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK", "Input clock"},
183 [144] = {3, 4, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK", "Input clock"},
184 [145] = {3, 5, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK", "Input clock"},
185 [146] = {3, 6, "DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK", "Input clock"},
186 [147] = {17, 4, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
187 [148] = {19, 0, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"},
188 [149] = {19, 1, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
189 [150] = {19, 2, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
190 [151] = {19, 3, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
191 [152] = {19, 4, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
192 [153] = {19, 5, "DEV_CPSW0_PRE_RGMII4_TCLK", "Output clock"},
193 [154] = {19, 6, "DEV_CPSW0_RGMII3_RXC_I", "Input clock"},
194 [155] = {19, 7, "DEV_CPSW0_RGMII4_RXC_I", "Input clock"},
195 [156] = {19, 8, "DEV_CPSW0_PRE_RGMII3_TCLK", "Output clock"},
196 [157] = {19, 9, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"},
197 [158] = {19, 10, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
198 [159] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
199 [160] = {19, 13, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
200 [161] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
201 [162] = {19, 15, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
202 [163] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
203 [164] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
204 [165] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
205 [166] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
206 [167] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
207 [168] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
208 [169] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
209 [170] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
210 [171] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
211 [172] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
212 [173] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
213 [174] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
214 [175] = {19, 32, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
215 [176] = {19, 33, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
216 [177] = {19, 34, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
217 [178] = {19, 35, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
218 [179] = {19, 36, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
219 [180] = {19, 37, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
220 [181] = {19, 38, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
221 [182] = {19, 39, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
222 [183] = {19, 40, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
223 [184] = {19, 41, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
224 [185] = {19, 42, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
225 [186] = {19, 43, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
226 [187] = {19, 45, "DEV_CPSW0_PRE_RGMII2_TCLK", "Output clock"},
227 [188] = {19, 46, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
228 [189] = {19, 47, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
229 [190] = {19, 48, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
230 [191] = {19, 49, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"},
231 [192] = {19, 50, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
232 [193] = {19, 51, "DEV_CPSW0_PRE_RGMII1_TCLK", "Output clock"},
233 [194] = {19, 52, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
234 [195] = {19, 53, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
235 [196] = {19, 54, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
236 [197] = {19, 55, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
237 [198] = {19, 56, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
238 [199] = {19, 57, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
239 [200] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
240 [201] = {19, 59, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
241 [202] = {19, 60, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
242 [203] = {19, 61, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
243 [204] = {19, 62, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
244 [205] = {19, 63, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
245 [206] = {19, 64, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
246 [207] = {19, 66, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
247 [208] = {19, 67, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
248 [209] = {26, 0, "DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A", "Output clock"},
249 [210] = {26, 1, "DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A", "Output clock"},
250 [211] = {26, 2, "DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A", "Output clock"},
251 [212] = {26, 3, "DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A", "Output clock"},
252 [213] = {26, 4, "DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK", "Input clock"},
253 [214] = {26, 5, "DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK", "Input clock"},
254 [215] = {26, 6, "DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK", "Input clock"},
255 [216] = {26, 7, "DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK", "Input clock"},
256 [217] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
257 [218] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
258 [219] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
259 [220] = {25, 0, "DEV_CPT2_AGGR3_VCLK_CLK", "Input clock"},
260 [221] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
261 [222] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
262 [223] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
263 [224] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
264 [225] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
265 [226] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
266 [227] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
267 [228] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
268 [229] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
269 [230] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
270 [231] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
271 [232] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
272 [233] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
273 [234] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
274 [235] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
275 [236] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
276 [237] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
277 [238] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
278 [239] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
279 [240] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
280 [241] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
281 [242] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
282 [243] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
283 [244] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
284 [245] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
285 [246] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
286 [247] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
287 [248] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
288 [249] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
289 [250] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
290 [251] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
291 [252] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
292 [253] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
293 [254] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
294 [255] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
295 [256] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
296 [257] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
297 [258] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
298 [259] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
299 [260] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
300 [261] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
301 [262] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
302 [263] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
303 [264] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
304 [265] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
305 [266] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
306 [267] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
307 [268] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
308 [269] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
309 [270] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
310 [271] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
311 [272] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
312 [273] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
313 [274] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
314 [275] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
315 [276] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
316 [277] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
317 [278] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
318 [279] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
319 [280] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
320 [281] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
321 [282] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
322 [283] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
323 [284] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
324 [285] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
325 [286] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
326 [287] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
327 [288] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
328 [289] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
329 [290] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
330 [291] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
331 [292] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
332 [293] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
333 [294] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
334 [295] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
335 [296] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
336 [297] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
337 [298] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
338 [299] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
339 [300] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
340 [301] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
341 [302] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
342 [303] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
343 [304] = {8, 0, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
344 [305] = {8, 5, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
345 [306] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
346 [307] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
347 [308] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
348 [309] = {304, 34, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
349 [310] = {304, 49, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
350 [311] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
351 [312] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
352 [313] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
353 [314] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
354 [315] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
355 [316] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
356 [317] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
357 [318] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
358 [319] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
359 [320] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
360 [321] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
361 [322] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
362 [323] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
363 [324] = {97, 0, "DEV_ESM0_CLK", "Input clock"},
364 [325] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
365 [326] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
366 [327] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
367 [328] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
368 [329] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
369 [330] = {115, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
370 [331] = {115, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
371 [332] = {115, 2, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
372 [333] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
373 [334] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
374 [335] = {115, 5, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
375 [336] = {115, 6, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
376 [337] = {115, 7, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
377 [338] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
378 [339] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
379 [340] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
380 [341] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
381 [342] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
382 [343] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
383 [344] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
384 [345] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
385 [346] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
386 [347] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
387 [348] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
388 [349] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
389 [350] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
390 [351] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
391 [352] = {187, 0, "DEV_I2C0_PISCL", "Input clock"},
392 [353] = {187, 1, "DEV_I2C0_PISYS_CLK", "Input clock"},
393 [354] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
394 [355] = {187, 3, "DEV_I2C0_PORSCL", "Output clock"},
395 [356] = {188, 0, "DEV_I2C1_PISCL", "Input clock"},
396 [357] = {188, 1, "DEV_I2C1_PISYS_CLK", "Input clock"},
397 [358] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
398 [359] = {188, 3, "DEV_I2C1_PORSCL", "Output clock"},
399 [360] = {189, 0, "DEV_I2C2_PISCL", "Input clock"},
400 [361] = {189, 1, "DEV_I2C2_PISYS_CLK", "Input clock"},
401 [362] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
402 [363] = {189, 3, "DEV_I2C2_PORSCL", "Output clock"},
403 [364] = {190, 0, "DEV_I2C3_PISCL", "Input clock"},
404 [365] = {190, 1, "DEV_I2C3_PISYS_CLK", "Input clock"},
405 [366] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
406 [367] = {190, 3, "DEV_I2C3_PORSCL", "Output clock"},
407 [368] = {191, 0, "DEV_I2C4_PISCL", "Input clock"},
408 [369] = {191, 1, "DEV_I2C4_PISYS_CLK", "Input clock"},
409 [370] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
410 [371] = {191, 3, "DEV_I2C4_PORSCL", "Output clock"},
411 [372] = {192, 0, "DEV_I2C5_PISCL", "Input clock"},
412 [373] = {192, 1, "DEV_I2C5_PISYS_CLK", "Input clock"},
413 [374] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
414 [375] = {192, 3, "DEV_I2C5_PORSCL", "Output clock"},
415 [376] = {193, 0, "DEV_I2C6_PISCL", "Input clock"},
416 [377] = {193, 1, "DEV_I2C6_PISYS_CLK", "Input clock"},
417 [378] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
418 [379] = {193, 3, "DEV_I2C6_PORSCL", "Output clock"},
419 [380] = {116, 0, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
420 [381] = {116, 1, "DEV_I3C0_I3C_SCL_DO", "Output clock"},
421 [382] = {116, 2, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
422 [383] = {116, 4, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
423 [384] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
424 [385] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
425 [386] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
426 [387] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
427 [388] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
428 [389] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
429 [390] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
430 [391] = {156, 6, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
431 [392] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
432 [393] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
433 [394] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
434 [395] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
435 [396] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
436 [397] = {158, 6, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
437 [398] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
438 [399] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
439 [400] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
440 [401] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
441 [402] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
442 [403] = {168, 6, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
443 [404] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
444 [405] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
445 [406] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
446 [407] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
447 [408] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
448 [409] = {169, 6, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
449 [410] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
450 [411] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
451 [412] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
452 [413] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
453 [414] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
454 [415] = {170, 6, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
455 [416] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
456 [417] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
457 [418] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
458 [419] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
459 [420] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
460 [421] = {171, 6, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
461 [422] = {150, 0, "DEV_MCAN14_MCANSS_HCLK_CLK", "Input clock"},
462 [423] = {150, 2, "DEV_MCAN14_MCANSS_CCLK_CLK", "Input muxed clock"},
463 [424] = {150, 3, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
464 [425] = {150, 4, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
465 [426] = {150, 5, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
466 [427] = {150, 6, "DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN14_MCANSS_CCLK_CLK"},
467 [428] = {151, 0, "DEV_MCAN15_MCANSS_HCLK_CLK", "Input clock"},
468 [429] = {151, 2, "DEV_MCAN15_MCANSS_CCLK_CLK", "Input muxed clock"},
469 [430] = {151, 3, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
470 [431] = {151, 4, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
471 [432] = {151, 5, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
472 [433] = {151, 6, "DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN15_MCANSS_CCLK_CLK"},
473 [434] = {152, 0, "DEV_MCAN16_MCANSS_HCLK_CLK", "Input clock"},
474 [435] = {152, 2, "DEV_MCAN16_MCANSS_CCLK_CLK", "Input muxed clock"},
475 [436] = {152, 3, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
476 [437] = {152, 4, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
477 [438] = {152, 5, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
478 [439] = {152, 6, "DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN16_MCANSS_CCLK_CLK"},
479 [440] = {153, 0, "DEV_MCAN17_MCANSS_HCLK_CLK", "Input clock"},
480 [441] = {153, 2, "DEV_MCAN17_MCANSS_CCLK_CLK", "Input muxed clock"},
481 [442] = {153, 3, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
482 [443] = {153, 4, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
483 [444] = {153, 5, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
484 [445] = {153, 6, "DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN17_MCANSS_CCLK_CLK"},
485 [446] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
486 [447] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
487 [448] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
488 [449] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
489 [450] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
490 [451] = {160, 6, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
491 [452] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
492 [453] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
493 [454] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
494 [455] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
495 [456] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
496 [457] = {161, 6, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
497 [458] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
498 [459] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
499 [460] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
500 [461] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
501 [462] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
502 [463] = {162, 6, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
503 [464] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
504 [465] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
505 [466] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
506 [467] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
507 [468] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
508 [469] = {163, 6, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
509 [470] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
510 [471] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
511 [472] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
512 [473] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
513 [474] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
514 [475] = {164, 6, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
515 [476] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
516 [477] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
517 [478] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
518 [479] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
519 [480] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
520 [481] = {165, 6, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
521 [482] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
522 [483] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
523 [484] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
524 [485] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
525 [486] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
526 [487] = {166, 6, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
527 [488] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
528 [489] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
529 [490] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
530 [491] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
531 [492] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
532 [493] = {167, 6, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
533 [494] = {174, 0, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
534 [495] = {174, 2, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
535 [496] = {174, 3, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
536 [497] = {174, 4, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
537 [498] = {174, 5, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
538 [499] = {174, 6, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
539 [500] = {174, 11, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
540 [501] = {174, 12, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
541 [502] = {174, 13, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
542 [503] = {174, 14, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
543 [504] = {174, 19, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
544 [505] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
545 [506] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
546 [507] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
547 [508] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
548 [509] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
549 [510] = {174, 30, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
550 [511] = {174, 31, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
551 [512] = {174, 32, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
552 [513] = {174, 33, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
553 [514] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
554 [515] = {174, 39, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
555 [516] = {174, 40, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
556 [517] = {174, 41, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
557 [518] = {174, 42, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
558 [519] = {174, 45, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
559 [520] = {174, 46, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
560 [521] = {174, 47, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
561 [522] = {174, 48, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
562 [523] = {174, 49, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
563 [524] = {174, 50, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
564 [525] = {174, 51, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
565 [526] = {175, 0, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
566 [527] = {175, 2, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
567 [528] = {175, 3, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
568 [529] = {175, 4, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
569 [530] = {175, 5, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
570 [531] = {175, 6, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
571 [532] = {175, 11, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
572 [533] = {175, 12, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
573 [534] = {175, 13, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
574 [535] = {175, 14, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
575 [536] = {175, 19, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
576 [537] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
577 [538] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
578 [539] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
579 [540] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
580 [541] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
581 [542] = {175, 30, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
582 [543] = {175, 31, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
583 [544] = {175, 32, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
584 [545] = {175, 33, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
585 [546] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
586 [547] = {175, 39, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
587 [548] = {175, 40, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
588 [549] = {175, 41, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
589 [550] = {175, 42, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
590 [551] = {175, 45, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
591 [552] = {175, 46, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
592 [553] = {175, 47, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
593 [554] = {175, 48, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
594 [555] = {175, 49, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
595 [556] = {175, 50, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
596 [557] = {175, 51, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
597 [558] = {176, 0, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
598 [559] = {176, 2, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
599 [560] = {176, 3, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
600 [561] = {176, 4, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
601 [562] = {176, 5, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
602 [563] = {176, 6, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
603 [564] = {176, 11, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
604 [565] = {176, 12, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
605 [566] = {176, 13, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
606 [567] = {176, 14, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
607 [568] = {176, 19, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
608 [569] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
609 [570] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
610 [571] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
611 [572] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
612 [573] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
613 [574] = {176, 30, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
614 [575] = {176, 31, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
615 [576] = {176, 32, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
616 [577] = {176, 33, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
617 [578] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
618 [579] = {176, 39, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
619 [580] = {176, 40, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
620 [581] = {176, 41, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
621 [582] = {176, 42, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
622 [583] = {176, 45, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
623 [584] = {176, 46, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
624 [585] = {176, 47, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
625 [586] = {176, 48, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
626 [587] = {176, 49, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
627 [588] = {176, 50, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
628 [589] = {176, 51, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
629 [590] = {266, 3, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
630 [591] = {266, 4, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
631 [592] = {266, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
632 [593] = {267, 3, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
633 [594] = {267, 4, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
634 [595] = {267, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
635 [596] = {268, 3, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
636 [597] = {268, 4, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
637 [598] = {268, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
638 [599] = {269, 0, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
639 [600] = {269, 1, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
640 [601] = {269, 3, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
641 [602] = {269, 4, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
642 [603] = {269, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
643 [604] = {270, 0, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
644 [605] = {270, 1, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
645 [606] = {270, 2, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
646 [607] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
647 [608] = {271, 3, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
648 [609] = {271, 4, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
649 [610] = {271, 5, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
650 [611] = {272, 3, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
651 [612] = {272, 4, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
652 [613] = {272, 5, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
653 [614] = {273, 3, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
654 [615] = {273, 4, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
655 [616] = {273, 5, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
656 [617] = {0, 0, "DEV_MCU_ADC0_SYS_CLK", "Input clock"},
657 [618] = {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"},
658 [619] = {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
659 [620] = {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
660 [621] = {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
661 [622] = {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
662 [623] = {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"},
663 [624] = {1, 0, "DEV_MCU_ADC1_SYS_CLK", "Input clock"},
664 [625] = {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"},
665 [626] = {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
666 [627] = {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
667 [628] = {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
668 [629] = {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
669 [630] = {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"},
670 [631] = {18, 0, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"},
671 [632] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
672 [633] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
673 [634] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
674 [635] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
675 [636] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
676 [637] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
677 [638] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
678 [639] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
679 [640] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
680 [641] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
681 [642] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
682 [643] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
683 [644] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
684 [645] = {18, 20, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
685 [646] = {18, 21, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
686 [647] = {18, 22, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"},
687 [648] = {18, 24, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
688 [649] = {18, 27, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
689 [650] = {18, 28, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
690 [651] = {18, 29, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
691 [652] = {18, 30, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
692 [653] = {18, 31, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
693 [654] = {18, 32, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
694 [655] = {18, 33, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
695 [656] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
696 [657] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
697 [658] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
698 [659] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
699 [660] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
700 [661] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
701 [662] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
702 [663] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
703 [664] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
704 [665] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
705 [666] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
706 [667] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
707 [668] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
708 [669] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
709 [670] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
710 [671] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
711 [672] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
712 [673] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
713 [674] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
714 [675] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
715 [676] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
716 [677] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
717 [678] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
718 [679] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
719 [680] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
720 [681] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
721 [682] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
722 [683] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
723 [684] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
724 [685] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
725 [686] = {46, 4, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
726 [687] = {46, 5, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
727 [688] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
728 [689] = {46, 8, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
729 [690] = {46, 9, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
730 [691] = {46, 11, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
731 [692] = {46, 12, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
732 [693] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
733 [694] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
734 [695] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
735 [696] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
736 [697] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
737 [698] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
738 [699] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
739 [700] = {102, 7, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
740 [701] = {102, 10, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
741 [702] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
742 [703] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
743 [704] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
744 [705] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
745 [706] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
746 [707] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
747 [708] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
748 [709] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
749 [710] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
750 [711] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
751 [712] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input clock"},
752 [713] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
753 [714] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
754 [715] = {194, 0, "DEV_MCU_I2C0_PISCL", "Input clock"},
755 [716] = {194, 1, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
756 [717] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
757 [718] = {195, 0, "DEV_MCU_I2C1_PISCL", "Input clock"},
758 [719] = {195, 1, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
759 [720] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
760 [721] = {195, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"},
761 [722] = {117, 0, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
762 [723] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"},
763 [724] = {117, 2, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
764 [725] = {117, 4, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
765 [726] = {118, 2, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
766 [727] = {118, 4, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
767 [728] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
768 [729] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
769 [730] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
770 [731] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
771 [732] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
772 [733] = {172, 6, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
773 [734] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
774 [735] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
775 [736] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
776 [737] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
777 [738] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
778 [739] = {173, 6, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
779 [740] = {274, 3, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
780 [741] = {274, 4, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
781 [742] = {274, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
782 [743] = {275, 0, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
783 [744] = {275, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
784 [745] = {275, 3, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
785 [746] = {275, 4, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
786 [747] = {275, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
787 [748] = {276, 0, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
788 [749] = {276, 1, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
789 [750] = {276, 2, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
790 [751] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
791 [752] = {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"},
792 [753] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
793 [754] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
794 [755] = {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"},
795 [756] = {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"},
796 [757] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
797 [758] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
798 [759] = {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
799 [760] = {142, 1, "DEV_MCU_PBIST0_CLK7_CLK", "Input clock"},
800 [761] = {142, 2, "DEV_MCU_PBIST0_CLK3_CLK", "Input clock"},
801 [762] = {142, 3, "DEV_MCU_PBIST0_CLK5_CLK", "Input clock"},
802 [763] = {142, 4, "DEV_MCU_PBIST0_CLK1_CLK", "Input clock"},
803 [764] = {142, 5, "DEV_MCU_PBIST0_CLK8_CLK", "Input clock"},
804 [765] = {142, 6, "DEV_MCU_PBIST0_CLK6_CLK", "Input clock"},
805 [766] = {142, 8, "DEV_MCU_PBIST0_CLK4_CLK", "Input clock"},
806 [767] = {142, 9, "DEV_MCU_PBIST0_CLK2_CLK", "Input clock"},
807 [768] = {143, 1, "DEV_MCU_PBIST1_CLK7_CLK", "Input clock"},
808 [769] = {143, 2, "DEV_MCU_PBIST1_CLK3_CLK", "Input clock"},
809 [770] = {143, 3, "DEV_MCU_PBIST1_CLK5_CLK", "Input clock"},
810 [771] = {143, 4, "DEV_MCU_PBIST1_CLK1_CLK", "Input clock"},
811 [772] = {143, 5, "DEV_MCU_PBIST1_CLK8_CLK", "Input clock"},
812 [773] = {143, 6, "DEV_MCU_PBIST1_CLK6_CLK", "Input clock"},
813 [774] = {143, 8, "DEV_MCU_PBIST1_CLK4_CLK", "Input clock"},
814 [775] = {143, 9, "DEV_MCU_PBIST1_CLK2_CLK", "Input clock"},
815 [776] = {144, 1, "DEV_MCU_PBIST2_CLK7_CLK", "Input clock"},
816 [777] = {144, 2, "DEV_MCU_PBIST2_CLK3_CLK", "Input clock"},
817 [778] = {144, 3, "DEV_MCU_PBIST2_CLK5_CLK", "Input clock"},
818 [779] = {144, 4, "DEV_MCU_PBIST2_CLK1_CLK", "Input clock"},
819 [780] = {144, 5, "DEV_MCU_PBIST2_CLK8_CLK", "Input clock"},
820 [781] = {144, 6, "DEV_MCU_PBIST2_CLK6_CLK", "Input clock"},
821 [782] = {144, 8, "DEV_MCU_PBIST2_CLK4_CLK", "Input clock"},
822 [783] = {144, 9, "DEV_MCU_PBIST2_CLK2_CLK", "Input clock"},
823 [784] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
824 [785] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
825 [786] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
826 [787] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
827 [788] = {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
828 [789] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
829 [790] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
830 [791] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
831 [792] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
832 [793] = {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
833 [794] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
834 [795] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
835 [796] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
836 [797] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
837 [798] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
838 [799] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
839 [800] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
840 [801] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
841 [802] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
842 [803] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
843 [804] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
844 [805] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
845 [806] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"},
846 [807] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
847 [808] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
848 [809] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
849 [810] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
850 [811] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
851 [812] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
852 [813] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
853 [814] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
854 [815] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
855 [816] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
856 [817] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
857 [818] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
858 [819] = {35, 11, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
859 [820] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
860 [821] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
861 [822] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
862 [823] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
863 [824] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
864 [825] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
865 [826] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
866 [827] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
867 [828] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
868 [829] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
869 [830] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
870 [831] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
871 [832] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
872 [833] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
873 [834] = {72, 11, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
874 [835] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
875 [836] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
876 [837] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
877 [838] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
878 [839] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
879 [840] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
880 [841] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
881 [842] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
882 [843] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
883 [844] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
884 [845] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
885 [846] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
886 [847] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
887 [848] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
888 [849] = {74, 11, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"},
889 [850] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
890 [851] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
891 [852] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
892 [853] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
893 [854] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
894 [855] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
895 [856] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
896 [857] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
897 [858] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
898 [859] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
899 [860] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
900 [861] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
901 [862] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
902 [863] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
903 [864] = {76, 11, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"},
904 [865] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
905 [866] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
906 [867] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
907 [868] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
908 [869] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
909 [870] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
910 [871] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
911 [872] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
912 [873] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
913 [874] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
914 [875] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
915 [876] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
916 [877] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
917 [878] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
918 [879] = {78, 11, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"},
919 [880] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
920 [881] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
921 [882] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
922 [883] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
923 [884] = {149, 2, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
924 [885] = {149, 3, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
925 [886] = {149, 4, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
926 [887] = {149, 5, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
927 [888] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
928 [889] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
929 [890] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
930 [891] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
931 [892] = {91, 6, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
932 [893] = {91, 7, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
933 [894] = {92, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"},
934 [895] = {92, 1, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
935 [896] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
936 [897] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
937 [898] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
938 [899] = {92, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
939 [900] = {92, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
940 [901] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
941 [902] = {199, 0, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"},
942 [903] = {199, 1, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"},
943 [904] = {199, 2, "DEV_NAVSS0_CPTS0_GENF4", "Output clock"},
944 [905] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
945 [906] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
946 [907] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
947 [908] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
948 [909] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
949 [910] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
950 [911] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
951 [912] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
952 [913] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
953 [914] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
954 [915] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
955 [916] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
956 [917] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
957 [918] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
958 [919] = {201, 20, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
959 [920] = {201, 21, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
960 [921] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"},
961 [922] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
962 [923] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
963 [924] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
964 [925] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
965 [926] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
966 [927] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
967 [928] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
968 [929] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
969 [930] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
970 [931] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
971 [932] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
972 [933] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
973 [934] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
974 [935] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
975 [936] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
976 [937] = {207, 0, "DEV_NAVSS0_MODSS_INTA_0_SYS_CLK", "Input clock"},
977 [938] = {208, 0, "DEV_NAVSS0_MODSS_INTA_1_SYS_CLK", "Input clock"},
978 [939] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
979 [940] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
980 [941] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
981 [942] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"},
982 [943] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
983 [944] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
984 [945] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
985 [946] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
986 [947] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
987 [948] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
988 [949] = {209, 0, "DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
989 [950] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
990 [951] = {139, 1, "DEV_PBIST0_CLK7_CLK", "Input clock"},
991 [952] = {139, 2, "DEV_PBIST0_CLK3_CLK", "Input clock"},
992 [953] = {139, 3, "DEV_PBIST0_CLK5_CLK", "Input clock"},
993 [954] = {139, 4, "DEV_PBIST0_CLK1_CLK", "Input clock"},
994 [955] = {139, 5, "DEV_PBIST0_CLK8_CLK", "Input clock"},
995 [956] = {139, 6, "DEV_PBIST0_CLK6_CLK", "Input clock"},
996 [957] = {139, 8, "DEV_PBIST0_CLK4_CLK", "Input clock"},
997 [958] = {139, 9, "DEV_PBIST0_CLK2_CLK", "Input clock"},
998 [959] = {140, 1, "DEV_PBIST1_CLK7_CLK", "Input clock"},
999 [960] = {140, 2, "DEV_PBIST1_CLK3_CLK", "Input clock"},
1000 [961] = {140, 3, "DEV_PBIST1_CLK5_CLK", "Input clock"},
1001 [962] = {140, 4, "DEV_PBIST1_CLK1_CLK", "Input clock"},
1002 [963] = {140, 5, "DEV_PBIST1_CLK8_CLK", "Input clock"},
1003 [964] = {140, 6, "DEV_PBIST1_CLK6_CLK", "Input clock"},
1004 [965] = {140, 8, "DEV_PBIST1_CLK4_CLK", "Input clock"},
1005 [966] = {140, 9, "DEV_PBIST1_CLK2_CLK", "Input clock"},
1006 [967] = {141, 1, "DEV_PBIST2_CLK7_CLK", "Input clock"},
1007 [968] = {141, 2, "DEV_PBIST2_CLK3_CLK", "Input clock"},
1008 [969] = {141, 3, "DEV_PBIST2_CLK5_CLK", "Input clock"},
1009 [970] = {141, 4, "DEV_PBIST2_CLK1_CLK", "Input clock"},
1010 [971] = {141, 5, "DEV_PBIST2_CLK8_CLK", "Input clock"},
1011 [972] = {141, 6, "DEV_PBIST2_CLK6_CLK", "Input clock"},
1012 [973] = {141, 8, "DEV_PBIST2_CLK4_CLK", "Input clock"},
1013 [974] = {141, 9, "DEV_PBIST2_CLK2_CLK", "Input clock"},
1014 [975] = {240, 0, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
1015 [976] = {240, 1, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
1016 [977] = {240, 2, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
1017 [978] = {240, 3, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
1018 [979] = {240, 4, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
1019 [980] = {240, 5, "DEV_PCIE1_PCIE_LANE3_TXMCLK", "Input clock"},
1020 [981] = {240, 6, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
1021 [982] = {240, 7, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
1022 [983] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
1023 [984] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1024 [985] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1025 [986] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1026 [987] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1027 [988] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1028 [989] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1029 [990] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1030 [991] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1031 [992] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1032 [993] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1033 [994] = {240, 23, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1034 [995] = {240, 24, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
1035 [996] = {240, 25, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
1036 [997] = {240, 27, "DEV_PCIE1_PCIE_LANE2_RXCLK", "Input clock"},
1037 [998] = {240, 28, "DEV_PCIE1_PCIE_LANE2_TXMCLK", "Input clock"},
1038 [999] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
1039 [1000] = {240, 30, "DEV_PCIE1_PCIE_LANE3_TXFCLK", "Input clock"},
1040 [1001] = {240, 31, "DEV_PCIE1_PCIE_LANE2_TXFCLK", "Input clock"},
1041 [1002] = {240, 32, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
1042 [1003] = {240, 33, "DEV_PCIE1_PCIE_LANE2_TXCLK", "Output clock"},
1043 [1004] = {240, 34, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
1044 [1005] = {240, 35, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
1045 [1006] = {240, 36, "DEV_PCIE1_PCIE_LANE3_RXFCLK", "Input clock"},
1046 [1007] = {240, 37, "DEV_PCIE1_PCIE_LANE2_RXFCLK", "Input clock"},
1047 [1008] = {240, 38, "DEV_PCIE1_PCIE_LANE3_RXCLK", "Input clock"},
1048 [1009] = {240, 39, "DEV_PCIE1_PCIE_LANE3_REFCLK", "Input clock"},
1049 [1010] = {240, 40, "DEV_PCIE1_PCIE_LANE2_REFCLK", "Input clock"},
1050 [1011] = {240, 41, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
1051 [1012] = {240, 42, "DEV_PCIE1_PCIE_LANE3_TXCLK", "Output clock"},
1052 [1013] = {240, 43, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
1053 [1014] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
1054 [1015] = {133, 1, "DEV_PSC0_CLK", "Input clock"},
1055 [1016] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
1056 [1017] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
1057 [1018] = {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
1058 [1019] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
1059 [1020] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
1060 [1021] = {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
1061 [1022] = {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
1062 [1023] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
1063 [1024] = {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1064 [1025] = {252, 3, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1065 [1026] = {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1066 [1027] = {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1067 [1028] = {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1068 [1029] = {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1069 [1030] = {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1070 [1031] = {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
1071 [1032] = {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
1072 [1033] = {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
1073 [1034] = {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1074 [1035] = {253, 3, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1075 [1036] = {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1076 [1037] = {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1077 [1038] = {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1078 [1039] = {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1079 [1040] = {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1080 [1041] = {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
1081 [1042] = {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
1082 [1043] = {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
1083 [1044] = {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1084 [1045] = {258, 3, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1085 [1046] = {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1086 [1047] = {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1087 [1048] = {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1088 [1049] = {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1089 [1050] = {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1090 [1051] = {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
1091 [1052] = {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
1092 [1053] = {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
1093 [1054] = {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1094 [1055] = {259, 3, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1095 [1056] = {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1096 [1057] = {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1097 [1058] = {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1098 [1059] = {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1099 [1060] = {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1100 [1061] = {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
1101 [1062] = {292, 1, "DEV_SERDES_10G1_IP3_LN1_TXFCLK", "Output clock"},
1102 [1063] = {292, 3, "DEV_SERDES_10G1_IP2_LN2_REFCLK", "Output clock"},
1103 [1064] = {292, 4, "DEV_SERDES_10G1_IP1_LN0_TXMCLK", "Output clock"},
1104 [1065] = {292, 6, "DEV_SERDES_10G1_IP3_LN3_RXCLK", "Output clock"},
1105 [1066] = {292, 9, "DEV_SERDES_10G1_IP2_LN2_RXCLK", "Output clock"},
1106 [1067] = {292, 10, "DEV_SERDES_10G1_IP1_LN0_TXFCLK", "Output clock"},
1107 [1068] = {292, 11, "DEV_SERDES_10G1_CLK", "Input clock"},
1108 [1069] = {292, 13, "DEV_SERDES_10G1_IP1_LN3_RXCLK", "Output clock"},
1109 [1070] = {292, 14, "DEV_SERDES_10G1_IP1_LN1_TXMCLK", "Output clock"},
1110 [1071] = {292, 15, "DEV_SERDES_10G1_IP2_LN0_TXFCLK", "Output clock"},
1111 [1072] = {292, 16, "DEV_SERDES_10G1_IP2_LN2_TXMCLK", "Output clock"},
1112 [1073] = {292, 19, "DEV_SERDES_10G1_IP3_LN1_TXCLK", "Input clock"},
1113 [1074] = {292, 21, "DEV_SERDES_10G1_IP2_LN3_RXFCLK", "Output clock"},
1114 [1075] = {292, 22, "DEV_SERDES_10G1_IP1_LN2_TXCLK", "Input clock"},
1115 [1076] = {292, 24, "DEV_SERDES_10G1_IP2_LN1_RXCLK", "Output clock"},
1116 [1077] = {292, 25, "DEV_SERDES_10G1_IP2_LN1_TXCLK", "Input clock"},
1117 [1078] = {292, 29, "DEV_SERDES_10G1_IP1_LN2_TXMCLK", "Output clock"},
1118 [1079] = {292, 32, "DEV_SERDES_10G1_IP2_LN1_TXMCLK", "Output clock"},
1119 [1080] = {292, 33, "DEV_SERDES_10G1_IP2_LN1_TXFCLK", "Output clock"},
1120 [1081] = {292, 34, "DEV_SERDES_10G1_IP1_LN1_TXFCLK", "Output clock"},
1121 [1082] = {292, 38, "DEV_SERDES_10G1_IP1_LN2_RXCLK", "Output clock"},
1122 [1083] = {292, 40, "DEV_SERDES_10G1_IP2_LN1_REFCLK", "Output clock"},
1123 [1084] = {292, 41, "DEV_SERDES_10G1_IP2_LN0_TXMCLK", "Output clock"},
1124 [1085] = {292, 42, "DEV_SERDES_10G1_IP2_LN3_RXCLK", "Output clock"},
1125 [1086] = {292, 43, "DEV_SERDES_10G1_IP2_LN2_TXCLK", "Input clock"},
1126 [1087] = {292, 44, "DEV_SERDES_10G1_IP2_LN2_RXFCLK", "Output clock"},
1127 [1088] = {292, 45, "DEV_SERDES_10G1_IP1_LN1_RXFCLK", "Output clock"},
1128 [1089] = {292, 49, "DEV_SERDES_10G1_IP1_LN0_RXCLK", "Output clock"},
1129 [1090] = {292, 52, "DEV_SERDES_10G1_IP1_LN1_RXCLK", "Output clock"},
1130 [1091] = {292, 55, "DEV_SERDES_10G1_IP1_LN0_RXFCLK", "Output clock"},
1131 [1092] = {292, 56, "DEV_SERDES_10G1_IP3_LN3_TXCLK", "Input clock"},
1132 [1093] = {292, 59, "DEV_SERDES_10G1_IP2_LN3_REFCLK", "Output clock"},
1133 [1094] = {292, 61, "DEV_SERDES_10G1_IP2_LN0_TXCLK", "Input clock"},
1134 [1095] = {292, 62, "DEV_SERDES_10G1_IP2_LN3_TXMCLK", "Output clock"},
1135 [1096] = {292, 63, "DEV_SERDES_10G1_IP1_LN1_REFCLK", "Output clock"},
1136 [1097] = {292, 65, "DEV_SERDES_10G1_IP1_LN3_TXCLK", "Input clock"},
1137 [1098] = {292, 66, "DEV_SERDES_10G1_IP3_LN1_TXMCLK", "Output clock"},
1138 [1099] = {292, 67, "DEV_SERDES_10G1_IP2_LN2_TXFCLK", "Output clock"},
1139 [1100] = {292, 73, "DEV_SERDES_10G1_IP3_LN1_RXCLK", "Output clock"},
1140 [1101] = {292, 74, "DEV_SERDES_10G1_IP3_LN1_REFCLK", "Output clock"},
1141 [1102] = {292, 75, "DEV_SERDES_10G1_IP1_LN3_REFCLK", "Output clock"},
1142 [1103] = {292, 77, "DEV_SERDES_10G1_IP1_LN0_REFCLK", "Output clock"},
1143 [1104] = {292, 80, "DEV_SERDES_10G1_IP1_LN2_REFCLK", "Output clock"},
1144 [1105] = {292, 81, "DEV_SERDES_10G1_IP2_LN0_REFCLK", "Output clock"},
1145 [1106] = {292, 82, "DEV_SERDES_10G1_IP2_LN0_RXCLK", "Output clock"},
1146 [1107] = {292, 85, "DEV_SERDES_10G1_CORE_REF_CLK", "Input muxed clock"},
1147 [1108] = {292, 86, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
1148 [1109] = {292, 87, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
1149 [1110] = {292, 88, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
1150 [1111] = {292, 89, "DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G1_CORE_REF_CLK"},
1151 [1112] = {292, 92, "DEV_SERDES_10G1_IP1_LN3_TXMCLK", "Output clock"},
1152 [1113] = {292, 95, "DEV_SERDES_10G1_IP2_LN3_TXCLK", "Input clock"},
1153 [1114] = {292, 96, "DEV_SERDES_10G1_IP3_LN3_RXFCLK", "Output clock"},
1154 [1115] = {292, 98, "DEV_SERDES_10G1_IP3_LN3_REFCLK", "Output clock"},
1155 [1116] = {292, 100, "DEV_SERDES_10G1_IP2_LN1_RXFCLK", "Output clock"},
1156 [1117] = {292, 102, "DEV_SERDES_10G1_IP3_LN1_RXFCLK", "Output clock"},
1157 [1118] = {292, 104, "DEV_SERDES_10G1_IP1_LN1_TXCLK", "Input clock"},
1158 [1119] = {292, 107, "DEV_SERDES_10G1_IP3_LN3_TXFCLK", "Output clock"},
1159 [1120] = {292, 108, "DEV_SERDES_10G1_IP1_LN3_TXFCLK", "Output clock"},
1160 [1121] = {292, 109, "DEV_SERDES_10G1_IP2_LN3_TXFCLK", "Output clock"},
1161 [1122] = {292, 111, "DEV_SERDES_10G1_IP1_LN0_TXCLK", "Input clock"},
1162 [1123] = {292, 112, "DEV_SERDES_10G1_IP2_LN0_RXFCLK", "Output clock"},
1163 [1124] = {292, 113, "DEV_SERDES_10G1_IP1_LN2_RXFCLK", "Output clock"},
1164 [1125] = {292, 118, "DEV_SERDES_10G1_IP1_LN2_TXFCLK", "Output clock"},
1165 [1126] = {292, 124, "DEV_SERDES_10G1_IP1_LN3_RXFCLK", "Output clock"},
1166 [1127] = {292, 126, "DEV_SERDES_10G1_IP3_LN3_TXMCLK", "Output clock"},
1167 [1128] = {29, 0, "DEV_STM0_CORE_CLK", "Input clock"},
1168 [1129] = {29, 1, "DEV_STM0_VBUSP_CLK", "Input clock"},
1169 [1130] = {29, 2, "DEV_STM0_ATB_CLK", "Input clock"},
1170 [1131] = {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
1171 [1132] = {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
1172 [1133] = {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1173 [1134] = {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1174 [1135] = {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1175 [1136] = {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1176 [1137] = {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1177 [1138] = {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1178 [1139] = {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1179 [1140] = {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1180 [1141] = {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1181 [1142] = {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1182 [1143] = {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1183 [1144] = {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1184 [1145] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1185 [1146] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1186 [1147] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1187 [1148] = {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
1188 [1149] = {49, 26, "DEV_TIMER0_TIMER_PWM", "Output clock"},
1189 [1150] = {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
1190 [1151] = {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
1191 [1152] = {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
1192 [1153] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
1193 [1154] = {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
1194 [1155] = {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
1195 [1156] = {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1196 [1157] = {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1197 [1158] = {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1198 [1159] = {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1199 [1160] = {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1200 [1161] = {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1201 [1162] = {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1202 [1163] = {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1203 [1164] = {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1204 [1165] = {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1205 [1166] = {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1206 [1167] = {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1207 [1168] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1208 [1169] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1209 [1170] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1210 [1171] = {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
1211 [1172] = {60, 26, "DEV_TIMER10_TIMER_PWM", "Output clock"},
1212 [1173] = {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
1213 [1174] = {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
1214 [1175] = {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
1215 [1176] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
1216 [1177] = {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"},
1217 [1178] = {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
1218 [1179] = {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1219 [1180] = {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1220 [1181] = {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1221 [1182] = {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1222 [1183] = {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1223 [1184] = {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1224 [1185] = {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1225 [1186] = {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1226 [1187] = {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1227 [1188] = {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1228 [1189] = {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1229 [1190] = {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1230 [1191] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1231 [1192] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1232 [1193] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1233 [1194] = {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
1234 [1195] = {63, 26, "DEV_TIMER12_TIMER_PWM", "Output clock"},
1235 [1196] = {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"},
1236 [1197] = {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
1237 [1198] = {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
1238 [1199] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
1239 [1200] = {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"},
1240 [1201] = {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
1241 [1202] = {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1242 [1203] = {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1243 [1204] = {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1244 [1205] = {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1245 [1206] = {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1246 [1207] = {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1247 [1208] = {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1248 [1209] = {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1249 [1210] = {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1250 [1211] = {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1251 [1212] = {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1252 [1213] = {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1253 [1214] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1254 [1215] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1255 [1216] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1256 [1217] = {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
1257 [1218] = {65, 26, "DEV_TIMER14_TIMER_PWM", "Output clock"},
1258 [1219] = {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"},
1259 [1220] = {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
1260 [1221] = {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
1261 [1222] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
1262 [1223] = {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"},
1263 [1224] = {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
1264 [1225] = {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1265 [1226] = {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1266 [1227] = {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1267 [1228] = {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1268 [1229] = {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1269 [1230] = {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1270 [1231] = {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1271 [1232] = {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1272 [1233] = {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1273 [1234] = {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1274 [1235] = {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1275 [1236] = {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1276 [1237] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1277 [1238] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1278 [1239] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1279 [1240] = {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
1280 [1241] = {67, 26, "DEV_TIMER16_TIMER_PWM", "Output clock"},
1281 [1242] = {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"},
1282 [1243] = {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
1283 [1244] = {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
1284 [1245] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
1285 [1246] = {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"},
1286 [1247] = {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
1287 [1248] = {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1288 [1249] = {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1289 [1250] = {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1290 [1251] = {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1291 [1252] = {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1292 [1253] = {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1293 [1254] = {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1294 [1255] = {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1295 [1256] = {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1296 [1257] = {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1297 [1258] = {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1298 [1259] = {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1299 [1260] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1300 [1261] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1301 [1262] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1302 [1263] = {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
1303 [1264] = {69, 26, "DEV_TIMER18_TIMER_PWM", "Output clock"},
1304 [1265] = {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"},
1305 [1266] = {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
1306 [1267] = {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
1307 [1268] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
1308 [1269] = {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
1309 [1270] = {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
1310 [1271] = {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1311 [1272] = {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1312 [1273] = {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1313 [1274] = {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1314 [1275] = {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1315 [1276] = {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1316 [1277] = {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1317 [1278] = {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1318 [1279] = {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1319 [1280] = {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1320 [1281] = {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1321 [1282] = {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1322 [1283] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1323 [1284] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1324 [1285] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1325 [1286] = {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
1326 [1287] = {51, 26, "DEV_TIMER2_TIMER_PWM", "Output clock"},
1327 [1288] = {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
1328 [1289] = {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
1329 [1290] = {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
1330 [1291] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
1331 [1292] = {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
1332 [1293] = {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
1333 [1294] = {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1334 [1295] = {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1335 [1296] = {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1336 [1297] = {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1337 [1298] = {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1338 [1299] = {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1339 [1300] = {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1340 [1301] = {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1341 [1302] = {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1342 [1303] = {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1343 [1304] = {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1344 [1305] = {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1345 [1306] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1346 [1307] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1347 [1308] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1348 [1309] = {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
1349 [1310] = {53, 26, "DEV_TIMER4_TIMER_PWM", "Output clock"},
1350 [1311] = {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
1351 [1312] = {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
1352 [1313] = {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
1353 [1314] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
1354 [1315] = {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
1355 [1316] = {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
1356 [1317] = {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1357 [1318] = {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1358 [1319] = {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1359 [1320] = {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1360 [1321] = {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1361 [1322] = {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1362 [1323] = {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1363 [1324] = {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1364 [1325] = {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1365 [1326] = {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1366 [1327] = {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1367 [1328] = {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1368 [1329] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1369 [1330] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1370 [1331] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1371 [1332] = {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
1372 [1333] = {55, 26, "DEV_TIMER6_TIMER_PWM", "Output clock"},
1373 [1334] = {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
1374 [1335] = {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
1375 [1336] = {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
1376 [1337] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
1377 [1338] = {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
1378 [1339] = {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
1379 [1340] = {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1380 [1341] = {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1381 [1342] = {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1382 [1343] = {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1383 [1344] = {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1384 [1345] = {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1385 [1346] = {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1386 [1347] = {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1387 [1348] = {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1388 [1349] = {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1389 [1350] = {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1390 [1351] = {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1391 [1352] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1392 [1353] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1393 [1354] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1394 [1355] = {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
1395 [1356] = {58, 26, "DEV_TIMER8_TIMER_PWM", "Output clock"},
1396 [1357] = {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
1397 [1358] = {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
1398 [1359] = {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
1399 [1360] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
1400 [1361] = {146, 2, "DEV_UART0_FCLK_CLK", "Input clock"},
1401 [1362] = {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"},
1402 [1363] = {278, 2, "DEV_UART1_FCLK_CLK", "Input clock"},
1403 [1364] = {278, 3, "DEV_UART1_VBUSP_CLK", "Input clock"},
1404 [1365] = {279, 2, "DEV_UART2_FCLK_CLK", "Input clock"},
1405 [1366] = {279, 3, "DEV_UART2_VBUSP_CLK", "Input clock"},
1406 [1367] = {280, 2, "DEV_UART3_FCLK_CLK", "Input clock"},
1407 [1368] = {280, 3, "DEV_UART3_VBUSP_CLK", "Input clock"},
1408 [1369] = {281, 2, "DEV_UART4_FCLK_CLK", "Input clock"},
1409 [1370] = {281, 3, "DEV_UART4_VBUSP_CLK", "Input clock"},
1410 [1371] = {282, 2, "DEV_UART5_FCLK_CLK", "Input clock"},
1411 [1372] = {282, 3, "DEV_UART5_VBUSP_CLK", "Input clock"},
1412 [1373] = {283, 2, "DEV_UART6_FCLK_CLK", "Input clock"},
1413 [1374] = {283, 3, "DEV_UART6_VBUSP_CLK", "Input clock"},
1414 [1375] = {284, 2, "DEV_UART7_FCLK_CLK", "Input clock"},
1415 [1376] = {284, 3, "DEV_UART7_VBUSP_CLK", "Input clock"},
1416 [1377] = {285, 2, "DEV_UART8_FCLK_CLK", "Input clock"},
1417 [1378] = {285, 3, "DEV_UART8_VBUSP_CLK", "Input clock"},
1418 [1379] = {286, 2, "DEV_UART9_FCLK_CLK", "Input clock"},
1419 [1380] = {286, 3, "DEV_UART9_VBUSP_CLK", "Input clock"},
1420 [1381] = {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"},
1421 [1382] = {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
1422 [1383] = {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
1423 [1384] = {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
1424 [1385] = {288, 4, "DEV_USB0_BUF_CLK", "Input clock"},
1425 [1386] = {288, 5, "DEV_USB0_PIPE_TXFCLK", "Input clock"},
1426 [1387] = {288, 6, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
1427 [1388] = {288, 7, "DEV_USB0_PIPE_RXCLK", "Input clock"},
1428 [1389] = {288, 8, "DEV_USB0_PIPE_TXMCLK", "Input clock"},
1429 [1390] = {288, 9, "DEV_USB0_PIPE_RXFCLK", "Input clock"},
1430 [1391] = {288, 11, "DEV_USB0_PIPE_TXCLK", "Output clock"},
1431 [1392] = {288, 12, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
1432 [1393] = {288, 13, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
1433 [1394] = {288, 14, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
1434 [1395] = {288, 15, "DEV_USB0_PCLK_CLK", "Input clock"},
1435 [1396] = {288, 17, "DEV_USB0_ACLK_CLK", "Input clock"},
1436 [1397] = {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"},
1437 [1398] = {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
1438 [1399] = {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input muxed clock"},
1439 [1400] = {113, 1, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
1440 [1401] = {113, 2, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
1441 [1402] = {113, 3, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
1442 [1403] = {113, 4, "DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_MMR_CLK"},
1443 [1404] = {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input muxed clock"},
1444 [1405] = {114, 1, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
1445 [1406] = {114, 2, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
1446 [1407] = {114, 3, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
1447 [1408] = {114, 4, "DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO1_MMR_CLK"},
1448 [1409] = {197, 0, "DEV_WKUP_I2C0_PISCL", "Input clock"},
1449 [1410] = {197, 1, "DEV_WKUP_I2C0_PISYS_CLK", "Input clock"},
1450 [1411] = {197, 2, "DEV_WKUP_I2C0_CLK", "Input clock"},
1451 [1412] = {197, 3, "DEV_WKUP_I2C0_PORSCL", "Output clock"},
1452 [1413] = {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"},
1453 [1414] = {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
1454 [1415] = {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
1455 [1416] = {287, 2, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"},
1456 [1417] = {287, 3, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
1457 [1418] = {287, 4, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
1458 [1419] = {287, 5, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
1459 [1420] = {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
1460 [1421] = {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
1461 [1422] = {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
1462 [1423] = {40, 0, "DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK", "Input clock"},
1463 [1424] = {40, 1, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK", "Output clock"},
1464 [1425] = {40, 2, "DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK", "Output clock"},
1465};
diff --git a/soc/j7200/j7200_clocks_info.h b/soc/j7200/j7200_clocks_info.h
new file mode 100644
index 0000000..e9e5ad2
--- /dev/null
+++ b/soc/j7200/j7200_clocks_info.h
@@ -0,0 +1,42 @@
1/*
2 * J7200 Clocks Info
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __J7200_CLOCKS_INFO_H
36#define __J7200_CLOCKS_INFO_H
37
38#define J7200_MAX_CLOCKS 1426
39
40extern struct ti_sci_clocks_info j7200_clocks_info[];
41
42#endif /* __J7200_CLOCKS_INFO_H */
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