diff options
author | Murali Karicheri | 2014-11-21 10:58:41 -0600 |
---|---|---|
committer | Murali Karicheri | 2014-11-21 10:58:41 -0600 |
commit | 11a8eaee39b68e6047f07382c251786b40bef165 (patch) | |
tree | ccacd9765017c25fa61524598a9e53c1644f8c73 | |
parent | 2235516234345f05c4d73da95d1a4f4cbbde7f3b (diff) | |
parent | bdec1c4c21be8c50a39bc7eaeeddfb6d64d63ce5 (diff) | |
download | linux-v3.13/master.tar.gz linux-v3.13/master.tar.xz linux-v3.13/master.zip |
Merge branch 'v3.13/keystone-drivers' into v3.13/masterv3.13/master
-rw-r--r-- | Documentation/devicetree/bindings/rapidio/keystone-srio.txt | 55 | ||||
-rw-r--r-- | drivers/rapidio/devices/keystone_rio.c | 863 | ||||
-rw-r--r-- | drivers/rapidio/devices/keystone_rio.h | 17 | ||||
-rw-r--r-- | drivers/rapidio/devices/keystone_rio_serdes.c | 1606 | ||||
-rw-r--r-- | drivers/rapidio/devices/keystone_rio_serdes.h | 76 |
5 files changed, 2142 insertions, 475 deletions
diff --git a/Documentation/devicetree/bindings/rapidio/keystone-srio.txt b/Documentation/devicetree/bindings/rapidio/keystone-srio.txt index ededa82c952..9837b0aa691 100644 --- a/Documentation/devicetree/bindings/rapidio/keystone-srio.txt +++ b/Documentation/devicetree/bindings/rapidio/keystone-srio.txt | |||
@@ -25,23 +25,8 @@ dma-coherent: Indicate if DirectIO operations support hw cache-coherency. | |||
25 | On KeyStone platforms it is recommended to set this property | 25 | On KeyStone platforms it is recommended to set this property |
26 | when running on ARM cores. | 26 | when running on ARM cores. |
27 | keystone2-serdes: Indicate that the driver needs to use KeyStone 2 SerDes | 27 | keystone2-serdes: Indicate that the driver needs to use KeyStone 2 SerDes |
28 | initialization. If not specified, it will KeyStone 1 | 28 | initialization. If not specified, it will be KeyStone 1 |
29 | initialization instead. | 29 | initialization instead. |
30 | serdes_1sb: Allow to set the TX driver 1 lsb pre emphasis setting for KeyStone | ||
31 | 2 SerDes. There is one value per lane. Default value is 0. | ||
32 | serdes_c1: Allow to override value of TX driver C1 coefficient for KeyStone | ||
33 | 2 SerDes. There is one value per lane. Default value if not | ||
34 | specified is 6 for 3.125Gbps and 4 for other baudrates. | ||
35 | serdes_c2: Allow to override value of TX driver C2 coefficient for KeyStone | ||
36 | 2 SerDes. There is one value per lane. Default value is 0 if not | ||
37 | specified. | ||
38 | serdes_cm: Allow to override value of TX driver CM coefficient for KeyStone | ||
39 | 2 SerDes. There is one value per lane. Default value is 0. | ||
40 | serdes_att: Allow to set attenuator setting of TX driver for KeyStone 2 SerDes. | ||
41 | There is one value per lane. Default value is 12 if not specified. | ||
42 | serdes_vreg: Allow to set regulator voltage setting for TX driver for KeyStone 2 | ||
43 | SerDes. There is one value per lane. Default value is 4 if not | ||
44 | specified. | ||
45 | baudrate: This the lane baudrate configuration number (from 0 to 3). | 30 | baudrate: This the lane baudrate configuration number (from 0 to 3). |
46 | If not specified the baudrate configuration 0 will be used | 31 | If not specified the baudrate configuration 0 will be used |
47 | (1.25Gbps). | 32 | (1.25Gbps). |
@@ -74,8 +59,46 @@ pkt-forward: This allow to define the routing table for hardware packet | |||
74 | 0x3 to port 1. | 59 | 0x3 to port 1. |
75 | All the 8 entries must be referenced with the 3 values. | 60 | All the 8 entries must be referenced with the 3 values. |
76 | 61 | ||
62 | SerDes optional properties | ||
63 | -------------------------- | ||
64 | |||
65 | These properties are used to tune the KeyStone 2 SerDes hardware parameters and | ||
66 | coefficients. For more information please refer to KeyStone II Architecture | ||
67 | Serializer/Deserializer (SerDes) User Guide (SPRUHO3) available on www.ti.com. | ||
68 | |||
69 | serdes_1sb: Allow to set the TX driver 1 lsb pre emphasis setting for KeyStone | ||
70 | 2 SerDes. There is one value per lane. Default value is 0. | ||
71 | serdes_c1: Allow to override value of TX driver C1 coefficient for KeyStone | ||
72 | 2 SerDes. There is one value per lane. Default value if not | ||
73 | specified is 6 for 3.125Gbps and 4 for other baudrates. | ||
74 | serdes_c2: Allow to override value of TX driver C2 coefficient for KeyStone | ||
75 | 2 SerDes. There is one value per lane. Default value is 0 if not | ||
76 | specified. | ||
77 | serdes_cm: Allow to override value of TX driver CM coefficient for KeyStone | ||
78 | 2 SerDes. There is one value per lane. Default value is 0. | ||
79 | serdes_att: Allow to set attenuator setting of TX driver for KeyStone 2 SerDes. | ||
80 | There is one value per lane. Default value is 12 if not specified. | ||
81 | serdes_vreg: Allow to set regulator voltage setting for TX driver for KeyStone 2 | ||
82 | SerDes. There is one value per lane. Default value is 4 if not | ||
83 | specified. | ||
84 | serdes_vdreg: Allow to set lane regulator output voltage setting for TX driver | ||
85 | for KeyStone 2. Default value is 1 (VNOM) if not specified. | ||
86 | serdes_rx_att_start: | ||
87 | Allow to set attenuator start value of RX driver for Keystone 2 | ||
88 | SerDes. There is one value per lane. Default value is 3. | ||
89 | serdes_rx_boost_start: | ||
90 | Allow to set attenuator start value of RX driver for Keystone 2 | ||
91 | SerDes. There is one value per lane. Default value is 3. | ||
92 | serdes_rx_att: Allow to set attenuator static value of RX driver for Keystone 2 | ||
93 | SerDes. If set to -1, dynamic calibration is used instead. | ||
94 | There is one value per lane. Default value is -1 (dynamic cal). | ||
95 | serdes_rx_boost: Allow to set attenuator start value of RX driver for Keystone 2 | ||
96 | SerDes. If set to -1, dynamic calibration is used instead. | ||
97 | There is one value per lane. Default value is -1 (dynamic cal). | ||
98 | |||
77 | Sub-nodes | 99 | Sub-nodes |
78 | --------- | 100 | --------- |
101 | |||
79 | Each mailbox (according to num-mboxes) must be added as subnodes "mbox-%d" with %d the | 102 | Each mailbox (according to num-mboxes) must be added as subnodes "mbox-%d" with %d the |
80 | mailbox number (from 0 to n). | 103 | mailbox number (from 0 to n). |
81 | This sub-node has the following properties: | 104 | This sub-node has the following properties: |
diff --git a/drivers/rapidio/devices/keystone_rio.c b/drivers/rapidio/devices/keystone_rio.c index ab0d920ec64..75398932e89 100644 --- a/drivers/rapidio/devices/keystone_rio.c +++ b/drivers/rapidio/devices/keystone_rio.c | |||
@@ -37,6 +37,18 @@ | |||
37 | 37 | ||
38 | #define DRIVER_VER "v1.2" | 38 | #define DRIVER_VER "v1.2" |
39 | 39 | ||
40 | static bool serdes_calibration; | ||
41 | module_param(serdes_calibration, bool, 0); | ||
42 | MODULE_PARM_DESC( | ||
43 | serdes_calibration, | ||
44 | "Perform Serdes calibration before starting RapidIO (default = 0)"); | ||
45 | |||
46 | static bool enable_ports = 1; | ||
47 | module_param(enable_ports, bool, 0); | ||
48 | MODULE_PARM_DESC( | ||
49 | enable_port, | ||
50 | "Enable RapidIO ports at boottime (default = 1)"); | ||
51 | |||
40 | /* | 52 | /* |
41 | * Main KeyStone RapidIO driver data | 53 | * Main KeyStone RapidIO driver data |
42 | */ | 54 | */ |
@@ -44,6 +56,10 @@ struct keystone_rio_data { | |||
44 | struct device *dev; | 56 | struct device *dev; |
45 | struct rio_mport *mport[KEYSTONE_RIO_MAX_PORT]; | 57 | struct rio_mport *mport[KEYSTONE_RIO_MAX_PORT]; |
46 | struct clk *clk; | 58 | struct clk *clk; |
59 | |||
60 | u32 started; | ||
61 | u32 calibrating; | ||
62 | |||
47 | struct completion lsu_completion; | 63 | struct completion lsu_completion; |
48 | struct mutex lsu_lock; | 64 | struct mutex lsu_lock; |
49 | u8 lsu_dio; | 65 | u8 lsu_dio; |
@@ -97,11 +113,19 @@ struct keystone_rio_data { | |||
97 | 113 | ||
98 | struct keystone_rio_board_controller_info board_rio_cfg; | 114 | struct keystone_rio_board_controller_info board_rio_cfg; |
99 | 115 | ||
100 | const struct keystone_serdes_ops *serdes_ops; | 116 | struct keystone_serdes_data serdes; |
101 | }; | 117 | }; |
102 | 118 | ||
103 | static void dbell_handler(struct keystone_rio_data *krio_priv); | 119 | static void dbell_handler( |
104 | static void keystone_rio_port_write_handler(struct keystone_rio_data *krio_priv); | 120 | struct keystone_rio_data *krio_priv); |
121 | static void keystone_rio_port_write_handler( | ||
122 | struct keystone_rio_data *krio_priv); | ||
123 | static void keystone_rio_handle_logical_error( | ||
124 | struct keystone_rio_data *krio_priv); | ||
125 | static int keystone_rio_setup_controller( | ||
126 | struct keystone_rio_data *krio_priv); | ||
127 | static void keystone_rio_shutdown_controller( | ||
128 | struct keystone_rio_data *krio_priv); | ||
105 | 129 | ||
106 | struct keystone_lane_config { | 130 | struct keystone_lane_config { |
107 | int start; /* lane start number of the port */ | 131 | int start; /* lane start number of the port */ |
@@ -147,8 +171,7 @@ static void special_interrupt_handler(int ics, struct keystone_rio_data *krio_pr | |||
147 | 171 | ||
148 | switch (ics) { | 172 | switch (ics) { |
149 | case KEYSTONE_RIO_MCAST_EVT_INT: | 173 | case KEYSTONE_RIO_MCAST_EVT_INT: |
150 | /* Multi-cast event control symbol interrupt | 174 | /* Multi-cast event control symbol interrupt received */ |
151 | received on any port */ | ||
152 | break; | 175 | break; |
153 | 176 | ||
154 | case KEYSTONE_RIO_PORT_WRITEIN_INT: | 177 | case KEYSTONE_RIO_PORT_WRITEIN_INT: |
@@ -158,6 +181,7 @@ static void special_interrupt_handler(int ics, struct keystone_rio_data *krio_pr | |||
158 | 181 | ||
159 | case KEYSTONE_RIO_EVT_CAP_ERROR_INT: | 182 | case KEYSTONE_RIO_EVT_CAP_ERROR_INT: |
160 | /* Logical layer error management event capture */ | 183 | /* Logical layer error management event capture */ |
184 | keystone_rio_handle_logical_error(krio_priv); | ||
161 | break; | 185 | break; |
162 | 186 | ||
163 | case KEYSTONE_RIO_PORT0_ERROR_INT: | 187 | case KEYSTONE_RIO_PORT0_ERROR_INT: |
@@ -193,7 +217,7 @@ static irqreturn_t rio_interrupt_handler(int irq, void *data) | |||
193 | /* Handle special interrupts (error, reset, special event) */ | 217 | /* Handle special interrupts (error, reset, special event) */ |
194 | while (pending_err_rst_evnt_int) { | 218 | while (pending_err_rst_evnt_int) { |
195 | u32 ics = __ffs(pending_err_rst_evnt_int); | 219 | u32 ics = __ffs(pending_err_rst_evnt_int); |
196 | pending_err_rst_evnt_int &= ~(1 << ics); | 220 | pending_err_rst_evnt_int &= ~BIT(ics); |
197 | special_interrupt_handler(ics, krio_priv); | 221 | special_interrupt_handler(ics, krio_priv); |
198 | } | 222 | } |
199 | 223 | ||
@@ -389,7 +413,7 @@ retry_transfer: | |||
389 | res = -EIO; | 413 | res = -EIO; |
390 | goto out; | 414 | goto out; |
391 | } | 415 | } |
392 | ndelay(1000); | 416 | ndelay(KEYSTONE_RIO_TIMEOUT_NSEC); |
393 | } | 417 | } |
394 | 418 | ||
395 | /* Get LCB and LTID, LSU reg 6 is already read */ | 419 | /* Get LCB and LTID, LSU reg 6 is already read */ |
@@ -418,7 +442,7 @@ retry_transfer: | |||
418 | * interrupt request = 1 */ | 442 | * interrupt request = 1 */ |
419 | __raw_writel(((port_id << 8) | 443 | __raw_writel(((port_id << 8) |
420 | | (KEYSTONE_RIO_LSU_PRIO << 4) | 444 | | (KEYSTONE_RIO_LSU_PRIO << 4) |
421 | | (size ? (1 << 10) : 0) | 445 | | (size ? BIT(10) : 0) |
422 | | ((u32) dest_id << 16) | 446 | | ((u32) dest_id << 16) |
423 | | 1), | 447 | | 1), |
424 | &(krio_priv->regs->lsu_reg[lsu].destid)); | 448 | &(krio_priv->regs->lsu_reg[lsu].destid)); |
@@ -454,7 +478,7 @@ retry_transfer: | |||
454 | res = -EIO; | 478 | res = -EIO; |
455 | break; | 479 | break; |
456 | } | 480 | } |
457 | ndelay(1000); | 481 | ndelay(KEYSTONE_RIO_TIMEOUT_NSEC); |
458 | } | 482 | } |
459 | out: | 483 | out: |
460 | mutex_unlock(&krio_priv->lsu_lock); | 484 | mutex_unlock(&krio_priv->lsu_lock); |
@@ -489,7 +513,7 @@ out: | |||
489 | * or canceled LSU transfer. | 513 | * or canceled LSU transfer. |
490 | */ | 514 | */ |
491 | if ((res == -EAGAIN) && (retry_count-- > 0)) { | 515 | if ((res == -EAGAIN) && (retry_count-- > 0)) { |
492 | ndelay(1000); | 516 | ndelay(KEYSTONE_RIO_TIMEOUT_NSEC); |
493 | goto retry_transfer; | 517 | goto retry_transfer; |
494 | } | 518 | } |
495 | 519 | ||
@@ -576,7 +600,7 @@ static inline int dbell_get(u32 *pending) | |||
576 | { | 600 | { |
577 | if (*pending) { | 601 | if (*pending) { |
578 | int n = __ffs(*pending); | 602 | int n = __ffs(*pending); |
579 | *pending &= ~(1 << n); | 603 | *pending &= ~BIT(n); |
580 | return n; | 604 | return n; |
581 | } else | 605 | } else |
582 | return -1; | 606 | return -1; |
@@ -704,7 +728,7 @@ static int keystone_rio_dbell_send(struct rio_mport *mport, | |||
704 | /* LSU Reg 4 - */ | 728 | /* LSU Reg 4 - */ |
705 | __raw_writel(((port_id << 8) | 729 | __raw_writel(((port_id << 8) |
706 | | (KEYSTONE_RIO_LSU_PRIO << 4) | 730 | | (KEYSTONE_RIO_LSU_PRIO << 4) |
707 | | ((mport->sys_size) ? (1 << 10) : 0) | 731 | | ((mport->sys_size) ? BIT(10) : 0) |
708 | | ((u32) dest_id << 16) | 732 | | ((u32) dest_id << 16) |
709 | | 1), | 733 | | 1), |
710 | &(krio_priv->regs->lsu_reg[lsu].destid)); | 734 | &(krio_priv->regs->lsu_reg[lsu].destid)); |
@@ -844,7 +868,7 @@ static inline int keystone_rio_maint_request(int port_id, | |||
844 | /* LSU Reg 4 - */ | 868 | /* LSU Reg 4 - */ |
845 | __raw_writel(((port_id << 8) | 869 | __raw_writel(((port_id << 8) |
846 | | (KEYSTONE_RIO_LSU_PRIO << 4) | 870 | | (KEYSTONE_RIO_LSU_PRIO << 4) |
847 | | (size ? (1 << 10) : 0) | 871 | | (size ? BIT(10) : 0) |
848 | | ((u32) dest_id << 16)), | 872 | | ((u32) dest_id << 16)), |
849 | &(krio_priv->regs->lsu_reg[lsu].destid)); | 873 | &(krio_priv->regs->lsu_reg[lsu].destid)); |
850 | 874 | ||
@@ -1013,7 +1037,7 @@ static int keystone_rio_get_lane_config(u32 ports, u32 path_mode) | |||
1013 | while (ports) { | 1037 | while (ports) { |
1014 | u32 lane; | 1038 | u32 lane; |
1015 | u32 port = __ffs(ports); | 1039 | u32 port = __ffs(ports); |
1016 | ports &= ~(1 << port); | 1040 | ports &= ~BIT(port); |
1017 | 1041 | ||
1018 | if (keystone_lane_configs[path_mode][port].start == -1) | 1042 | if (keystone_lane_configs[path_mode][port].start == -1) |
1019 | return -1; | 1043 | return -1; |
@@ -1024,6 +1048,7 @@ static int keystone_rio_get_lane_config(u32 ports, u32 path_mode) | |||
1024 | lanes |= KEYSTONE_SERDES_LANE(lane); | 1048 | lanes |= KEYSTONE_SERDES_LANE(lane); |
1025 | } | 1049 | } |
1026 | } | 1050 | } |
1051 | |||
1027 | return (int) lanes; | 1052 | return (int) lanes; |
1028 | } | 1053 | } |
1029 | 1054 | ||
@@ -1033,6 +1058,7 @@ static int keystone_rio_get_lane_config(u32 ports, u32 path_mode) | |||
1033 | * | 1058 | * |
1034 | * @port: RIO port | 1059 | * @port: RIO port |
1035 | * @start: if non null, lanes will be started | 1060 | * @start: if non null, lanes will be started |
1061 | * @init_rx: if non null, lanes Rx coefficients will be applied | ||
1036 | * | 1062 | * |
1037 | * Returns %0 on success or %1 if lane is not OK during the expected timeout | 1063 | * Returns %0 on success or %1 if lane is not OK during the expected timeout |
1038 | */ | 1064 | */ |
@@ -1040,30 +1066,26 @@ static int keystone_rio_lanes_init_and_wait(u32 port, int start, | |||
1040 | struct keystone_rio_data *krio_priv) | 1066 | struct keystone_rio_data *krio_priv) |
1041 | { | 1067 | { |
1042 | u32 path_mode = krio_priv->board_rio_cfg.path_mode; | 1068 | u32 path_mode = krio_priv->board_rio_cfg.path_mode; |
1043 | int lanes = keystone_rio_get_lane_config(BIT(port), path_mode); | 1069 | int lanes = keystone_rio_get_lane_config(BIT(port), path_mode); |
1044 | struct keystone_serdes_config *serdes_config = | ||
1045 | &(krio_priv->board_rio_cfg.serdes_config); | ||
1046 | int res; | 1070 | int res; |
1047 | 1071 | ||
1048 | dev_dbg(krio_priv->dev, | 1072 | dev_dbg(krio_priv->dev, |
1049 | "Initializing lane mask 0x%x for port %d", | 1073 | "initializing lane mask 0x%x for port %d", |
1050 | lanes, port); | 1074 | lanes, port); |
1051 | 1075 | ||
1052 | /* Eventually start the lanes */ | 1076 | /* Eventually start the lane */ |
1053 | if (start) { | 1077 | if (start) { |
1054 | dev_dbg(krio_priv->dev, | 1078 | dev_dbg(krio_priv->dev, |
1055 | "Starting lane mask 0x%x for port %d", | 1079 | "starting lane mask 0x%x for port %d", |
1056 | lanes, port); | 1080 | lanes, port); |
1057 | 1081 | ||
1058 | krio_priv->serdes_ops->start_tx_lanes((u32) lanes, | 1082 | krio_priv->serdes.ops->start_tx_lanes((u32) lanes, |
1059 | krio_priv->dev, | 1083 | &krio_priv->serdes); |
1060 | krio_priv->serdes_regs, | ||
1061 | serdes_config); | ||
1062 | } | 1084 | } |
1063 | 1085 | ||
1064 | /* Wait lanes to be OK */ | 1086 | /* Wait lanes to be OK */ |
1065 | res = krio_priv->serdes_ops->wait_lanes_ok(lanes, | 1087 | res = krio_priv->serdes.ops->wait_lanes_ok(lanes, |
1066 | krio_priv->serdes_regs); | 1088 | &krio_priv->serdes); |
1067 | if (res < 0) { | 1089 | if (res < 0) { |
1068 | dev_dbg(krio_priv->dev, | 1090 | dev_dbg(krio_priv->dev, |
1069 | "port %d lane mask 0x%x is not OK\n", | 1091 | "port %d lane mask 0x%x is not OK\n", |
@@ -1075,6 +1097,51 @@ static int keystone_rio_lanes_init_and_wait(u32 port, int start, | |||
1075 | return 0; | 1097 | return 0; |
1076 | } | 1098 | } |
1077 | 1099 | ||
1100 | /* | ||
1101 | * SerDes main configuration | ||
1102 | */ | ||
1103 | static int keystone_rio_serdes_init(u32 baud, | ||
1104 | int calibrate, | ||
1105 | struct keystone_rio_data *krio_priv) | ||
1106 | { | ||
1107 | u32 path_mode = krio_priv->board_rio_cfg.path_mode; | ||
1108 | u32 ports = krio_priv->board_rio_cfg.ports; | ||
1109 | u32 lanes; | ||
1110 | int res; | ||
1111 | |||
1112 | /* Retrieve lane termination */ | ||
1113 | res = keystone_rio_get_lane_config(ports, path_mode); | ||
1114 | if (res <= 0) | ||
1115 | return res; | ||
1116 | |||
1117 | /* Initialize SerDes */ | ||
1118 | lanes = (u32) res; | ||
1119 | res = krio_priv->serdes.ops->config_lanes(lanes, | ||
1120 | baud, | ||
1121 | &krio_priv->serdes); | ||
1122 | if (res < 0) | ||
1123 | return res; | ||
1124 | |||
1125 | /* Check if we need to perform SerDes calibration */ | ||
1126 | if ((calibrate) && (!krio_priv->calibrating)) { | ||
1127 | |||
1128 | krio_priv->calibrating = 1; | ||
1129 | |||
1130 | /* Set calibration timeout */ | ||
1131 | krio_priv->board_rio_cfg.serdes_config.cal_timeout = | ||
1132 | krio_priv->board_rio_cfg.port_register_timeout; | ||
1133 | |||
1134 | /* Do the calibration */ | ||
1135 | krio_priv->serdes.ops->calibrate_lanes( | ||
1136 | lanes, | ||
1137 | &krio_priv->serdes); | ||
1138 | |||
1139 | krio_priv->calibrating = 0; | ||
1140 | } | ||
1141 | |||
1142 | return 0; | ||
1143 | } | ||
1144 | |||
1078 | /** | 1145 | /** |
1079 | * keystone_rio_hw_init - Configure a RapidIO controller | 1146 | * keystone_rio_hw_init - Configure a RapidIO controller |
1080 | * @baud: serdes baudrate | 1147 | * @baud: serdes baudrate |
@@ -1085,8 +1152,6 @@ static int keystone_rio_hw_init(u32 baud, struct keystone_rio_data *krio_priv) | |||
1085 | { | 1152 | { |
1086 | struct keystone_serdes_config *serdes_config | 1153 | struct keystone_serdes_config *serdes_config |
1087 | = &(krio_priv->board_rio_cfg.serdes_config); | 1154 | = &(krio_priv->board_rio_cfg.serdes_config); |
1088 | u32 path_mode = krio_priv->board_rio_cfg.path_mode; | ||
1089 | u32 ports = krio_priv->board_rio_cfg.ports; | ||
1090 | u32 val; | 1155 | u32 val; |
1091 | u32 block; | 1156 | u32 block; |
1092 | int res = 0; | 1157 | int res = 0; |
@@ -1097,7 +1162,7 @@ static int keystone_rio_hw_init(u32 baud, struct keystone_rio_data *krio_priv) | |||
1097 | for (block = 0; block <= KEYSTONE_RIO_BLK_NUM; block++) | 1162 | for (block = 0; block <= KEYSTONE_RIO_BLK_NUM; block++) |
1098 | __raw_writel(0, &(krio_priv->regs->blk[block].enable)); | 1163 | __raw_writel(0, &(krio_priv->regs->blk[block].enable)); |
1099 | 1164 | ||
1100 | ndelay(1000); | 1165 | ndelay(KEYSTONE_RIO_TIMEOUT_NSEC); |
1101 | 1166 | ||
1102 | /* Set sRIO out of reset */ | 1167 | /* Set sRIO out of reset */ |
1103 | __raw_writel((KEYSTONE_RIO_PER_RESTORE | KEYSTONE_RIO_PER_FREE), | 1168 | __raw_writel((KEYSTONE_RIO_PER_RESTORE | KEYSTONE_RIO_PER_FREE), |
@@ -1130,20 +1195,11 @@ static int keystone_rio_hw_init(u32 baud, struct keystone_rio_data *krio_priv) | |||
1130 | BIT(21) | BIT(8) : 0), | 1195 | BIT(21) | BIT(8) : 0), |
1131 | &krio_priv->regs->per_set_cntl); | 1196 | &krio_priv->regs->per_set_cntl); |
1132 | 1197 | ||
1133 | /* SerDes main configuration */ | 1198 | /* Initialize SerDes and eventually perform their calibration */ |
1134 | res = keystone_rio_get_lane_config(ports, path_mode); | 1199 | res = keystone_rio_serdes_init( |
1135 | if (res > 0) { | 1200 | baud, |
1136 | u32 lanes = (u32) res; | 1201 | krio_priv->board_rio_cfg.serdes_calibration, |
1137 | 1202 | krio_priv); | |
1138 | /* Initialize Serdes */ | ||
1139 | res = krio_priv->serdes_ops->config_lanes( | ||
1140 | lanes, | ||
1141 | baud, | ||
1142 | krio_priv->dev, | ||
1143 | krio_priv->serdes_regs, | ||
1144 | krio_priv->serdes_sts_reg, | ||
1145 | serdes_config); | ||
1146 | } | ||
1147 | 1203 | ||
1148 | if (res < 0) { | 1204 | if (res < 0) { |
1149 | dev_err(krio_priv->dev, "initialization of SerDes failed\n"); | 1205 | dev_err(krio_priv->dev, "initialization of SerDes failed\n"); |
@@ -1211,48 +1267,53 @@ static int keystone_rio_hw_init(u32 baud, struct keystone_rio_data *krio_priv) | |||
1211 | KEYSTONE_RIO_SP_HDR_EP_REC_ID); | 1267 | KEYSTONE_RIO_SP_HDR_EP_REC_ID); |
1212 | __raw_writel(val, &krio_priv->serial_port_regs->sp_maint_blk_hdr); | 1268 | __raw_writel(val, &krio_priv->serial_port_regs->sp_maint_blk_hdr); |
1213 | 1269 | ||
1214 | /* clear high bits of local config space base addr */ | 1270 | /* Clear high bits of local config space base addr */ |
1215 | __raw_writel(0x00000000, &krio_priv->car_csr_regs->local_cfg_hbar); | 1271 | __raw_writel(0x00000000, &krio_priv->car_csr_regs->local_cfg_hbar); |
1216 | 1272 | ||
1217 | /* set local config space base addr */ | 1273 | /* Set local config space base addr */ |
1218 | __raw_writel(0x00520000, &krio_priv->car_csr_regs->local_cfg_bar); | 1274 | __raw_writel(0x00520000, &krio_priv->car_csr_regs->local_cfg_bar); |
1219 | 1275 | ||
1220 | /* Enable HOST BIT(31) & MASTER_ENABLE BIT(30) bits */ | 1276 | /* Enable HOST BIT(31) & MASTER_ENABLE BIT(30) bits */ |
1221 | __raw_writel(0xc0000000, &krio_priv->serial_port_regs->sp_gen_ctl); | 1277 | __raw_writel(0xc0000000, &krio_priv->serial_port_regs->sp_gen_ctl); |
1222 | 1278 | ||
1223 | /* set link timeout value */ | 1279 | /* Set link timeout value */ |
1224 | __raw_writel(0x000FFF00, | 1280 | __raw_writel(0x000FFF00, |
1225 | &krio_priv->serial_port_regs->sp_link_timeout_ctl); | 1281 | &krio_priv->serial_port_regs->sp_link_timeout_ctl); |
1226 | 1282 | ||
1227 | /* set response timeout value */ | 1283 | /* Set response timeout value */ |
1228 | __raw_writel(0x000FFF00, | 1284 | __raw_writel(0x000FFF00, |
1229 | &krio_priv->serial_port_regs->sp_rsp_timeout_ctl); | 1285 | &krio_priv->serial_port_regs->sp_rsp_timeout_ctl); |
1230 | 1286 | ||
1231 | /* allows SELF_RESET and PWDN_PORT resets to clear stcky reg bits */ | 1287 | /* Allows SELF_RESET and PWDN_PORT resets to clear stcky reg bits */ |
1232 | __raw_writel(0x00000001, &krio_priv->link_regs->reg_rst_ctl); | 1288 | __raw_writel(0x00000001, &krio_priv->link_regs->reg_rst_ctl); |
1233 | 1289 | ||
1234 | /* clear all errors */ | 1290 | /* Clear all errors */ |
1235 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->err_det); | 1291 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->err_det); |
1236 | 1292 | ||
1237 | /* disable all error detection */ | 1293 | /* Disable all error detection */ |
1238 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->err_en); | 1294 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->err_en); |
1239 | __raw_writel(0x00000000, &krio_priv->link_regs->local_err_en); | 1295 | if (krio_priv->board_rio_cfg.pkt_forwarding) |
1296 | __raw_writel(0x00000000, | ||
1297 | &krio_priv->link_regs->local_err_en); | ||
1298 | else | ||
1299 | __raw_writel(BIT(24) | BIT(25) | BIT(31), | ||
1300 | &krio_priv->err_mgmt_regs->err_en); | ||
1240 | 1301 | ||
1241 | /* set err det block header */ | 1302 | /* Set err det block header */ |
1242 | val = (((KEYSTONE_RIO_ERR_HDR_NEXT_BLK_PTR & 0xffff) << 16) | | 1303 | val = (((KEYSTONE_RIO_ERR_HDR_NEXT_BLK_PTR & 0xffff) << 16) | |
1243 | KEYSTONE_RIO_ERR_EXT_FEAT_ID); | 1304 | KEYSTONE_RIO_ERR_EXT_FEAT_ID); |
1244 | __raw_writel(val, &krio_priv->err_mgmt_regs->err_report_blk_hdr); | 1305 | __raw_writel(val, &krio_priv->err_mgmt_regs->err_report_blk_hdr); |
1245 | 1306 | ||
1246 | /* clear msb of err captured addr reg */ | 1307 | /* Clear msb of err captured addr reg */ |
1247 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->h_addr_capt); | 1308 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->h_addr_capt); |
1248 | 1309 | ||
1249 | /* clear lsb of err captured addr reg */ | 1310 | /* Clear lsb of err captured addr reg */ |
1250 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->addr_capt); | 1311 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->addr_capt); |
1251 | 1312 | ||
1252 | /* clear err captured source and dest DevID reg */ | 1313 | /* Clear err captured source and dest DevID reg */ |
1253 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->id_capt); | 1314 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->id_capt); |
1254 | 1315 | ||
1255 | /* clear err captured packet info */ | 1316 | /* Clear err captured packet info */ |
1256 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->ctrl_capt); | 1317 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->ctrl_capt); |
1257 | 1318 | ||
1258 | __raw_writel(0x41004141, &krio_priv->phy_regs->phy_sp[0].__rsvd[3]); | 1319 | __raw_writel(0x41004141, &krio_priv->phy_regs->phy_sp[0].__rsvd[3]); |
@@ -1280,6 +1341,7 @@ static int keystone_rio_hw_init(u32 baud, struct keystone_rio_data *krio_priv) | |||
1280 | __raw_writel(0x0003ffff, &(krio_priv->regs->pkt_fwd_cntl[i].pf_8b)); | 1341 | __raw_writel(0x0003ffff, &(krio_priv->regs->pkt_fwd_cntl[i].pf_8b)); |
1281 | } | 1342 | } |
1282 | } | 1343 | } |
1344 | |||
1283 | if (!krio_priv->board_rio_cfg.pkt_forwarding) | 1345 | if (!krio_priv->board_rio_cfg.pkt_forwarding) |
1284 | dev_info(krio_priv->dev, "packet forwarding disabled\n"); | 1346 | dev_info(krio_priv->dev, "packet forwarding disabled\n"); |
1285 | 1347 | ||
@@ -1315,12 +1377,38 @@ static void keystone_rio_stop(struct keystone_rio_data *krio_priv) | |||
1315 | 1377 | ||
1316 | /* Disable PEREN bit to stop all new logical layer transactions */ | 1378 | /* Disable PEREN bit to stop all new logical layer transactions */ |
1317 | val = __raw_readl(&krio_priv->regs->pcr); | 1379 | val = __raw_readl(&krio_priv->regs->pcr); |
1318 | val &= ~KEYSTONE_RIO_PER_EN; | 1380 | __raw_writel(val & ~KEYSTONE_RIO_PER_EN, &krio_priv->regs->pcr); |
1319 | __raw_writel(val, &krio_priv->regs->pcr); | 1381 | |
1382 | /* Clear BOOT_COMPLETE bit */ | ||
1383 | val = __raw_readl(&krio_priv->regs->per_set_cntl); | ||
1384 | __raw_writel(val & ~KEYSTONE_RIO_BOOT_COMPLETE, | ||
1385 | &krio_priv->regs->per_set_cntl); | ||
1320 | } | 1386 | } |
1321 | 1387 | ||
1322 | static int keystone_rio_get_remote_port(u8 port, | 1388 | static void keystone_rio_handle_logical_error( |
1323 | struct keystone_rio_data *krio_priv) | 1389 | struct keystone_rio_data *krio_priv) |
1390 | { | ||
1391 | u32 err_det = __raw_readl(&krio_priv->err_mgmt_regs->err_det); | ||
1392 | |||
1393 | if (!err_det) | ||
1394 | return; | ||
1395 | |||
1396 | while (err_det) { | ||
1397 | u32 err = __ffs(err_det); | ||
1398 | err_det &= ~BIT(err); | ||
1399 | |||
1400 | /* TODO: perform better error management here */ | ||
1401 | dev_warn(krio_priv->dev, | ||
1402 | "logical layer error %d detected\n", err); | ||
1403 | } | ||
1404 | |||
1405 | /* Acknowledge logical layer error */ | ||
1406 | __raw_writel(0x00000000, &krio_priv->err_mgmt_regs->err_det); | ||
1407 | } | ||
1408 | |||
1409 | static int keystone_rio_get_remote_port( | ||
1410 | u8 port, | ||
1411 | struct keystone_rio_data *krio_priv) | ||
1324 | { | 1412 | { |
1325 | int res; | 1413 | int res; |
1326 | u32 value; | 1414 | u32 value; |
@@ -1526,49 +1614,50 @@ static void keystone_rio_pe_dpc(struct work_struct *work) | |||
1526 | to_delayed_work(work), struct keystone_rio_data, pe_work); | 1614 | to_delayed_work(work), struct keystone_rio_data, pe_work); |
1527 | u32 port; | 1615 | u32 port; |
1528 | 1616 | ||
1529 | dev_dbg(krio_priv->dev, "errors on ports: 0x%x\n", krio_priv->pe_ports); | 1617 | dev_dbg(krio_priv->dev, |
1618 | "ER errors on ports: 0x%x\n", | ||
1619 | krio_priv->pe_ports); | ||
1530 | 1620 | ||
1531 | for (port = 0; port < KEYSTONE_RIO_MAX_PORT; port++) { | 1621 | for (port = 0; port < KEYSTONE_RIO_MAX_PORT; port++) { |
1532 | if (test_and_clear_bit(port, (void *)&krio_priv->pe_ports)) { | ||
1533 | 1622 | ||
1623 | /* Skip port if we are currently registering it */ | ||
1624 | if (krio_priv->ports_registering & BIT(port)) | ||
1625 | continue; | ||
1626 | |||
1627 | if (test_and_clear_bit(port, (void *)&krio_priv->pe_ports)) { | ||
1534 | /* Wait lanes to be OK */ | 1628 | /* Wait lanes to be OK */ |
1535 | if (keystone_rio_lanes_init_and_wait(port, 0, | 1629 | if (keystone_rio_lanes_init_and_wait(port, 0, |
1536 | krio_priv)) { | 1630 | krio_priv)) { |
1537 | dev_dbg(krio_priv->dev, | 1631 | dev_dbg(krio_priv->dev, |
1538 | "port %d: lanes are not OK\n", port); | 1632 | "ER port %d: lanes are not OK\n", port); |
1539 | goto retry; | 1633 | krio_priv->pe_ports |= BIT(port); |
1540 | } | 1634 | } |
1541 | 1635 | ||
1542 | /* Recover from port error state */ | 1636 | /* Recover from port error state */ |
1543 | if (keystone_rio_port_error_recovery(port, | 1637 | if (keystone_rio_port_error_recovery(port, |
1544 | krio_priv)) { | 1638 | krio_priv)) { |
1545 | dev_dbg(krio_priv->dev, | 1639 | dev_dbg(krio_priv->dev, |
1546 | "port %d: failed to perform error" | 1640 | "ER port %d: failed to perform error" |
1547 | " recovery\n", | 1641 | " recovery\n", |
1548 | port); | 1642 | port); |
1549 | goto retry; | ||
1550 | } | ||
1551 | |||
1552 | /* Continue to next port */ | ||
1553 | continue; | ||
1554 | retry: | ||
1555 | /* | ||
1556 | * If error recovery failed schedule another one if | ||
1557 | * there is time left | ||
1558 | */ | ||
1559 | if (krio_priv->pe_cnt-- > 1) { | ||
1560 | krio_priv->pe_ports |= BIT(port); | 1643 | krio_priv->pe_ports |= BIT(port); |
1561 | schedule_delayed_work( | ||
1562 | &krio_priv->pe_work, | ||
1563 | KEYSTONE_RIO_REGISTER_DELAY); | ||
1564 | } else { | ||
1565 | dev_err(krio_priv->dev, | ||
1566 | "port %d: failed to recover from " | ||
1567 | "errors\n", | ||
1568 | port); | ||
1569 | } | 1644 | } |
1570 | } | 1645 | } |
1571 | } | 1646 | } |
1647 | |||
1648 | /* If error recovery failed delay another one if there is time left */ | ||
1649 | if (krio_priv->pe_ports) { | ||
1650 | if (krio_priv->pe_cnt-- > 1) { | ||
1651 | schedule_delayed_work( | ||
1652 | &krio_priv->pe_work, | ||
1653 | KEYSTONE_RIO_REGISTER_DELAY); | ||
1654 | } else { | ||
1655 | dev_err(krio_priv->dev, | ||
1656 | "ER port %d: failed to recover from " | ||
1657 | "errors\n", | ||
1658 | port); | ||
1659 | } | ||
1660 | } | ||
1572 | } | 1661 | } |
1573 | 1662 | ||
1574 | /** | 1663 | /** |
@@ -1646,9 +1735,8 @@ port_phy_error: | |||
1646 | "fix unstable lane mask 0x%x for port %d\n", | 1735 | "fix unstable lane mask 0x%x for port %d\n", |
1647 | lanes, port); | 1736 | lanes, port); |
1648 | 1737 | ||
1649 | krio_priv->serdes_ops->fix_unstable_lanes(lanes, | 1738 | krio_priv->serdes.ops->fix_unstable_lanes(lanes, |
1650 | krio_priv->dev, | 1739 | &krio_priv->serdes); |
1651 | krio_priv->serdes_regs); | ||
1652 | port_error: | 1740 | port_error: |
1653 | return -EIO; | 1741 | return -EIO; |
1654 | } | 1742 | } |
@@ -1657,19 +1745,38 @@ port_error: | |||
1657 | * keystone_rio_port_disable - Disable a RapidIO port | 1745 | * keystone_rio_port_disable - Disable a RapidIO port |
1658 | * @port: index of the port to configure | 1746 | * @port: index of the port to configure |
1659 | */ | 1747 | */ |
1660 | static void keystone_rio_port_disable(u32 port, struct keystone_rio_data *krio_priv) | 1748 | static void keystone_rio_port_disable( |
1749 | u32 port, | ||
1750 | struct keystone_rio_data *krio_priv) | ||
1661 | { | 1751 | { |
1662 | /* Disable port */ | 1752 | /* Disable port */ |
1663 | __raw_writel(0x800000, &(krio_priv->serial_port_regs->sp[port].ctl)); | 1753 | __raw_writel(0x800000, &(krio_priv->serial_port_regs->sp[port].ctl)); |
1664 | } | 1754 | } |
1665 | 1755 | ||
1666 | /** | 1756 | /** |
1757 | * keystone_rio_port_enable - Enable a RapidIO port | ||
1758 | * @port: index of the port to configure | ||
1759 | */ | ||
1760 | static void keystone_rio_port_enable( | ||
1761 | u32 port, | ||
1762 | struct keystone_rio_data *krio_priv) | ||
1763 | { | ||
1764 | /* Enable port in input and output */ | ||
1765 | __raw_writel(0x600000, &(krio_priv->serial_port_regs->sp[port].ctl)); | ||
1766 | } | ||
1767 | |||
1768 | /** | ||
1667 | * keystone_rio_port_init - Configure a RapidIO port | 1769 | * keystone_rio_port_init - Configure a RapidIO port |
1668 | * @port: index of the port to configure | 1770 | * @port: index of the port to configure |
1669 | * @mode: serdes configuration | 1771 | * @mode: serdes configuration |
1670 | */ | 1772 | */ |
1671 | static int keystone_rio_port_init(u32 port, u32 path_mode, struct keystone_rio_data *krio_priv) | 1773 | static int keystone_rio_port_init( |
1774 | u32 port, | ||
1775 | u32 path_mode, | ||
1776 | struct keystone_rio_data *krio_priv) | ||
1672 | { | 1777 | { |
1778 | u32 val; | ||
1779 | |||
1673 | if (port >= KEYSTONE_RIO_MAX_PORT) | 1780 | if (port >= KEYSTONE_RIO_MAX_PORT) |
1674 | return -EINVAL; | 1781 | return -EINVAL; |
1675 | 1782 | ||
@@ -1684,73 +1791,9 @@ static int keystone_rio_port_init(u32 port, u32 path_mode, struct keystone_rio_d | |||
1684 | /* Increase the number of valid code-groups required for sync */ | 1791 | /* Increase the number of valid code-groups required for sync */ |
1685 | __raw_writel(0x0f030300, &(krio_priv->phy_regs->phy_sp[port].vmin_exp)); | 1792 | __raw_writel(0x0f030300, &(krio_priv->phy_regs->phy_sp[port].vmin_exp)); |
1686 | 1793 | ||
1687 | /* Enable port in input and output */ | ||
1688 | __raw_writel(0x600000, &(krio_priv->serial_port_regs->sp[port].ctl)); | ||
1689 | |||
1690 | /* Program channel allocation to ports (1x, 2x or 4x) */ | 1794 | /* Program channel allocation to ports (1x, 2x or 4x) */ |
1691 | __raw_writel(path_mode, &(krio_priv->phy_regs->phy_sp[port].path_ctl)); | 1795 | __raw_writel(path_mode, &(krio_priv->phy_regs->phy_sp[port].path_ctl)); |
1692 | 1796 | ||
1693 | return 0; | ||
1694 | } | ||
1695 | |||
1696 | /** | ||
1697 | * keystone_rio_port_set_routing - Configure routing for a RapidIO port | ||
1698 | * @port: index of the port to configure | ||
1699 | */ | ||
1700 | static void keystone_rio_port_set_routing(u32 port, struct keystone_rio_data *krio_priv) | ||
1701 | { | ||
1702 | u32 base_dev_id = krio_priv->board_rio_cfg.size ? | ||
1703 | __raw_readl(&krio_priv->car_csr_regs->base_dev_id) & 0xffff : | ||
1704 | (__raw_readl(&krio_priv->car_csr_regs->base_dev_id) >> 16) & 0xff; | ||
1705 | |||
1706 | u32 brr = KEYSTONE_RIO_PKT_FW_BRR_NUM; | ||
1707 | |||
1708 | /* Enable routing to LLM for this BRR and port */ | ||
1709 | __raw_writel(0x84000000, | ||
1710 | &(krio_priv->transport_regs->transport_sp[port].base_route[brr].ctl)); | ||
1711 | |||
1712 | /* | ||
1713 | * Configure the Base Routing Register (BRR) to ensure that all packets | ||
1714 | * matching our DevId are admitted. | ||
1715 | */ | ||
1716 | __raw_writel((base_dev_id << 16) | | ||
1717 | (krio_priv->board_rio_cfg.size ? 0xffff : 0xff), | ||
1718 | &(krio_priv->transport_regs->transport_sp[port].base_route[brr].pattern_match)); | ||
1719 | |||
1720 | dev_dbg(krio_priv->dev, "pattern_match = 0x%x for BRR %d\n", | ||
1721 | __raw_readl(&krio_priv->transport_regs->transport_sp[port].base_route[brr].pattern_match), | ||
1722 | brr); | ||
1723 | |||
1724 | /* Enable routing to LLM for this BRR and port */ | ||
1725 | brr += 1; | ||
1726 | __raw_writel(0x84000000, | ||
1727 | &(krio_priv->transport_regs->transport_sp[port].base_route[brr].ctl)); | ||
1728 | |||
1729 | /* | ||
1730 | * Configure the Base Routing Register (BRR) to ensure that all broadcast | ||
1731 | * packets are admitted as well. | ||
1732 | */ | ||
1733 | __raw_writel((0xffff << 16) | | ||
1734 | (krio_priv->board_rio_cfg.size ? 0xffff : 0xff), | ||
1735 | &(krio_priv->transport_regs->transport_sp[port].base_route[brr].pattern_match)); | ||
1736 | |||
1737 | dev_dbg(krio_priv->dev, "pattern_match = 0x%x for BRR %d\n", | ||
1738 | __raw_readl(&krio_priv->transport_regs->transport_sp[port].base_route[brr].pattern_match), | ||
1739 | brr); | ||
1740 | |||
1741 | /* Set multicast and packet forwarding mode */ | ||
1742 | __raw_writel(0x00209000, | ||
1743 | &(krio_priv->transport_regs->transport_sp[port].control)); | ||
1744 | } | ||
1745 | |||
1746 | /** | ||
1747 | * keystone_rio_port_activate - Start using a RapidIO port | ||
1748 | * @port: index of the port to configure | ||
1749 | */ | ||
1750 | static int keystone_rio_port_activate(u32 port, struct keystone_rio_data *krio_priv) | ||
1751 | { | ||
1752 | u32 val; | ||
1753 | |||
1754 | /* | 1797 | /* |
1755 | * Disable all errors reporting if using packet forwarding | 1798 | * Disable all errors reporting if using packet forwarding |
1756 | * otherwise enable them. | 1799 | * otherwise enable them. |
@@ -1766,7 +1809,7 @@ static int keystone_rio_port_activate(u32 port, struct keystone_rio_data *krio_p | |||
1766 | 1809 | ||
1767 | /* Enable interrupt for reset request */ | 1810 | /* Enable interrupt for reset request */ |
1768 | val = __raw_readl(&(krio_priv->evt_mgmt_regs->evt_mgmt_rst_int_en)); | 1811 | val = __raw_readl(&(krio_priv->evt_mgmt_regs->evt_mgmt_rst_int_en)); |
1769 | __raw_writel(val | (1 << port), | 1812 | __raw_writel(val | BIT(port), |
1770 | &(krio_priv->evt_mgmt_regs->evt_mgmt_rst_int_en)); | 1813 | &(krio_priv->evt_mgmt_regs->evt_mgmt_rst_int_en)); |
1771 | 1814 | ||
1772 | /* Enable all PLM interrupts */ | 1815 | /* Enable all PLM interrupts */ |
@@ -1803,6 +1846,63 @@ static int keystone_rio_port_activate(u32 port, struct keystone_rio_data *krio_p | |||
1803 | return 0; | 1846 | return 0; |
1804 | } | 1847 | } |
1805 | 1848 | ||
1849 | /** | ||
1850 | * keystone_rio_port_set_routing - Configure routing for a RapidIO port | ||
1851 | * @port: index of the port to configure | ||
1852 | */ | ||
1853 | static void keystone_rio_port_set_routing( | ||
1854 | u32 port, | ||
1855 | struct keystone_rio_data *krio_priv) | ||
1856 | { | ||
1857 | struct keystone_rio_transport_layer_regs *t = krio_priv->transport_regs; | ||
1858 | u32 base_dev_id = krio_priv->board_rio_cfg.size ? | ||
1859 | __raw_readl(&krio_priv->car_csr_regs->base_dev_id) & 0xffff : | ||
1860 | (__raw_readl(&krio_priv->car_csr_regs->base_dev_id) >> 16) | ||
1861 | & 0xff; | ||
1862 | u32 brr = KEYSTONE_RIO_PKT_FW_BRR_NUM; | ||
1863 | |||
1864 | /* | ||
1865 | * Configure the Base Routing Register (BRR) to ensure that all packets | ||
1866 | * matching our DevId are admitted. | ||
1867 | */ | ||
1868 | __raw_writel((base_dev_id << 16) | | ||
1869 | (krio_priv->board_rio_cfg.size ? 0xffff : 0xff), | ||
1870 | &(t->transport_sp[port].base_route[brr].pattern_match)); | ||
1871 | |||
1872 | dev_dbg(krio_priv->dev, "pattern_match = 0x%x for BRR %d\n", | ||
1873 | __raw_readl( | ||
1874 | &(t->transport_sp[port].base_route[brr].pattern_match)), | ||
1875 | brr); | ||
1876 | |||
1877 | /* Enable routing to LLM for this BRR and port */ | ||
1878 | __raw_writel(0x84000000, | ||
1879 | &(t->transport_sp[port].base_route[brr].ctl)); | ||
1880 | |||
1881 | /* Use next BRR */ | ||
1882 | brr += 1; | ||
1883 | |||
1884 | /* | ||
1885 | * Configure the Base Routing Register (BRR) to ensure that all | ||
1886 | * broadcast packets are admitted as well. | ||
1887 | */ | ||
1888 | __raw_writel((0xffff << 16) | | ||
1889 | (krio_priv->board_rio_cfg.size ? 0xffff : 0xff), | ||
1890 | &(t->transport_sp[port].base_route[brr].pattern_match)); | ||
1891 | |||
1892 | dev_dbg(krio_priv->dev, "pattern_match = 0x%x for BRR %d\n", | ||
1893 | __raw_readl( | ||
1894 | &(t->transport_sp[port].base_route[brr].pattern_match)), | ||
1895 | brr); | ||
1896 | |||
1897 | /* Enable routing to LLM for this BRR and port */ | ||
1898 | __raw_writel(0x84000000, | ||
1899 | &(t->transport_sp[port].base_route[brr].ctl)); | ||
1900 | |||
1901 | /* Set multicast and packet forwarding mode */ | ||
1902 | __raw_writel(0x00209000, | ||
1903 | &(t->transport_sp[port].control)); | ||
1904 | } | ||
1905 | |||
1806 | /*------------------------- Configuration space mngt ----------------------*/ | 1906 | /*------------------------- Configuration space mngt ----------------------*/ |
1807 | 1907 | ||
1808 | /** | 1908 | /** |
@@ -2477,24 +2577,17 @@ static int keystone_rio_open_inb_mbox(struct rio_mport *mport, | |||
2477 | return res; | 2577 | return res; |
2478 | } | 2578 | } |
2479 | 2579 | ||
2480 | /** | 2580 | static void keystone_rio_close_rx_mbox(int mbox, |
2481 | * keystone_rio_close_inb_mbox - Shut down KeyStone inbound mailbox | 2581 | struct keystone_rio_data *krio_priv) |
2482 | * @mport: Master port implementing the inbound message unit | ||
2483 | * @mbox: Mailbox to close | ||
2484 | * | ||
2485 | * Disables the outbound message unit, stop queues and free all resources | ||
2486 | */ | ||
2487 | static void keystone_rio_close_inb_mbox(struct rio_mport *mport, int mbox) | ||
2488 | { | 2582 | { |
2489 | struct keystone_rio_data *krio_priv = mport->priv; | ||
2490 | struct keystone_rio_mbox_info *rx_mbox = &krio_priv->rx_mbox[mbox]; | 2583 | struct keystone_rio_mbox_info *rx_mbox = &krio_priv->rx_mbox[mbox]; |
2491 | 2584 | ||
2492 | dev_info(krio_priv->dev, "close inb mbox: mport = 0x%x, mbox = %d\n", | 2585 | if (mbox >= KEYSTONE_RIO_MAX_MBOX) |
2493 | (u32) mport, mbox); | 2586 | return; |
2494 | 2587 | ||
2495 | rx_mbox->running = 0; | 2588 | rx_mbox->running = 0; |
2496 | 2589 | ||
2497 | if (!(rx_mbox->port)) | 2590 | if (!rx_mbox->port) |
2498 | return; | 2591 | return; |
2499 | 2592 | ||
2500 | rx_mbox->port = NULL; | 2593 | rx_mbox->port = NULL; |
@@ -2504,8 +2597,23 @@ static void keystone_rio_close_inb_mbox(struct rio_mport *mport, int mbox) | |||
2504 | keystone_rio_free_rxu_map(rx_mbox->rxu_map_id[1], krio_priv); | 2597 | keystone_rio_free_rxu_map(rx_mbox->rxu_map_id[1], krio_priv); |
2505 | 2598 | ||
2506 | keystone_rio_mp_inb_exit(mbox, krio_priv); | 2599 | keystone_rio_mp_inb_exit(mbox, krio_priv); |
2600 | } | ||
2507 | 2601 | ||
2508 | return; | 2602 | /** |
2603 | * keystone_rio_close_inb_mbox - Shutdown KeyStone inbound mailbox | ||
2604 | * @mport: Master port implementing the inbound message unit | ||
2605 | * @mbox: Mailbox to close | ||
2606 | * | ||
2607 | * Disables the outbound message unit, stop queues and free all resources | ||
2608 | */ | ||
2609 | static void keystone_rio_close_inb_mbox(struct rio_mport *mport, int mbox) | ||
2610 | { | ||
2611 | struct keystone_rio_data *krio_priv = mport->priv; | ||
2612 | |||
2613 | dev_info(krio_priv->dev, "close inb mbox: mport = 0x%x, mbox = %d\n", | ||
2614 | (u32) mport, mbox); | ||
2615 | |||
2616 | keystone_rio_close_rx_mbox(mbox, krio_priv); | ||
2509 | } | 2617 | } |
2510 | 2618 | ||
2511 | /** | 2619 | /** |
@@ -2719,8 +2827,26 @@ static int keystone_rio_open_outb_mbox(struct rio_mport *mport, | |||
2719 | return 0; | 2827 | return 0; |
2720 | } | 2828 | } |
2721 | 2829 | ||
2830 | static void keystone_rio_close_tx_mbox(int mbox, | ||
2831 | struct keystone_rio_data *krio_priv) | ||
2832 | { | ||
2833 | struct keystone_rio_mbox_info *tx_mbox = &(krio_priv->tx_mbox[mbox]); | ||
2834 | |||
2835 | if (mbox >= KEYSTONE_RIO_MAX_MBOX) | ||
2836 | return; | ||
2837 | |||
2838 | tx_mbox->running = 0; | ||
2839 | |||
2840 | if (!tx_mbox->port) | ||
2841 | return; | ||
2842 | |||
2843 | tx_mbox->port = NULL; | ||
2844 | |||
2845 | keystone_rio_mp_outb_exit(krio_priv); | ||
2846 | } | ||
2847 | |||
2722 | /** | 2848 | /** |
2723 | * keystone_rio_close_outb_mbox - Shut down KeyStone outbound mailbox | 2849 | * keystone_rio_close_outb_mbox - Shutdown KeyStone outbound mailbox |
2724 | * @mport: Master port implementing the outbound message unit | 2850 | * @mport: Master port implementing the outbound message unit |
2725 | * @mbox: Mailbox to close | 2851 | * @mbox: Mailbox to close |
2726 | * | 2852 | * |
@@ -2729,20 +2855,11 @@ static int keystone_rio_open_outb_mbox(struct rio_mport *mport, | |||
2729 | static void keystone_rio_close_outb_mbox(struct rio_mport *mport, int mbox) | 2855 | static void keystone_rio_close_outb_mbox(struct rio_mport *mport, int mbox) |
2730 | { | 2856 | { |
2731 | struct keystone_rio_data *krio_priv = mport->priv; | 2857 | struct keystone_rio_data *krio_priv = mport->priv; |
2732 | struct keystone_rio_mbox_info *tx_mbox = &(krio_priv->tx_mbox[mbox]); | ||
2733 | |||
2734 | if (mbox >= KEYSTONE_RIO_MAX_MBOX) | ||
2735 | return; | ||
2736 | 2858 | ||
2737 | dev_info(krio_priv->dev, "close_outb_mbox: mport = 0x%x, mbox = %d\n", | 2859 | dev_info(krio_priv->dev, "close outb mbox: mport = 0x%x, mbox = %d\n", |
2738 | (u32) mport, mbox); | 2860 | (u32) mport, mbox); |
2739 | 2861 | ||
2740 | tx_mbox->port = NULL; | 2862 | keystone_rio_close_tx_mbox(mbox, krio_priv); |
2741 | tx_mbox->running = 0; | ||
2742 | |||
2743 | keystone_rio_mp_outb_exit(krio_priv); | ||
2744 | |||
2745 | return; | ||
2746 | } | 2863 | } |
2747 | 2864 | ||
2748 | static void keystone_rio_tx_complete(void *data) | 2865 | static void keystone_rio_tx_complete(void *data) |
@@ -3132,11 +3249,13 @@ static void keystone_rio_get_controller_defaults(struct device_node *node, | |||
3132 | /* K1 setup*/ | 3249 | /* K1 setup*/ |
3133 | c->serdes_type = KEYSTONE_SERDES_TYPE_K1; | 3250 | c->serdes_type = KEYSTONE_SERDES_TYPE_K1; |
3134 | c->serdes_config.prescalar_srv_clk = 0x001e; | 3251 | c->serdes_config.prescalar_srv_clk = 0x001e; |
3252 | c->serdes_config.do_dfe_cal = 0; /* no DFE calibration */ | ||
3135 | c->path_mode = 0x0000; | 3253 | c->path_mode = 0x0000; |
3136 | } else { | 3254 | } else { |
3137 | /* K2 setup*/ | 3255 | /* K2 setup*/ |
3138 | c->serdes_type = KEYSTONE_SERDES_TYPE_K2; | 3256 | c->serdes_type = KEYSTONE_SERDES_TYPE_K2; |
3139 | c->serdes_config.prescalar_srv_clk = 0x001f; | 3257 | c->serdes_config.prescalar_srv_clk = 0x001f; |
3258 | c->serdes_config.do_dfe_cal = 0; /* no DFE calibration */ | ||
3140 | c->path_mode = 0x0004; | 3259 | c->path_mode = 0x0004; |
3141 | 3260 | ||
3142 | if (of_property_read_u32(node, "baudrate", &c->serdes_baudrate)) { | 3261 | if (of_property_read_u32(node, "baudrate", &c->serdes_baudrate)) { |
@@ -3147,58 +3266,105 @@ static void keystone_rio_get_controller_defaults(struct device_node *node, | |||
3147 | } | 3266 | } |
3148 | } | 3267 | } |
3149 | 3268 | ||
3269 | /* Set if performing optional SerDes calibration sequence at boot */ | ||
3270 | c->serdes_calibration = serdes_calibration; | ||
3271 | |||
3150 | /* SerDes pre-1lsb, c1, c2, cm, att and vreg config */ | 3272 | /* SerDes pre-1lsb, c1, c2, cm, att and vreg config */ |
3151 | if (of_property_read_u32_array(node, "serdes_1sb", &temp[0], 4)) { | 3273 | if (of_property_read_u32_array(node, "serdes_1sb", &temp[0], 4)) { |
3152 | for (i = 0; i < 4; i++) | 3274 | for (i = 0; i < 4; i++) |
3153 | c->serdes_config.lane[i].pre_1lsb = 0; | 3275 | c->serdes_config.tx[i].pre_1lsb = 0; |
3154 | } else { | 3276 | } else { |
3155 | for (i = 0; i < 4; i++) | 3277 | for (i = 0; i < 4; i++) |
3156 | c->serdes_config.lane[i].pre_1lsb = temp[i]; | 3278 | c->serdes_config.tx[i].pre_1lsb = temp[i]; |
3157 | } | 3279 | } |
3158 | 3280 | ||
3159 | if (of_property_read_u32_array(node, "serdes_c1", &temp[0], 4)) { | 3281 | if (of_property_read_u32_array(node, "serdes_c1", &temp[0], 4)) { |
3160 | if (c->serdes_baudrate == KEYSTONE_SERDES_BAUD_3_125) { | 3282 | if (c->serdes_baudrate == KEYSTONE_SERDES_BAUD_3_125) { |
3161 | for (i = 0; i < 4; i++) | 3283 | for (i = 0; i < 4; i++) |
3162 | c->serdes_config.lane[i].c1_coeff = 4; | 3284 | c->serdes_config.tx[i].c1_coeff = 4; |
3163 | } else { | 3285 | } else { |
3164 | for (i = 0; i < 4; i++) | 3286 | for (i = 0; i < 4; i++) |
3165 | c->serdes_config.lane[i].c1_coeff = 6; | 3287 | c->serdes_config.tx[i].c1_coeff = 6; |
3166 | } | 3288 | } |
3167 | } else { | 3289 | } else { |
3168 | for (i = 0; i < 4; i++) | 3290 | for (i = 0; i < 4; i++) |
3169 | c->serdes_config.lane[i].c1_coeff = temp[i]; | 3291 | c->serdes_config.tx[i].c1_coeff = temp[i]; |
3170 | } | 3292 | } |
3171 | 3293 | ||
3172 | if (of_property_read_u32_array(node, "serdes_c2", &temp[0], 4)) { | 3294 | if (of_property_read_u32_array(node, "serdes_c2", &temp[0], 4)) { |
3173 | for (i = 0; i < 4; i++) | 3295 | for (i = 0; i < 4; i++) |
3174 | c->serdes_config.lane[i].c2_coeff = 0; | 3296 | c->serdes_config.tx[i].c2_coeff = 0; |
3175 | } else { | 3297 | } else { |
3176 | for (i = 0; i < 4; i++) | 3298 | for (i = 0; i < 4; i++) |
3177 | c->serdes_config.lane[i].c2_coeff = temp[i]; | 3299 | c->serdes_config.tx[i].c2_coeff = temp[i]; |
3178 | } | 3300 | } |
3179 | 3301 | ||
3180 | if (of_property_read_u32_array(node, "serdes_cm", &temp[0], 4)) { | 3302 | if (of_property_read_u32_array(node, "serdes_cm", &temp[0], 4)) { |
3181 | for (i = 0; i < 4; i++) | 3303 | for (i = 0; i < 4; i++) |
3182 | c->serdes_config.lane[i].cm_coeff = 0; | 3304 | c->serdes_config.tx[i].cm_coeff = 0; |
3183 | } else { | 3305 | } else { |
3184 | for (i = 0; i < 4; i++) | 3306 | for (i = 0; i < 4; i++) |
3185 | c->serdes_config.lane[i].cm_coeff = temp[i]; | 3307 | c->serdes_config.tx[i].cm_coeff = temp[i]; |
3186 | } | 3308 | } |
3187 | 3309 | ||
3188 | if (of_property_read_u32_array(node, "serdes_att", &temp[0], 4)) { | 3310 | if (of_property_read_u32_array(node, "serdes_att", &temp[0], 4)) { |
3189 | for (i = 0; i < 4; i++) | 3311 | for (i = 0; i < 4; i++) |
3190 | c->serdes_config.lane[i].att = 12; | 3312 | c->serdes_config.tx[i].att = 12; |
3191 | } else { | 3313 | } else { |
3192 | for (i = 0; i < 4; i++) | 3314 | for (i = 0; i < 4; i++) |
3193 | c->serdes_config.lane[i].att = temp[i]; | 3315 | c->serdes_config.tx[i].att = temp[i]; |
3194 | } | 3316 | } |
3195 | 3317 | ||
3196 | if (of_property_read_u32_array(node, "serdes_vreg", &temp[0], 4)) { | 3318 | if (of_property_read_u32_array(node, "serdes_vreg", &temp[0], 4)) { |
3197 | for (i = 0; i < 4; i++) | 3319 | for (i = 0; i < 4; i++) |
3198 | c->serdes_config.lane[i].vreg = 4; | 3320 | c->serdes_config.tx[i].vreg = 4; |
3321 | } else { | ||
3322 | for (i = 0; i < 4; i++) | ||
3323 | c->serdes_config.tx[i].vreg = temp[i]; | ||
3324 | } | ||
3325 | |||
3326 | if (of_property_read_u32_array(node, "serdes_vdreg", &temp[0], 4)) { | ||
3327 | for (i = 0; i < 4; i++) | ||
3328 | c->serdes_config.tx[i].vdreg = 1; | ||
3329 | } else { | ||
3330 | for (i = 0; i < 4; i++) | ||
3331 | c->serdes_config.tx[i].vdreg = temp[i]; | ||
3332 | } | ||
3333 | |||
3334 | if (of_property_read_u32_array(node, "serdes_rx_att_start", | ||
3335 | &temp[0], 4)) { | ||
3336 | for (i = 0; i < 4; i++) | ||
3337 | c->serdes_config.rx[i].start_att = 3; | ||
3338 | } else { | ||
3339 | for (i = 0; i < 4; i++) | ||
3340 | c->serdes_config.rx[i].start_att = temp[i]; | ||
3341 | } | ||
3342 | |||
3343 | if (of_property_read_u32_array(node, "serdes_rx_boost_start", | ||
3344 | &temp[0], 4)) { | ||
3345 | for (i = 0; i < 4; i++) | ||
3346 | c->serdes_config.rx[i].start_boost = 3; | ||
3347 | } else { | ||
3348 | for (i = 0; i < 4; i++) | ||
3349 | c->serdes_config.rx[i].start_boost = temp[i]; | ||
3350 | } | ||
3351 | |||
3352 | if (of_property_read_u32_array(node, "serdes_rx_att", &temp[0], 4)) { | ||
3353 | for (i = 0; i < 4; i++) | ||
3354 | /* Use dynamic Rx calibration */ | ||
3355 | c->serdes_config.rx[i].mean_att = -1; | ||
3199 | } else { | 3356 | } else { |
3200 | for (i = 0; i < 4; i++) | 3357 | for (i = 0; i < 4; i++) |
3201 | c->serdes_config.lane[i].vreg = temp[i]; | 3358 | c->serdes_config.rx[i].mean_att = temp[i]; |
3359 | } | ||
3360 | |||
3361 | if (of_property_read_u32_array(node, "serdes_rx_boost", &temp[0], 4)) { | ||
3362 | for (i = 0; i < 4; i++) | ||
3363 | /* Use dynamic Rx calibration */ | ||
3364 | c->serdes_config.rx[i].mean_boost = -1; | ||
3365 | } else { | ||
3366 | for (i = 0; i < 4; i++) | ||
3367 | c->serdes_config.rx[i].mean_boost = temp[i]; | ||
3202 | } | 3368 | } |
3203 | 3369 | ||
3204 | /* Path mode config (mapping of SerDes lanes to port widths) */ | 3370 | /* Path mode config (mapping of SerDes lanes to port widths) */ |
@@ -3207,7 +3373,7 @@ static void keystone_rio_get_controller_defaults(struct device_node *node, | |||
3207 | "Missing \"path_mode\" parameter\n"); | 3373 | "Missing \"path_mode\" parameter\n"); |
3208 | } | 3374 | } |
3209 | 3375 | ||
3210 | /* Max possible ports configurations per path_mode */ | 3376 | /* Max possible ports configurations per path_mode */ |
3211 | if ((c->path_mode == 0 && | 3377 | if ((c->path_mode == 0 && |
3212 | c->ports & ~KEYSTONE_MAX_PORTS_PATH_MODE_0) || | 3378 | c->ports & ~KEYSTONE_MAX_PORTS_PATH_MODE_0) || |
3213 | (c->path_mode == 1 && | 3379 | (c->path_mode == 1 && |
@@ -3294,7 +3460,7 @@ static void keystone_rio_get_controller_defaults(struct device_node *node, | |||
3294 | } | 3460 | } |
3295 | } | 3461 | } |
3296 | 3462 | ||
3297 | static int keystone_rio_port_chk(struct keystone_rio_data *krio_priv) | 3463 | static int keystone_rio_port_chk(struct keystone_rio_data *krio_priv, int init) |
3298 | { | 3464 | { |
3299 | u32 ports = krio_priv->ports_registering; | 3465 | u32 ports = krio_priv->ports_registering; |
3300 | u32 size = krio_priv->board_rio_cfg.size; | 3466 | u32 size = krio_priv->board_rio_cfg.size; |
@@ -3303,13 +3469,18 @@ static int keystone_rio_port_chk(struct keystone_rio_data *krio_priv) | |||
3303 | while (ports) { | 3469 | while (ports) { |
3304 | int status; | 3470 | int status; |
3305 | u32 port = __ffs(ports); | 3471 | u32 port = __ffs(ports); |
3306 | ports &= ~(1 << port); | 3472 | ports &= ~BIT(port); |
3307 | 3473 | ||
3308 | /* Wait lanes to be OK */ | 3474 | /* Eventually start lanes and wait them to be OK and with SD */ |
3309 | if (keystone_rio_lanes_init_and_wait(port, 0, krio_priv)) | 3475 | if (keystone_rio_lanes_init_and_wait(port, init, krio_priv)) |
3310 | continue; | 3476 | continue; |
3311 | 3477 | ||
3312 | /* Check port status */ | 3478 | /* |
3479 | * Check the port status here before calling the generic RapidIO | ||
3480 | * layer. Port status check is done in rio_mport_is_active() as | ||
3481 | * well but we need to do it our way first due to some delays in | ||
3482 | * hw initialization. | ||
3483 | */ | ||
3313 | status = keystone_rio_port_status(port, krio_priv); | 3484 | status = keystone_rio_port_status(port, krio_priv); |
3314 | if (status == 0) { | 3485 | if (status == 0) { |
3315 | unsigned long flags; | 3486 | unsigned long flags; |
@@ -3320,24 +3491,25 @@ static int keystone_rio_port_chk(struct keystone_rio_data *krio_priv) | |||
3320 | * Only mport registration may fail now. | 3491 | * Only mport registration may fail now. |
3321 | */ | 3492 | */ |
3322 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | 3493 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); |
3323 | krio_priv->ports |= (1 << port); | 3494 | krio_priv->ports |= BIT(port); |
3324 | krio_priv->ports_registering &= ~(1 << port); | 3495 | krio_priv->ports_registering &= ~BIT(port); |
3325 | spin_unlock_irqrestore(&krio_priv->port_chk_lock, | 3496 | spin_unlock_irqrestore(&krio_priv->port_chk_lock, |
3326 | flags); | 3497 | flags); |
3327 | 3498 | ||
3328 | /* Register mport only if this is initial port check */ | 3499 | /* Register mport only if this is initial port check */ |
3329 | if (!krio_priv->mport[port]) { | 3500 | if (!krio_priv->mport[port]) { |
3330 | mport = keystone_rio_register_mport(port, size, | 3501 | mport = keystone_rio_register_mport( |
3331 | krio_priv); | 3502 | port, size, krio_priv); |
3503 | |||
3332 | if (!mport) { | 3504 | if (!mport) { |
3333 | dev_err(krio_priv->dev, | 3505 | dev_err(krio_priv->dev, |
3334 | "failed to register mport %d\n", | 3506 | "failed to register mport %d\n", |
3335 | port); | 3507 | port); |
3336 | return -1; | 3508 | return -1; |
3337 | } | 3509 | } |
3510 | |||
3338 | dev_info(krio_priv->dev, | 3511 | dev_info(krio_priv->dev, |
3339 | "port RIO%d host_deviceid %d " | 3512 | "port RIO%d host_deviceid %d registered\n", |
3340 | "registered\n", | ||
3341 | port, mport->host_deviceid); | 3513 | port, mport->host_deviceid); |
3342 | } else { | 3514 | } else { |
3343 | dev_info(krio_priv->dev, | 3515 | dev_info(krio_priv->dev, |
@@ -3352,7 +3524,6 @@ static int keystone_rio_port_chk(struct keystone_rio_data *krio_priv) | |||
3352 | */ | 3524 | */ |
3353 | if (krio_priv->board_rio_cfg.pkt_forwarding) | 3525 | if (krio_priv->board_rio_cfg.pkt_forwarding) |
3354 | keystone_rio_port_set_routing(port, krio_priv); | 3526 | keystone_rio_port_set_routing(port, krio_priv); |
3355 | |||
3356 | } else { | 3527 | } else { |
3357 | if (status == -EINVAL) | 3528 | if (status == -EINVAL) |
3358 | return -1; | 3529 | return -1; |
@@ -3370,10 +3541,13 @@ static void keystone_rio_port_chk_task(struct work_struct *work) | |||
3370 | to_delayed_work(work), struct keystone_rio_data, port_chk_task); | 3541 | to_delayed_work(work), struct keystone_rio_data, port_chk_task); |
3371 | int res; | 3542 | int res; |
3372 | 3543 | ||
3373 | res = keystone_rio_port_chk(krio_priv); | 3544 | res = keystone_rio_port_chk(krio_priv, 0); |
3374 | if (res) { | 3545 | if (res) { |
3375 | unsigned long flags; | 3546 | unsigned long flags; |
3376 | 3547 | ||
3548 | if (res == -1) | ||
3549 | return; | ||
3550 | |||
3377 | /* If port check failed schedule next check (if any) */ | 3551 | /* If port check failed schedule next check (if any) */ |
3378 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | 3552 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); |
3379 | if (krio_priv->port_chk_cnt-- > 1) { | 3553 | if (krio_priv->port_chk_cnt-- > 1) { |
@@ -3410,14 +3584,14 @@ static ssize_t keystone_rio_ports_store(struct device *dev, | |||
3410 | if (kstrtoul(buf, 0, &ports)) | 3584 | if (kstrtoul(buf, 0, &ports)) |
3411 | return -EINVAL; | 3585 | return -EINVAL; |
3412 | 3586 | ||
3413 | if (ports > ((1 << KEYSTONE_RIO_MAX_PORT) - 1)) | 3587 | if (ports > (BIT(KEYSTONE_RIO_MAX_PORT) - 1)) |
3414 | return -EINVAL; | 3588 | return -EINVAL; |
3415 | 3589 | ||
3416 | /* | 3590 | /* |
3417 | * Only the ports defined in DTS can be rescanned because SerDes | 3591 | * Only the ports defined in DTS can be rescanned because SerDes |
3418 | * initialization is not restarted here, only link status check. | 3592 | * initialization is not restarted here, only link status check. |
3419 | */ | 3593 | */ |
3420 | ports &= krio_priv->board_rio_cfg.ports; | 3594 | ports &= krio_priv->board_rio_cfg.ports; |
3421 | 3595 | ||
3422 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | 3596 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); |
3423 | krio_priv->ports_registering = (ports & ~krio_priv->ports); | 3597 | krio_priv->ports_registering = (ports & ~krio_priv->ports); |
@@ -3454,14 +3628,117 @@ static ssize_t keystone_rio_ports_show(struct device *dev, | |||
3454 | return scnprintf(buf, PAGE_SIZE, "0x%x\n", krio_priv->ports); | 3628 | return scnprintf(buf, PAGE_SIZE, "0x%x\n", krio_priv->ports); |
3455 | } | 3629 | } |
3456 | 3630 | ||
3631 | static ssize_t keystone_rio_start_store(struct device *dev, | ||
3632 | struct device_attribute *attr, | ||
3633 | const char *buf, | ||
3634 | size_t count) | ||
3635 | { | ||
3636 | struct keystone_rio_data *krio_priv = (struct keystone_rio_data *) | ||
3637 | dev->platform_data; | ||
3638 | long unsigned int new_start; | ||
3639 | |||
3640 | if (kstrtoul(buf, 0, &new_start)) | ||
3641 | return -EINVAL; | ||
3642 | |||
3643 | /* Start SRIO peripheral if not started */ | ||
3644 | if ((new_start) && (krio_priv->started == 0)) { | ||
3645 | keystone_rio_setup_controller(krio_priv); | ||
3646 | return count; | ||
3647 | } | ||
3648 | |||
3649 | /* Stop SRIO peripheral if started */ | ||
3650 | if ((new_start == 0) && (krio_priv->started == 1)) { | ||
3651 | keystone_rio_shutdown_controller(krio_priv); | ||
3652 | return count; | ||
3653 | } | ||
3654 | |||
3655 | return count; | ||
3656 | } | ||
3657 | |||
3658 | static ssize_t keystone_rio_start_show(struct device *dev, | ||
3659 | struct device_attribute *attr, | ||
3660 | char *buf) | ||
3661 | { | ||
3662 | struct keystone_rio_data *krio_priv = (struct keystone_rio_data *) | ||
3663 | dev->platform_data; | ||
3664 | |||
3665 | if (krio_priv == NULL) | ||
3666 | return -EINVAL; | ||
3667 | |||
3668 | return scnprintf(buf, PAGE_SIZE, "%d\n", krio_priv->started); | ||
3669 | } | ||
3670 | |||
3671 | static ssize_t keystone_rio_calibrate_store(struct device *dev, | ||
3672 | struct device_attribute *attr, | ||
3673 | const char *buf, | ||
3674 | size_t count) | ||
3675 | { | ||
3676 | struct keystone_rio_data *krio_priv = (struct keystone_rio_data *) | ||
3677 | dev->platform_data; | ||
3678 | long unsigned int new_calibrate; | ||
3679 | |||
3680 | if (kstrtoul(buf, 0, &new_calibrate)) | ||
3681 | return -EINVAL; | ||
3682 | |||
3683 | /* Start SRIO calibration */ | ||
3684 | if ((new_calibrate) && (krio_priv->started == 0)) { | ||
3685 | int res; | ||
3686 | u32 block; | ||
3687 | |||
3688 | /* Enable RIO SerDes blocks */ | ||
3689 | __raw_writel(1, &krio_priv->regs->gbl_en); | ||
3690 | for (block = KEYSTONE_RIO_BLK_PORT0; | ||
3691 | block <= KEYSTONE_RIO_BLK_PORT3; | ||
3692 | block++) | ||
3693 | __raw_writel(1, &(krio_priv->regs->blk[block].enable)); | ||
3694 | |||
3695 | /* Do SerDes initialization and calibration */ | ||
3696 | res = keystone_rio_serdes_init( | ||
3697 | krio_priv->board_rio_cfg.serdes_baudrate, | ||
3698 | 1, | ||
3699 | krio_priv); | ||
3700 | |||
3701 | if (res < 0) | ||
3702 | dev_err(krio_priv->dev, | ||
3703 | "calibration of SerDes failed\n"); | ||
3704 | } | ||
3705 | |||
3706 | return count; | ||
3707 | } | ||
3708 | |||
3709 | static ssize_t keystone_rio_calibrate_show(struct device *dev, | ||
3710 | struct device_attribute *attr, | ||
3711 | char *buf) | ||
3712 | { | ||
3713 | struct keystone_rio_data *krio_priv = (struct keystone_rio_data *) | ||
3714 | dev->platform_data; | ||
3715 | |||
3716 | if (krio_priv == NULL) | ||
3717 | return -EINVAL; | ||
3718 | |||
3719 | return scnprintf(buf, PAGE_SIZE, "%d\n", krio_priv->calibrating); | ||
3720 | } | ||
3721 | |||
3457 | static DEVICE_ATTR(ports, | 3722 | static DEVICE_ATTR(ports, |
3458 | S_IRUGO | S_IWUSR, | 3723 | S_IRUGO | S_IWUSR, |
3459 | keystone_rio_ports_show, | 3724 | keystone_rio_ports_show, |
3460 | keystone_rio_ports_store); | 3725 | keystone_rio_ports_store); |
3461 | 3726 | ||
3727 | static DEVICE_ATTR(start, | ||
3728 | S_IRUGO | S_IWUSR, | ||
3729 | keystone_rio_start_show, | ||
3730 | keystone_rio_start_store); | ||
3731 | |||
3732 | static DEVICE_ATTR(calibrate, | ||
3733 | S_IRUGO | S_IWUSR, | ||
3734 | keystone_rio_calibrate_show, | ||
3735 | keystone_rio_calibrate_store); | ||
3736 | |||
3462 | static void keystone_rio_sysfs_remove(struct device *dev) | 3737 | static void keystone_rio_sysfs_remove(struct device *dev) |
3463 | { | 3738 | { |
3464 | device_remove_file(dev, &dev_attr_ports); | 3739 | device_remove_file(dev, &dev_attr_ports); |
3740 | device_remove_file(dev, &dev_attr_start); | ||
3741 | device_remove_file(dev, &dev_attr_calibrate); | ||
3465 | } | 3742 | } |
3466 | 3743 | ||
3467 | static int keystone_rio_sysfs_create(struct device *dev) | 3744 | static int keystone_rio_sysfs_create(struct device *dev) |
@@ -3469,8 +3746,20 @@ static int keystone_rio_sysfs_create(struct device *dev) | |||
3469 | int res = 0; | 3746 | int res = 0; |
3470 | 3747 | ||
3471 | res = device_create_file(dev, &dev_attr_ports); | 3748 | res = device_create_file(dev, &dev_attr_ports); |
3472 | if (res) | 3749 | if (res) { |
3473 | dev_err(dev, "unable create sysfs ports file\n"); | 3750 | dev_err(dev, "unable create sysfs ports file\n"); |
3751 | return res; | ||
3752 | } | ||
3753 | |||
3754 | res = device_create_file(dev, &dev_attr_start); | ||
3755 | if (res) { | ||
3756 | dev_err(dev, "unable create sysfs start file\n"); | ||
3757 | return res; | ||
3758 | } | ||
3759 | |||
3760 | res = device_create_file(dev, &dev_attr_calibrate); | ||
3761 | if (res) | ||
3762 | dev_err(dev, "unable create sysfs calibrate file\n"); | ||
3474 | 3763 | ||
3475 | return res; | 3764 | return res; |
3476 | } | 3765 | } |
@@ -3486,7 +3775,6 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3486 | u32 path_mode; | 3775 | u32 path_mode; |
3487 | u32 size = 0; | 3776 | u32 size = 0; |
3488 | int res = 0; | 3777 | int res = 0; |
3489 | struct rio_mport *mport; | ||
3490 | char str[8]; | 3778 | char str[8]; |
3491 | unsigned long flags; | 3779 | unsigned long flags; |
3492 | 3780 | ||
@@ -3495,6 +3783,8 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3495 | baud = krio_priv->board_rio_cfg.serdes_baudrate; | 3783 | baud = krio_priv->board_rio_cfg.serdes_baudrate; |
3496 | path_mode = krio_priv->board_rio_cfg.path_mode; | 3784 | path_mode = krio_priv->board_rio_cfg.path_mode; |
3497 | 3785 | ||
3786 | krio_priv->started = 1; | ||
3787 | |||
3498 | dev_dbg(krio_priv->dev, "size = %d, ports = 0x%x, baud = %d, path_mode = %d\n", | 3788 | dev_dbg(krio_priv->dev, "size = %d, ports = 0x%x, baud = %d, path_mode = %d\n", |
3499 | size, ports, baud, path_mode); | 3789 | size, ports, baud, path_mode); |
3500 | 3790 | ||
@@ -3518,8 +3808,7 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3518 | snprintf(str, sizeof(str), "5.00"); | 3808 | snprintf(str, sizeof(str), "5.00"); |
3519 | break; | 3809 | break; |
3520 | default: | 3810 | default: |
3521 | res = -EINVAL; | 3811 | return -EINVAL; |
3522 | goto out; | ||
3523 | } | 3812 | } |
3524 | 3813 | ||
3525 | dev_info(krio_priv->dev, | 3814 | dev_info(krio_priv->dev, |
@@ -3543,6 +3832,9 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3543 | for (p = 0; p < KEYSTONE_RIO_MAX_PORT; p++) | 3832 | for (p = 0; p < KEYSTONE_RIO_MAX_PORT; p++) |
3544 | keystone_rio_port_disable(p, krio_priv); | 3833 | keystone_rio_port_disable(p, krio_priv); |
3545 | 3834 | ||
3835 | /* Register all configured ports */ | ||
3836 | krio_priv->ports_registering = krio_priv->board_rio_cfg.ports; | ||
3837 | |||
3546 | /* Initialize interrupts */ | 3838 | /* Initialize interrupts */ |
3547 | res = keystone_rio_interrupt_setup(krio_priv); | 3839 | res = keystone_rio_interrupt_setup(krio_priv); |
3548 | if (res) | 3840 | if (res) |
@@ -3551,15 +3843,9 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3551 | /* Start the controller */ | 3843 | /* Start the controller */ |
3552 | keystone_rio_start(krio_priv); | 3844 | keystone_rio_start(krio_priv); |
3553 | 3845 | ||
3554 | /* Use and check ports status (but only the requested ones) */ | ||
3555 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | ||
3556 | krio_priv->ports_registering = 0; | ||
3557 | spin_unlock_irqrestore(&krio_priv->port_chk_lock, flags); | ||
3558 | |||
3559 | while (ports) { | 3846 | while (ports) { |
3560 | int status; | ||
3561 | u32 port = __ffs(ports); | 3847 | u32 port = __ffs(ports); |
3562 | ports &= ~(1 << port); | 3848 | ports &= ~BIT(port); |
3563 | 3849 | ||
3564 | res = keystone_rio_port_init(port, path_mode, krio_priv); | 3850 | res = keystone_rio_port_init(port, path_mode, krio_priv); |
3565 | if (res < 0) { | 3851 | if (res < 0) { |
@@ -3569,56 +3855,16 @@ static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) | |||
3569 | } | 3855 | } |
3570 | 3856 | ||
3571 | /* Start the port */ | 3857 | /* Start the port */ |
3572 | keystone_rio_port_activate(port, krio_priv); | 3858 | keystone_rio_port_enable(port, krio_priv); |
3573 | |||
3574 | /* Start lanes and wait them to be OK */ | ||
3575 | if (keystone_rio_lanes_init_and_wait(port, 1, krio_priv)) | ||
3576 | goto port_not_ready; | ||
3577 | |||
3578 | /* | ||
3579 | * Check the port status here before calling the generic RapidIO | ||
3580 | * layer. Port status check is done in rio_mport_is_active() as | ||
3581 | * well but we need to do it our way first due to some delays in | ||
3582 | * hw initialization. | ||
3583 | */ | ||
3584 | status = keystone_rio_port_status(port, krio_priv); | ||
3585 | if (status == 0) { | ||
3586 | /* Register this port */ | ||
3587 | mport = keystone_rio_register_mport(port, size, krio_priv); | ||
3588 | if (!mport) | ||
3589 | goto out; | ||
3590 | |||
3591 | /* | ||
3592 | * Update routing after discovery/enumeration | ||
3593 | * with new dev id | ||
3594 | */ | ||
3595 | if (krio_priv->board_rio_cfg.pkt_forwarding) | ||
3596 | keystone_rio_port_set_routing(port, krio_priv); | ||
3597 | |||
3598 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | ||
3599 | krio_priv->ports |= (1 << port); | ||
3600 | spin_unlock_irqrestore(&krio_priv->port_chk_lock, | ||
3601 | flags); | ||
3602 | |||
3603 | dev_info(krio_priv->dev, | ||
3604 | "port RIO%d host_deviceid %d registered\n", | ||
3605 | port, mport->host_deviceid); | ||
3606 | |||
3607 | continue; | ||
3608 | } | ||
3609 | if (status == -EINVAL) | ||
3610 | return status; | ||
3611 | port_not_ready: | ||
3612 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | ||
3613 | krio_priv->ports_registering |= (1 << port); | ||
3614 | spin_unlock_irqrestore(&krio_priv->port_chk_lock, flags); | ||
3615 | |||
3616 | dev_warn(krio_priv->dev, "port %d not ready\n", port); | ||
3617 | } | 3859 | } |
3618 | 3860 | ||
3619 | if (krio_priv->ports_registering) { | 3861 | /* Complete port initialization and wait link */ |
3620 | unsigned long flags; | 3862 | res = keystone_rio_port_chk(krio_priv, 1); |
3863 | if (res) { | ||
3864 | if (res == -1) | ||
3865 | return -ENOMEM; | ||
3621 | 3866 | ||
3867 | /* If port check failed schedule asynchronous periodic check */ | ||
3622 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); | 3868 | spin_lock_irqsave(&krio_priv->port_chk_lock, flags); |
3623 | krio_priv->port_chk_cnt = | 3869 | krio_priv->port_chk_cnt = |
3624 | krio_priv->board_rio_cfg.port_register_timeout / | 3870 | krio_priv->board_rio_cfg.port_register_timeout / |
@@ -3628,7 +3874,7 @@ port_not_ready: | |||
3628 | schedule_delayed_work(&krio_priv->port_chk_task, | 3874 | schedule_delayed_work(&krio_priv->port_chk_task, |
3629 | KEYSTONE_RIO_REGISTER_DELAY); | 3875 | KEYSTONE_RIO_REGISTER_DELAY); |
3630 | } | 3876 | } |
3631 | out: | 3877 | |
3632 | return res; | 3878 | return res; |
3633 | } | 3879 | } |
3634 | 3880 | ||
@@ -3663,8 +3909,10 @@ static int keystone_rio_probe(struct platform_device *pdev) | |||
3663 | mutex_init(&krio_priv->lsu_lock); | 3909 | mutex_init(&krio_priv->lsu_lock); |
3664 | init_completion(&krio_priv->lsu_completion); | 3910 | init_completion(&krio_priv->lsu_completion); |
3665 | spin_lock_init(&krio_priv->port_chk_lock); | 3911 | spin_lock_init(&krio_priv->port_chk_lock); |
3912 | |||
3666 | INIT_DELAYED_WORK(&krio_priv->port_chk_task, | 3913 | INIT_DELAYED_WORK(&krio_priv->port_chk_task, |
3667 | keystone_rio_port_chk_task); | 3914 | keystone_rio_port_chk_task); |
3915 | INIT_DELAYED_WORK(&krio_priv->pe_work, keystone_rio_pe_dpc); | ||
3668 | 3916 | ||
3669 | regs = ioremap(krio_priv->board_rio_cfg.boot_cfg_regs_base, | 3917 | regs = ioremap(krio_priv->board_rio_cfg.boot_cfg_regs_base, |
3670 | krio_priv->board_rio_cfg.boot_cfg_regs_size); | 3918 | krio_priv->board_rio_cfg.boot_cfg_regs_size); |
@@ -3693,11 +3941,15 @@ static int keystone_rio_probe(struct platform_device *pdev) | |||
3693 | krio_priv->fabric_regs = regs + 0x1be00; | 3941 | krio_priv->fabric_regs = regs + 0x1be00; |
3694 | krio_priv->car_csr_regs_base = (u32) regs + 0xb000; | 3942 | krio_priv->car_csr_regs_base = (u32) regs + 0xb000; |
3695 | 3943 | ||
3696 | INIT_DELAYED_WORK(&krio_priv->pe_work, keystone_rio_pe_dpc); | 3944 | /* Register SerDes */ |
3945 | res = keystone_rio_serdes_register( | ||
3946 | serdes_type, | ||
3947 | krio_priv->serdes_regs, | ||
3948 | krio_priv->serdes_sts_reg, | ||
3949 | &pdev->dev, | ||
3950 | &krio_priv->serdes, | ||
3951 | &krio_priv->board_rio_cfg.serdes_config); | ||
3697 | 3952 | ||
3698 | /* Retrieve SerDes ops */ | ||
3699 | res = keystone_rio_serdes_register(serdes_type, | ||
3700 | &krio_priv->serdes_ops); | ||
3701 | if (res < 0) { | 3953 | if (res < 0) { |
3702 | dev_err(&pdev->dev, "cannot register SerDes type %d\n", | 3954 | dev_err(&pdev->dev, "cannot register SerDes type %d\n", |
3703 | serdes_type); | 3955 | serdes_type); |
@@ -3728,59 +3980,82 @@ static int keystone_rio_probe(struct platform_device *pdev) | |||
3728 | dev_info(&pdev->dev, "KeyStone RapidIO driver %s\n", DRIVER_VER); | 3980 | dev_info(&pdev->dev, "KeyStone RapidIO driver %s\n", DRIVER_VER); |
3729 | 3981 | ||
3730 | /* Setup the sRIO controller */ | 3982 | /* Setup the sRIO controller */ |
3731 | res = keystone_rio_setup_controller(krio_priv); | 3983 | if (enable_ports) { |
3732 | if (res < 0) { | 3984 | res = keystone_rio_setup_controller(krio_priv); |
3733 | clk_disable_unprepare(krio_priv->clk); | 3985 | if (res < 0) { |
3734 | clk_put(krio_priv->clk); | 3986 | clk_disable_unprepare(krio_priv->clk); |
3735 | kfree(krio_priv); | 3987 | clk_put(krio_priv->clk); |
3736 | return res; | 3988 | kfree(krio_priv); |
3989 | return res; | ||
3990 | } | ||
3737 | } | 3991 | } |
3738 | 3992 | ||
3739 | return 0; | 3993 | return 0; |
3740 | } | 3994 | } |
3741 | 3995 | ||
3742 | static void keystone_rio_shutdown(struct platform_device *pdev) | 3996 | static void keystone_rio_shutdown_controller( |
3997 | struct keystone_rio_data *krio_priv) | ||
3743 | { | 3998 | { |
3744 | struct keystone_rio_data *krio_priv = platform_get_drvdata(pdev); | 3999 | u32 lanes = keystone_rio_get_lane_config( |
4000 | krio_priv->board_rio_cfg.ports, | ||
4001 | krio_priv->board_rio_cfg.path_mode); | ||
3745 | int i; | 4002 | int i; |
3746 | u32 lanes = keystone_rio_get_lane_config(krio_priv->board_rio_cfg.ports, | 4003 | |
3747 | krio_priv->board_rio_cfg.path_mode); | 4004 | dev_dbg(krio_priv->dev, "shutdown controller\n"); |
3748 | 4005 | ||
3749 | keystone_rio_interrupt_release(krio_priv); | 4006 | keystone_rio_interrupt_release(krio_priv); |
3750 | keystone_rio_mp_outb_exit(krio_priv); | ||
3751 | 4007 | ||
3752 | for (i = 0; i < KEYSTONE_RIO_MAX_MBOX; i++) | 4008 | /* Shutdown associated SerDes */ |
3753 | keystone_rio_mp_inb_exit(i, krio_priv); | 4009 | krio_priv->serdes.ops->shutdown_lanes(lanes, &krio_priv->serdes); |
3754 | 4010 | ||
4011 | /* Stop the hw controller */ | ||
3755 | keystone_rio_stop(krio_priv); | 4012 | keystone_rio_stop(krio_priv); |
3756 | 4013 | ||
3757 | /* Wait current DMA transfers to finish */ | ||
3758 | mdelay(10); | ||
3759 | |||
3760 | /* Disable blocks */ | 4014 | /* Disable blocks */ |
3761 | __raw_writel(0, &krio_priv->regs->gbl_en); | 4015 | __raw_writel(0, &krio_priv->regs->gbl_en); |
3762 | for (i = 0; i <= KEYSTONE_RIO_BLK_NUM; i++) | 4016 | for (i = 0; i < KEYSTONE_RIO_BLK_NUM; i++) { |
3763 | __raw_writel(0, &(krio_priv->regs->blk[i].enable)); | 4017 | __raw_writel(0, &(krio_priv->regs->blk[i].enable)); |
4018 | while (__raw_readl(&(krio_priv->regs->blk[i].status)) & 0x1) | ||
4019 | usleep_range(10, 50); | ||
4020 | } | ||
3764 | 4021 | ||
3765 | /* Shutdown associated SerDes */ | 4022 | krio_priv->started = 0; |
3766 | krio_priv->serdes_ops->shutdown_lanes(lanes, krio_priv->serdes_regs); | 4023 | } |
4024 | |||
4025 | static void keystone_rio_shutdown(struct platform_device *pdev) | ||
4026 | { | ||
4027 | struct keystone_rio_data *krio_priv = platform_get_drvdata(pdev); | ||
4028 | int i; | ||
4029 | |||
4030 | if (krio_priv->started) | ||
4031 | keystone_rio_shutdown_controller(krio_priv); | ||
4032 | |||
4033 | for (i = 0; i < KEYSTONE_RIO_MAX_MBOX; i++) { | ||
4034 | keystone_rio_close_tx_mbox(i, krio_priv); | ||
4035 | keystone_rio_close_rx_mbox(i, krio_priv); | ||
4036 | } | ||
4037 | |||
4038 | /* Wait current DMA transfers to finish */ | ||
4039 | mdelay(10); | ||
3767 | 4040 | ||
3768 | if (krio_priv->clk) { | 4041 | if (krio_priv->clk) { |
3769 | clk_disable_unprepare(krio_priv->clk); | 4042 | clk_disable_unprepare(krio_priv->clk); |
3770 | clk_put(krio_priv->clk); | 4043 | clk_put(krio_priv->clk); |
3771 | } | 4044 | } |
3772 | |||
3773 | platform_set_drvdata(pdev, NULL); | ||
3774 | |||
3775 | kfree(krio_priv); | ||
3776 | } | 4045 | } |
3777 | 4046 | ||
3778 | static int __exit keystone_rio_remove(struct platform_device *pdev) | 4047 | static int __exit keystone_rio_remove(struct platform_device *pdev) |
3779 | { | 4048 | { |
4049 | struct keystone_rio_data *krio_priv = platform_get_drvdata(pdev); | ||
4050 | |||
3780 | keystone_rio_shutdown(pdev); | 4051 | keystone_rio_shutdown(pdev); |
3781 | 4052 | ||
3782 | keystone_rio_sysfs_remove(&pdev->dev); | 4053 | keystone_rio_sysfs_remove(&pdev->dev); |
3783 | 4054 | ||
4055 | platform_set_drvdata(pdev, NULL); | ||
4056 | |||
4057 | kfree(krio_priv); | ||
4058 | |||
3784 | return 0; | 4059 | return 0; |
3785 | } | 4060 | } |
3786 | 4061 | ||
diff --git a/drivers/rapidio/devices/keystone_rio.h b/drivers/rapidio/devices/keystone_rio.h index 074f5a9ff97..93bc6173051 100644 --- a/drivers/rapidio/devices/keystone_rio.h +++ b/drivers/rapidio/devices/keystone_rio.h | |||
@@ -145,7 +145,6 @@ | |||
145 | * RapidIO global definitions | 145 | * RapidIO global definitions |
146 | */ | 146 | */ |
147 | #define KEYSTONE_RIO_MAX_PORT 4 | 147 | #define KEYSTONE_RIO_MAX_PORT 4 |
148 | #define KEYSTONE_RIO_BLK_NUM 9 | ||
149 | #define KEYSTONE_RIO_MAX_MBOX 4 /* 4 in multi-segment, | 148 | #define KEYSTONE_RIO_MAX_MBOX 4 /* 4 in multi-segment, |
150 | 64 in single-seg */ | 149 | 64 in single-seg */ |
151 | #define KEYSTONE_RIO_MAX_PKT_FW_ENTRIES 8 /* max of packet forwarding | 150 | #define KEYSTONE_RIO_MAX_PKT_FW_ENTRIES 8 /* max of packet forwarding |
@@ -157,6 +156,21 @@ | |||
157 | #define KEYSTONE_RIO_PKT_FW_BRR_NUM 1 /* BRR used for packet forwarding */ | 156 | #define KEYSTONE_RIO_PKT_FW_BRR_NUM 1 /* BRR used for packet forwarding */ |
158 | 157 | ||
159 | /* | 158 | /* |
159 | * Block definition | ||
160 | */ | ||
161 | #define KEYSTONE_RIO_BLK_NUM 9 | ||
162 | |||
163 | #define KEYSTONE_RIO_BLK_MMR 0 | ||
164 | #define KEYSTONE_RIO_BLK_LSU 1 | ||
165 | #define KEYSTONE_RIO_BLK_MAU 2 | ||
166 | #define KEYSTONE_RIO_BLK_TXU 3 | ||
167 | #define KEYSTONE_RIO_BLK_RXU 4 | ||
168 | #define KEYSTONE_RIO_BLK_PORT0 5 | ||
169 | #define KEYSTONE_RIO_BLK_PORT1 6 | ||
170 | #define KEYSTONE_RIO_BLK_PORT2 7 | ||
171 | #define KEYSTONE_RIO_BLK_PORT3 8 | ||
172 | |||
173 | /* | ||
160 | * Dev Id and dev revision | 174 | * Dev Id and dev revision |
161 | */ | 175 | */ |
162 | #define KEYSTONE_RIO_DEV_ID_VAL \ | 176 | #define KEYSTONE_RIO_DEV_ID_VAL \ |
@@ -234,6 +248,7 @@ struct keystone_rio_board_controller_info { | |||
234 | * 1 - Large size, 65536 devices. */ | 248 | * 1 - Large size, 65536 devices. */ |
235 | u16 serdes_type; | 249 | u16 serdes_type; |
236 | u32 serdes_baudrate; | 250 | u32 serdes_baudrate; |
251 | u32 serdes_calibration; | ||
237 | u32 path_mode; | 252 | u32 path_mode; |
238 | u32 port_register_timeout; | 253 | u32 port_register_timeout; |
239 | u32 pkt_forwarding; | 254 | u32 pkt_forwarding; |
diff --git a/drivers/rapidio/devices/keystone_rio_serdes.c b/drivers/rapidio/devices/keystone_rio_serdes.c index 59c26c34a4f..bee92005b60 100644 --- a/drivers/rapidio/devices/keystone_rio_serdes.c +++ b/drivers/rapidio/devices/keystone_rio_serdes.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/uaccess.h> | 18 | #include <linux/uaccess.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
21 | #include <linux/sysfs.h> | ||
21 | 22 | ||
22 | #include "keystone_rio_serdes.h" | 23 | #include "keystone_rio_serdes.h" |
23 | 24 | ||
@@ -73,17 +74,15 @@ struct k1_rio_serdes_regs { | |||
73 | static int k1_rio_serdes_config_lanes( | 74 | static int k1_rio_serdes_config_lanes( |
74 | u32 lanes, | 75 | u32 lanes, |
75 | u32 baud, | 76 | u32 baud, |
76 | struct device *dev, | 77 | struct keystone_serdes_data *serdes) |
77 | void __iomem *regs, | ||
78 | void __iomem *sts_reg, | ||
79 | struct keystone_serdes_config *serdes_config) | ||
80 | { | 78 | { |
81 | u32 lane; | 79 | u32 lane; |
82 | int res = 0; | 80 | int res = 0; |
83 | u32 val; | 81 | u32 val; |
84 | unsigned long timeout; | 82 | unsigned long timeout; |
85 | struct k1_rio_serdes_regs *serdes_regs = | 83 | struct k1_rio_serdes_regs *serdes_regs = |
86 | (struct k1_rio_serdes_regs *) regs; | 84 | (struct k1_rio_serdes_regs *) serdes->regs; |
85 | struct device *dev = serdes->dev; | ||
87 | 86 | ||
88 | dev_dbg(dev, "SerDes: configuring SerDes for lane mask 0x%x\n", lanes); | 87 | dev_dbg(dev, "SerDes: configuring SerDes for lane mask 0x%x\n", lanes); |
89 | 88 | ||
@@ -100,13 +99,13 @@ static int k1_rio_serdes_config_lanes( | |||
100 | 99 | ||
101 | /* Check for RIO SerDes PLL lock */ | 100 | /* Check for RIO SerDes PLL lock */ |
102 | while (1) { | 101 | while (1) { |
103 | val = __raw_readl(sts_reg); | 102 | val = __raw_readl(serdes->sts_reg); |
104 | 103 | ||
105 | if ((val & 0x1) != 0x1) | 104 | if ((val & 0x1) != 0x1) |
106 | break; | 105 | break; |
107 | 106 | ||
108 | if (time_after(jiffies, timeout)) { | 107 | if (time_after(jiffies, timeout)) { |
109 | res = -1; | 108 | res = -EAGAIN; |
110 | break; | 109 | break; |
111 | } | 110 | } |
112 | 111 | ||
@@ -118,43 +117,80 @@ static int k1_rio_serdes_config_lanes( | |||
118 | 117 | ||
119 | static int k1_rio_serdes_start_tx_lanes( | 118 | static int k1_rio_serdes_start_tx_lanes( |
120 | u32 lanes, | 119 | u32 lanes, |
121 | struct device *dev, | 120 | struct keystone_serdes_data *serdes) |
122 | void __iomem *regs, | ||
123 | struct keystone_serdes_config *serdes_config) | ||
124 | { | 121 | { |
125 | return 0; | 122 | return 0; |
126 | } | 123 | } |
127 | 124 | ||
128 | static int k1_rio_serdes_wait_lanes_ok(u32 lanes, void __iomem *regs) | 125 | static int k1_rio_serdes_wait_lanes_ok(u32 lanes, |
126 | struct keystone_serdes_data *serdes) | ||
129 | { | 127 | { |
130 | return 0; | 128 | return 0; |
131 | } | 129 | } |
132 | 130 | ||
133 | static int k1_rio_serdes_shutdown_lanes(u32 lanes, void __iomem *regs) | 131 | static int k1_rio_serdes_shutdown_lanes(u32 lanes, |
132 | struct keystone_serdes_data *serdes) | ||
134 | { | 133 | { |
135 | return 0; | 134 | return 0; |
136 | } | 135 | } |
137 | 136 | ||
138 | static void k1_rio_serdes_fix_unstable_lanes(u32 lanes, | 137 | static void k1_rio_serdes_fix_unstable_lanes( |
139 | struct device *dev, | 138 | u32 lanes, |
140 | void __iomem *regs) | 139 | struct keystone_serdes_data *serdes) |
141 | { | 140 | { |
142 | return; | 141 | return; |
143 | } | 142 | } |
144 | 143 | ||
144 | static int k1_rio_serdes_calibrate_lanes(u32 lanes, | ||
145 | struct keystone_serdes_data *serdes) | ||
146 | { | ||
147 | return -ENOSYS; | ||
148 | } | ||
149 | |||
145 | static const struct keystone_serdes_ops k1_serdes_ops = { | 150 | static const struct keystone_serdes_ops k1_serdes_ops = { |
146 | .config_lanes = k1_rio_serdes_config_lanes, | 151 | .config_lanes = k1_rio_serdes_config_lanes, |
147 | .start_tx_lanes = k1_rio_serdes_start_tx_lanes, | 152 | .start_tx_lanes = k1_rio_serdes_start_tx_lanes, |
148 | .wait_lanes_ok = k1_rio_serdes_wait_lanes_ok, | 153 | .wait_lanes_ok = k1_rio_serdes_wait_lanes_ok, |
149 | .shutdown_lanes = k1_rio_serdes_shutdown_lanes, | 154 | .shutdown_lanes = k1_rio_serdes_shutdown_lanes, |
150 | .fix_unstable_lanes = k1_rio_serdes_fix_unstable_lanes, | 155 | .fix_unstable_lanes = k1_rio_serdes_fix_unstable_lanes, |
156 | .calibrate_lanes = k1_rio_serdes_calibrate_lanes, | ||
151 | }; | 157 | }; |
152 | 158 | ||
153 | /*-------------------------- KeyStone 2 SerDes functions --------------------*/ | 159 | /*-------------------------- KeyStone 2 SerDes functions --------------------*/ |
154 | 160 | ||
161 | #define KEYSTONE_SERDES_PRBS_7 0 | ||
162 | #define KEYSTONE_SERDES_PRBS_15 1 | ||
163 | #define KEYSTONE_SERDES_PRBS_23 2 | ||
164 | #define KEYSTONE_SERDES_PRBS_31 3 | ||
165 | |||
166 | #define KEYSTONE_SERDES_MAX_TAPS 5 | ||
167 | #define KEYSTONE_SERDES_MAX_COMPS 5 | ||
168 | |||
169 | #define KEYSTONE_SERDES_OFFSETS_RETRIES 100 | ||
170 | #define KEYSTONE_SERDES_ATT_BOOST_NUM_REPEAT 20 | ||
171 | #define KEYSTONE_SERDES_ATT_BOOST_REPEAT_MEAN 14 | ||
172 | |||
173 | /* SerDes PHY center DFE TAPs and data sample comparators structure */ | ||
174 | struct k2_rio_serdes_tap_offsets { | ||
175 | u32 tap1_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_TAPS]; | ||
176 | u32 tap2_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_TAPS]; | ||
177 | u32 tap3_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_TAPS]; | ||
178 | u32 tap4_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_TAPS]; | ||
179 | u32 tap5_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_TAPS]; | ||
180 | u32 cmp_offsets[KEYSTONE_SERDES_MAX_LANES][KEYSTONE_SERDES_MAX_COMPS]; | ||
181 | }; | ||
182 | |||
183 | struct k2_rio_serdes_reg_field { | ||
184 | u32 reg; | ||
185 | u32 shift; | ||
186 | }; | ||
187 | |||
188 | static int k2_rio_serdes_start_tx_lanes( | ||
189 | u32 lanes, | ||
190 | struct keystone_serdes_data *serdes); | ||
191 | |||
155 | /* | 192 | /* |
156 | * Main code to Read TBUS on PHY-A and generate attenuation and boost values | 193 | * Main code to Read TBUS on PHY-A |
157 | * for a lane given at serdes_base_address and lane_no | ||
158 | */ | 194 | */ |
159 | static void k2_rio_serdes_sb_write_tbus_addr(void __iomem *regs, | 195 | static void k2_rio_serdes_sb_write_tbus_addr(void __iomem *regs, |
160 | int select, | 196 | int select, |
@@ -195,10 +231,10 @@ static u32 k2_rio_serdes_sb_read_selected_tbus(void __iomem *regs, | |||
195 | } | 231 | } |
196 | 232 | ||
197 | /* | 233 | /* |
198 | * Wait SerDes RX valid | 234 | * Wait SerDes Rx valid |
199 | * To be performed after SerDes is configured and bit lock achieved | 235 | * To be performed after SerDes is configured and bit lock achieved |
200 | */ | 236 | */ |
201 | static int k2_rio_serdes_wait_rx_valid(void __iomem *regs, int lane) | 237 | static int k2_rio_serdes_wait_rx_valid(u32 lane, void __iomem *regs) |
202 | { | 238 | { |
203 | unsigned long timeout = jiffies | 239 | unsigned long timeout = jiffies |
204 | + msecs_to_jiffies(KEYSTONE_SERDES_TIMEOUT); | 240 | + msecs_to_jiffies(KEYSTONE_SERDES_TIMEOUT); |
@@ -227,7 +263,7 @@ static int k2_rio_serdes_wait_rx_valid(void __iomem *regs, int lane) | |||
227 | /* | 263 | /* |
228 | * Allow Serdes to re-acquire Signal Detect | 264 | * Allow Serdes to re-acquire Signal Detect |
229 | */ | 265 | */ |
230 | static inline void k2_rio_serdes_reacquire_sd(void __iomem *regs, int lane) | 266 | static inline void k2_rio_serdes_reacquire_sd(u32 lane, void __iomem *regs) |
231 | { | 267 | { |
232 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 2, 1, 0x0); | 268 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 2, 1, 0x0); |
233 | } | 269 | } |
@@ -241,10 +277,11 @@ static inline u32 k2_rio_serdes_get_termination(void __iomem *regs) | |||
241 | } | 277 | } |
242 | 278 | ||
243 | /* | 279 | /* |
244 | * Set the TX termination | 280 | * Set the Tx termination |
245 | */ | 281 | */ |
246 | static void k2_rio_serdes_termination_config(void __iomem *regs, | 282 | static void k2_rio_serdes_termination_config(u32 lane, |
247 | u32 lane, u32 tx_term_np) | 283 | void __iomem *regs, |
284 | u32 tx_term_np) | ||
248 | { | 285 | { |
249 | /* Set tx termination */ | 286 | /* Set tx termination */ |
250 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x7c, 24, 8, tx_term_np); | 287 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x7c, 24, 8, tx_term_np); |
@@ -253,19 +290,19 @@ static void k2_rio_serdes_termination_config(void __iomem *regs, | |||
253 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x7c, 20, 1, 1); | 290 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x7c, 20, 1, 1); |
254 | } | 291 | } |
255 | 292 | ||
256 | static void k2_rio_serdes_display_att_boost(void __iomem *regs, u32 lane, | 293 | static inline void k2_rio_serdes_get_att_boost( |
257 | struct device *dev) | 294 | u32 lane, |
295 | void __iomem *regs, | ||
296 | struct keystone_serdes_lane_rx_config *rx_coeff) | ||
258 | { | 297 | { |
259 | u32 att; | 298 | u32 att; |
260 | u32 boost; | 299 | u32 boost; |
261 | 300 | ||
262 | /* Read attenuation and boost */ | 301 | /* Read attenuation and boost */ |
263 | att = boost = k2_rio_serdes_sb_read_selected_tbus(regs, lane + 1, 0x11); | 302 | att = boost = k2_rio_serdes_sb_read_selected_tbus(regs, |
264 | att = (att >> 4) & 0x0f; | 303 | lane + 1, 0x11); |
265 | boost = (boost >> 8) & 0x0f; | 304 | rx_coeff->att = (att >> 4) & 0x0f; |
266 | 305 | rx_coeff->boost = (boost >> 8) & 0x0f; | |
267 | dev_dbg(dev, "SerDes: lane %d att = %d, boost = %d\n", | ||
268 | lane, att, boost); | ||
269 | 306 | ||
270 | return; | 307 | return; |
271 | } | 308 | } |
@@ -275,23 +312,27 @@ static void k2_rio_serdes_display_att_boost(void __iomem *regs, u32 lane, | |||
275 | * adapting to the un-terminated Tx and un-programmed pre and post cursor | 312 | * adapting to the un-terminated Tx and un-programmed pre and post cursor |
276 | * settings | 313 | * settings |
277 | */ | 314 | */ |
278 | static inline void k2_rio_serdes_force_tx_idle(void __iomem *regs, u32 lane) | 315 | static inline void k2_rio_serdes_force_tx_idle(u32 lane, void __iomem *regs) |
279 | { | 316 | { |
317 | reg_fill_field(regs + (0x200 * lane) + 0x200 + 0xb8, 16, 2, 3); | ||
280 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 24, 2, 3); | 318 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 24, 2, 3); |
319 | reg_fill_field(regs + (0x200 * lane) + 0x200 + 0x28, 20, 2, 0); | ||
281 | } | 320 | } |
282 | 321 | ||
283 | static inline void k2_rio_serdes_force_tx_normal(void __iomem *regs, u32 lane) | 322 | static inline void k2_rio_serdes_force_tx_normal(u32 lane, void __iomem *regs) |
284 | { | 323 | { |
324 | reg_fill_field(regs + (0x200 * lane) + 0x200 + 0xb8, 16, 2, 0); | ||
285 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 24, 2, 0); | 325 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 24, 2, 0); |
326 | reg_fill_field(regs + (0x200 * lane) + 0x200 + 0x28, 20, 2, 3); | ||
286 | } | 327 | } |
287 | 328 | ||
288 | static inline void k2_rio_serdes_force_rx_disable(void __iomem *regs, u32 lane) | 329 | static inline void k2_rio_serdes_force_rx_disable(u32 lane, void __iomem *regs) |
289 | { | 330 | { |
290 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 15, 1, 1); | 331 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 15, 1, 1); |
291 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 13, 2, 0); | 332 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 13, 2, 0); |
292 | } | 333 | } |
293 | 334 | ||
294 | static inline void k2_rio_serdes_force_rx_enable(void __iomem *regs, u32 lane) | 335 | static inline void k2_rio_serdes_force_rx_enable(u32 lane, void __iomem *regs) |
295 | { | 336 | { |
296 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 15, 1, 1); | 337 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 15, 1, 1); |
297 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 13, 2, 3); | 338 | reg_fill_field(regs + (lane * 4) + 0x1fc0 + 0x20, 13, 2, 3); |
@@ -300,8 +341,8 @@ static inline void k2_rio_serdes_force_rx_enable(void __iomem *regs, u32 lane) | |||
300 | /* | 341 | /* |
301 | * Function to reset the Clock Data Recovery, attenuation and boost circuitry | 342 | * Function to reset the Clock Data Recovery, attenuation and boost circuitry |
302 | */ | 343 | */ |
303 | static inline void k2_rio_serdes_reset_cdr_att_boost(void __iomem *regs, | 344 | static inline void k2_rio_serdes_reset_cdr_att_boost(u32 lane, |
304 | u32 lane) | 345 | void __iomem *regs) |
305 | { | 346 | { |
306 | reg_finsr(regs + 0x004 + (0x200 * (lane + 1)), 2, 1, 0x2); | 347 | reg_finsr(regs + 0x004 + (0x200 * (lane + 1)), 2, 1, 0x2); |
307 | } | 348 | } |
@@ -311,8 +352,8 @@ static inline void k2_rio_serdes_reset_cdr_att_boost(void __iomem *regs, | |||
311 | */ | 352 | */ |
312 | static int k2_rio_serdes_wait_lanes_ok(u32 lanes, void __iomem *regs) | 353 | static int k2_rio_serdes_wait_lanes_ok(u32 lanes, void __iomem *regs) |
313 | { | 354 | { |
314 | u32 val; | ||
315 | unsigned long timeout; | 355 | unsigned long timeout; |
356 | u32 val; | ||
316 | u32 val_mask; | 357 | u32 val_mask; |
317 | 358 | ||
318 | /* LNn_OK_STATE bits */ | 359 | /* LNn_OK_STATE bits */ |
@@ -328,7 +369,7 @@ static int k2_rio_serdes_wait_lanes_ok(u32 lanes, void __iomem *regs) | |||
328 | break; | 369 | break; |
329 | 370 | ||
330 | if (time_after(jiffies, timeout)) | 371 | if (time_after(jiffies, timeout)) |
331 | return -1; | 372 | return -EAGAIN; |
332 | 373 | ||
333 | usleep_range(10, 50); | 374 | usleep_range(10, 50); |
334 | } | 375 | } |
@@ -340,11 +381,14 @@ static int k2_rio_serdes_wait_lanes_ok(u32 lanes, void __iomem *regs) | |||
340 | * Wait signal detect by checking LNn_SD_STATE bits in addition to LNn_OK_STATE | 381 | * Wait signal detect by checking LNn_SD_STATE bits in addition to LNn_OK_STATE |
341 | * bits | 382 | * bits |
342 | */ | 383 | */ |
343 | static int k2_rio_serdes_wait_lanes_sd(u32 lanes, void __iomem *regs) | 384 | static int k2_rio_serdes_wait_lanes_sd(u32 lanes, |
385 | struct keystone_serdes_data *serdes) | ||
344 | { | 386 | { |
345 | u32 val; | 387 | void __iomem *regs = serdes->regs; |
346 | unsigned long timeout; | 388 | unsigned long timeout; |
389 | u32 val; | ||
347 | u32 val_mask; | 390 | u32 val_mask; |
391 | u32 lane; | ||
348 | 392 | ||
349 | /* LNn_SD_STATE and LNn_OK_STATE bits */ | 393 | /* LNn_SD_STATE and LNn_OK_STATE bits */ |
350 | val_mask = lanes | (lanes << 8); | 394 | val_mask = lanes | (lanes << 8); |
@@ -359,18 +403,33 @@ static int k2_rio_serdes_wait_lanes_sd(u32 lanes, void __iomem *regs) | |||
359 | break; | 403 | break; |
360 | 404 | ||
361 | if (time_after(jiffies, timeout)) | 405 | if (time_after(jiffies, timeout)) |
362 | return -1; | 406 | return -EAGAIN; |
363 | 407 | ||
364 | usleep_range(10, 50); | 408 | usleep_range(10, 50); |
365 | } | 409 | } |
366 | 410 | ||
411 | /* Display Rx att/boost values */ | ||
412 | for_each_lanes(lanes, lane) { | ||
413 | /* Get the current Rx att/boost values */ | ||
414 | k2_rio_serdes_get_att_boost( | ||
415 | lane, | ||
416 | regs, | ||
417 | &(serdes->config->rx[lane])); | ||
418 | |||
419 | dev_dbg(serdes->dev, | ||
420 | "SerDes: Rx signal detected, att = %d, boost = %d for lane %d\n", | ||
421 | serdes->config->rx[lane].att, | ||
422 | serdes->config->rx[lane].boost, | ||
423 | lane); | ||
424 | } | ||
425 | |||
367 | return 0; | 426 | return 0; |
368 | } | 427 | } |
369 | 428 | ||
370 | /* | 429 | /* |
371 | * Assert reset while preserving the lnX_ctrl_i bits | 430 | * Assert reset while preserving the lnX_ctrl_i bits |
372 | */ | 431 | */ |
373 | static void k2_rio_serdes_sb_assert_reset(void __iomem *regs, u32 lane) | 432 | static void k2_rio_serdes_sb_assert_reset(u32 lane, void __iomem *regs) |
374 | { | 433 | { |
375 | unsigned int ui_tmpo; | 434 | unsigned int ui_tmpo; |
376 | unsigned int ui_tmp0; | 435 | unsigned int ui_tmp0; |
@@ -393,17 +452,17 @@ static void k2_rio_serdes_sb_assert_reset(void __iomem *regs, u32 lane) | |||
393 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 15, 15, ui_tmpo); | 452 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 15, 15, ui_tmpo); |
394 | } | 453 | } |
395 | 454 | ||
396 | static inline void k2_rio_serdes_sb_assert_full_reset(void __iomem *regs, | 455 | static inline void k2_rio_serdes_sb_assert_full_reset(u32 lane, |
397 | u32 lane) | 456 | void __iomem *regs) |
398 | { | 457 | { |
399 | /* Toggle bit 29 of LANE_028 */ | 458 | /* Toggle bit 29 of LANE_028 */ |
400 | reg_finsr(regs + (0 * 0x200) + (1 * 0x200) + 0x200 + 0x28, 29, 15, | 459 | reg_finsr(regs + (0 * 0x200) + (1 * 0x200) + 0x200 + 0x28, 29, 15, |
401 | 0x4260); | 460 | 0x4260); |
402 | } | 461 | } |
403 | 462 | ||
404 | static inline int k2_rio_serdes_sb_deassert_reset(void __iomem *regs, | 463 | static inline int k2_rio_serdes_sb_deassert_reset(u32 lane, |
405 | u32 block, | 464 | void __iomem *regs, |
406 | u32 lane) | 465 | u32 block) |
407 | { | 466 | { |
408 | /* Clear the reset bit */ | 467 | /* Clear the reset bit */ |
409 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 15, 1, 1); | 468 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 15, 1, 1); |
@@ -415,12 +474,18 @@ static inline int k2_rio_serdes_sb_deassert_reset(void __iomem *regs, | |||
415 | return 0; | 474 | return 0; |
416 | } | 475 | } |
417 | 476 | ||
418 | static void k2_rio_serdes_sb_clear_overlay_bit29(void __iomem *regs, u32 lane) | 477 | static void k2_rio_serdes_sb_clear_overlay_bit29(u32 lane, void __iomem *regs) |
419 | { | 478 | { |
420 | /* Clear overlay bit, bring the lane out of reset */ | 479 | /* Clear overlay bit, bring the lane out of reset */ |
421 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 29, 1, 0); | 480 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 29, 1, 0); |
422 | } | 481 | } |
423 | 482 | ||
483 | static void k2_rio_serdes_sb_set_overlay_bit29(u32 lane, void __iomem *regs) | ||
484 | { | ||
485 | /* Clear overlay bit, bring the lane out of reset */ | ||
486 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x28, 29, 1, 1); | ||
487 | } | ||
488 | |||
424 | static void k2_rio_serdes_init_3g(void __iomem *reg) | 489 | static void k2_rio_serdes_init_3g(void __iomem *reg) |
425 | { | 490 | { |
426 | /* Uses 6G half rate configuration */ | 491 | /* Uses 6G half rate configuration */ |
@@ -703,12 +768,12 @@ static void k2_rio_serdes_init_5g(void __iomem *reg) | |||
703 | reg_finsr((reg + 0x0a00), 7, 0, 0x5f); | 768 | reg_finsr((reg + 0x0a00), 7, 0, 0x5f); |
704 | } | 769 | } |
705 | 770 | ||
706 | static void k2_rio_serdes_lane_init(u32 lane, u32 rate, void __iomem *regs) | 771 | static void k2_rio_serdes_lane_init(u32 lane, void __iomem *regs, u32 rate) |
707 | { | 772 | { |
708 | /* Bring this lane out of reset by clearing override bit 29 */ | 773 | /* Bring this lane out of reset by clearing override bit 29 */ |
709 | k2_rio_serdes_sb_clear_overlay_bit29(regs, lane); | 774 | k2_rio_serdes_sb_clear_overlay_bit29(lane, regs); |
710 | 775 | ||
711 | /* Set lane control rate, force lane enable, rates, width and tx idle */ | 776 | /* Set lane control rate, force lane enable, rates, width and Tx idle */ |
712 | switch (rate) { | 777 | switch (rate) { |
713 | case KEYSTONE_SERDES_FULL_RATE: | 778 | case KEYSTONE_SERDES_FULL_RATE: |
714 | __raw_writel(0xf3c0f0f0, regs + 0x1fe0 + (4 * lane)); | 779 | __raw_writel(0xf3c0f0f0, regs + 0x1fe0 + (4 * lane)); |
@@ -739,41 +804,88 @@ static inline void k2_rio_serdes_lane_disable(u32 lane, void __iomem *regs) | |||
739 | } | 804 | } |
740 | 805 | ||
741 | /* | 806 | /* |
742 | * Forces the calibration of the SerDes receiver settings of attenuation | 807 | * Force the calibration of the SerDes receiver settings of att circuitry |
743 | * and boost circuitry. | 808 | * for all configured lanes |
744 | * | 809 | * |
745 | * This is only valid for SerDes PHY-A (i.e. all SerDes except XGE) | ||
746 | */ | 810 | */ |
747 | static void k2_rio_serdes_force_att_boost(void __iomem *regs, u32 lane) | 811 | static int k2_rio_serdes_force_att_calibration(u32 lanes, |
812 | void __iomem *regs, | ||
813 | u32 rate) | ||
748 | { | 814 | { |
749 | u32 boost_read = 0; | 815 | int res = 0; |
750 | u32 att_read = 0; | 816 | u32 lane; |
751 | u32 att_start = 0; | 817 | u32 att_read[KEYSTONE_SERDES_MAX_LANES]; |
752 | 818 | u32 att_start[KEYSTONE_SERDES_MAX_LANES]; | |
753 | if (k2_rio_serdes_wait_rx_valid(regs, lane)) | 819 | u32 reg; |
754 | return; | 820 | u32 shift; |
821 | |||
822 | /* Register offsert and field shift of att starrt for various rates */ | ||
823 | static struct k2_rio_serdes_reg_field __k2_rio_serdes_att_start[3] = { | ||
824 | { 0x84, 16 }, | ||
825 | { 0x84, 24 }, | ||
826 | { 0x8c, 8 }, | ||
827 | }; | ||
828 | |||
829 | /* Compute the rx att start field location corresponding to the rate */ | ||
830 | reg = __k2_rio_serdes_att_start[rate].reg; | ||
831 | shift = __k2_rio_serdes_att_start[rate].shift; | ||
755 | 832 | ||
756 | /* First read initial att start value */ | 833 | /* First read initial att start value */ |
757 | att_start = (__raw_readl(regs + (lane * 0x200) + 0x200 + 0x8c) | 834 | for_each_lanes(lanes, lane) |
758 | >> 8) & 0xf; | 835 | att_start[lane] = |
836 | (__raw_readl(regs + (lane * 0x200) + 0x200 + reg) | ||
837 | >> shift) & 0xf; | ||
759 | 838 | ||
760 | /* | 839 | /* |
761 | * Check att value, fix this as start value turn off att adaptation | 840 | * Check att value, fix this as start value turn off att adaptation |
762 | * and do boost readaptation | 841 | * and do boost readaptation |
763 | */ | 842 | */ |
764 | att_read = (k2_rio_serdes_sb_read_selected_tbus(regs, lane + 1, 0x11) | 843 | for_each_lanes(lanes, lane) |
765 | >> 4) & 0xf; | 844 | att_read[lane] = |
766 | 845 | (k2_rio_serdes_sb_read_selected_tbus(regs, lane + 1, 0x11) | |
767 | /* att_start */ | 846 | >> 4) & 0xf; |
768 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x8c, 8, 4, att_read); | 847 | |
769 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x84, 0, 1, 0); | 848 | /* Set att_start */ |
849 | for_each_lanes(lanes, lane) | ||
850 | reg_fill_field(regs + (lane * 0x200) + 0x200 + reg, | ||
851 | shift, 4, att_read[lane]); | ||
852 | |||
853 | /* Clear att init cal and att recal */ | ||
854 | reg_fill_field(regs + 0x0a00 + 0x84, 0, 1, 0); | ||
770 | reg_fill_field(regs + 0x0a00 + 0x8c, 24, 1, 0); | 855 | reg_fill_field(regs + 0x0a00 + 0x8c, 24, 1, 0); |
771 | 856 | ||
772 | /* Force cal */ | 857 | /* Force calibration for all lanes */ |
773 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0xac, 11, 1, 1); | 858 | reg_fill_field(regs + 0x0a00 + 0x98, 7, 1, 1); |
774 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0xac, 11, 1, 0); | 859 | reg_fill_field(regs + 0x0a00 + 0x98, 7, 1, 0); |
860 | |||
861 | /* Check RX valid */ | ||
862 | for_each_lanes(lanes, lane) { | ||
863 | if (k2_rio_serdes_wait_rx_valid(lane, regs)) | ||
864 | res = 1; | ||
865 | |||
866 | /* Write back initial att start value */ | ||
867 | reg_fill_field(regs + (lane * 0x200) + 0x200 + reg, shift, 4, | ||
868 | att_start[lane]); | ||
869 | } | ||
870 | |||
871 | /* Turn back on att adaptation */ | ||
872 | reg_fill_field(regs + 0x0a00 + 0x84, 0, 1, 1); | ||
873 | reg_fill_field(regs + 0x0a00 + 0x8c, 24, 1, 1); | ||
874 | |||
875 | return res; | ||
876 | } | ||
775 | 877 | ||
776 | k2_rio_serdes_wait_rx_valid(regs, lane); | 878 | /* |
879 | * Force the calibration of the SerDes receiver settings of boost circuitry | ||
880 | * | ||
881 | */ | ||
882 | static int k2_rio_serdes_force_boost_calibration(u32 lane, | ||
883 | void __iomem *regs) | ||
884 | { | ||
885 | u32 boost_read = 0; | ||
886 | |||
887 | if (k2_rio_serdes_wait_rx_valid(lane, regs)) | ||
888 | return -1; | ||
777 | 889 | ||
778 | /* Check boost value */ | 890 | /* Check boost value */ |
779 | boost_read = (k2_rio_serdes_sb_read_selected_tbus(regs, lane + 1, 0x11) | 891 | boost_read = (k2_rio_serdes_sb_read_selected_tbus(regs, lane + 1, 0x11) |
@@ -802,14 +914,149 @@ static void k2_rio_serdes_force_att_boost(void __iomem *regs, u32 lane) | |||
802 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x2c, 3, 7, 0x0); | 914 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x2c, 3, 7, 0x0); |
803 | 915 | ||
804 | do_not_inc: | 916 | do_not_inc: |
805 | /* Write back initial att start value */ | 917 | if (k2_rio_serdes_wait_rx_valid(lane, regs)) |
806 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x8c, 8, 4, att_start); | 918 | return -1; |
807 | 919 | ||
808 | /* Turn back on att adaptation */ | 920 | return 0; |
809 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x84, 0, 1, 1); | 921 | } |
810 | reg_fill_field(regs + 0x0a00 + 0x8c, 24, 1, 1); | 922 | |
923 | /* | ||
924 | * Calibrates the SerDes receiver by finding the averaging values for | ||
925 | * attenuation and boost coefficients | ||
926 | */ | ||
927 | static void k2_rio_serdes_att_boost_calibration( | ||
928 | u32 lane, | ||
929 | u32 lanes, | ||
930 | void __iomem *regs, | ||
931 | struct keystone_serdes_lane_rx_config *rx_coeff, | ||
932 | u32 rate) | ||
933 | { | ||
934 | u32 repeat_index; | ||
935 | int att = 0, num_att = 0, boost = 0, num_boost = 0; | ||
936 | int att_array[KEYSTONE_SERDES_ATT_BOOST_NUM_REPEAT]; | ||
937 | int boost_array[KEYSTONE_SERDES_ATT_BOOST_NUM_REPEAT]; | ||
938 | int res; | ||
939 | |||
940 | for (repeat_index = 0; | ||
941 | repeat_index < KEYSTONE_SERDES_ATT_BOOST_NUM_REPEAT; | ||
942 | repeat_index++) { | ||
943 | |||
944 | /* Wait SerDes Rx valid */ | ||
945 | if (k2_rio_serdes_wait_rx_valid(lane, regs)) { | ||
946 | att = boost = -1; | ||
947 | goto skip; | ||
948 | } | ||
949 | |||
950 | /* Force att calibration for all lanes */ | ||
951 | (void) k2_rio_serdes_force_att_calibration(lanes, regs, rate); | ||
952 | |||
953 | /* Force boost calibration */ | ||
954 | res = k2_rio_serdes_force_boost_calibration(lane, regs); | ||
955 | if (res < 0) { | ||
956 | att = boost = -1; | ||
957 | goto skip; | ||
958 | } | ||
959 | |||
960 | /* Record adapted att and boost into an array */ | ||
961 | att = boost = k2_rio_serdes_sb_read_selected_tbus(regs, | ||
962 | lane + 1, | ||
963 | 0x11); | ||
964 | att = (att >> 4) & 0x0f; | ||
965 | boost = (boost >> 8) & 0x0f; | ||
966 | |||
967 | skip: | ||
968 | att_array[repeat_index] = att; | ||
969 | boost_array[repeat_index] = boost; | ||
970 | |||
971 | k2_rio_serdes_reset_cdr_att_boost(lane, regs); | ||
972 | |||
973 | /* Wait at least 10 usecs */ | ||
974 | usleep_range(10, 50); | ||
975 | |||
976 | /* Allow Serdes to re-acquire Signal Detect */ | ||
977 | k2_rio_serdes_reacquire_sd(lane, regs); | ||
978 | } | ||
979 | |||
980 | /* Perform statistical analysis on saved att, boost values */ | ||
981 | att = boost = num_att = num_boost = 0; | ||
982 | |||
983 | for (repeat_index = 0; | ||
984 | repeat_index < KEYSTONE_SERDES_ATT_BOOST_NUM_REPEAT; | ||
985 | repeat_index++) { | ||
986 | if ((att_array[repeat_index] > 0) | ||
987 | && (att_array[repeat_index] | ||
988 | < KEYSTONE_SERDES_ATT_BOOST_REPEAT_MEAN)) { | ||
989 | att += att_array[repeat_index]; | ||
990 | num_att++; | ||
991 | } | ||
992 | |||
993 | if ((boost_array[repeat_index] > 0) | ||
994 | && (boost_array[repeat_index] | ||
995 | < KEYSTONE_SERDES_ATT_BOOST_REPEAT_MEAN)) { | ||
996 | boost += boost_array[repeat_index]; | ||
997 | num_boost++; | ||
998 | } | ||
999 | } | ||
1000 | |||
1001 | rx_coeff[lane].mean_att = (num_att > 0) ? | ||
1002 | (((att << 4) / num_att) + 8) >> 4 : -1; | ||
1003 | |||
1004 | rx_coeff[lane].mean_boost = (num_boost > 0) ? | ||
1005 | (((boost << 4) / num_boost) + 8) >> 4 : -1; | ||
1006 | } | ||
1007 | |||
1008 | /* | ||
1009 | * Disable Rx att and boost initial calibration and then set att and boost start | ||
1010 | * values to the mean values. | ||
1011 | */ | ||
1012 | static void k2_rio_serdes_set_att_boost( | ||
1013 | u32 lane, | ||
1014 | void __iomem *regs, | ||
1015 | struct keystone_serdes_lane_rx_config *rx_coeff) | ||
1016 | { | ||
1017 | /* Disable lane in Rx */ | ||
1018 | k2_rio_serdes_force_rx_disable(lane, regs); | ||
1019 | |||
1020 | /* Disable Rx calibration for all rates (RATE1, RATE2, RATE3) */ | ||
1021 | reg_finsr(regs + 0xa00 + 0x84, 10, 8, 0x0); | ||
1022 | |||
1023 | if (rx_coeff->mean_att != -1) { | ||
1024 | |||
1025 | /* Disable att init cal */ | ||
1026 | reg_finsr(regs + 0xa00 + 0x84, 0, 0, 0x0); | ||
1027 | |||
1028 | /* Disable att recal */ | ||
1029 | reg_finsr(regs + 0xa00 + 0x8c, 24, 24, 0x0); | ||
1030 | |||
1031 | /* Set att for all rates */ | ||
1032 | reg_finsr(regs + 0x200 * (lane + 1) + 0x8c, 11, 8, | ||
1033 | rx_coeff->mean_att); | ||
1034 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 27, 24, | ||
1035 | rx_coeff->mean_att); | ||
1036 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 19, 16, | ||
1037 | rx_coeff->mean_att); | ||
1038 | } | ||
1039 | |||
1040 | if (rx_coeff->mean_boost != -1) { | ||
1041 | |||
1042 | /* Disable boost init cal */ | ||
1043 | reg_finsr(regs + 0xa00 + 0x84, 1, 1, 0x0); | ||
1044 | |||
1045 | /* Disable boost recal */ | ||
1046 | reg_finsr(regs + 0xa00 + 0x8c, 25, 25, 0x0); | ||
1047 | |||
1048 | /* Set boost for all rates */ | ||
1049 | reg_finsr(regs + 0x200 * (lane + 1) + 0x8c, 15, 12, | ||
1050 | rx_coeff->mean_boost); | ||
1051 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 31, 28, | ||
1052 | rx_coeff->mean_boost); | ||
1053 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 23, 20, | ||
1054 | rx_coeff->mean_boost); | ||
1055 | } | ||
1056 | |||
1057 | /* Enable lane in Rx */ | ||
1058 | k2_rio_serdes_force_rx_enable(lane, regs); | ||
811 | 1059 | ||
812 | k2_rio_serdes_wait_rx_valid(regs, lane); | ||
813 | } | 1060 | } |
814 | 1061 | ||
815 | static inline void k2_rio_serdes_config_set_tx_coeffs( | 1062 | static inline void k2_rio_serdes_config_set_tx_coeffs( |
@@ -819,7 +1066,15 @@ static inline void k2_rio_serdes_config_set_tx_coeffs( | |||
819 | { | 1066 | { |
820 | u32 val; | 1067 | u32 val; |
821 | 1068 | ||
822 | /* Set C1/C2/CM coefficients */ | 1069 | /* Ensure we do not override out of bound bits */ |
1070 | tx_config->c1_coeff &= 0x1f; /* 5 bits */ | ||
1071 | tx_config->c2_coeff &= 0xf; /* 4 bits */ | ||
1072 | tx_config->cm_coeff &= 0xf; /* 4 bits */ | ||
1073 | tx_config->pre_1lsb &= 0x1; /* 1 bits */ | ||
1074 | tx_config->att &= 0xf; /* 4 bits */ | ||
1075 | tx_config->vreg &= 0x7; /* 4 bits */ | ||
1076 | |||
1077 | /* Set C1, C2, CM coefficients */ | ||
823 | val = (tx_config->c1_coeff) | 1078 | val = (tx_config->c1_coeff) |
824 | | ((tx_config->c2_coeff) << 8) | 1079 | | ((tx_config->c2_coeff) << 8) |
825 | | ((tx_config->cm_coeff) << 12); | 1080 | | ((tx_config->cm_coeff) << 12); |
@@ -834,18 +1089,631 @@ static inline void k2_rio_serdes_config_set_tx_coeffs( | |||
834 | 0x000000e0); | 1089 | 0x000000e0); |
835 | } | 1090 | } |
836 | 1091 | ||
1092 | static void k2_rio_serdes_config_set_rx_coeffs( | ||
1093 | u32 lanes, | ||
1094 | void __iomem *regs, | ||
1095 | struct device *dev, | ||
1096 | struct keystone_serdes_lane_rx_config *rx_config) | ||
1097 | { | ||
1098 | u32 lane; | ||
1099 | |||
1100 | /* Set Rx att/boost */ | ||
1101 | for_each_lanes(lanes, lane) { | ||
1102 | /* | ||
1103 | * We need to have at least one correct value before disabling | ||
1104 | * the dynamic Rx att/boost calibration | ||
1105 | */ | ||
1106 | if ((rx_config[lane].mean_att == -1) && | ||
1107 | (rx_config[lane].mean_boost == -1)) | ||
1108 | continue; | ||
1109 | |||
1110 | /* Force signal detect low, reset CDR, attenuation and boost */ | ||
1111 | k2_rio_serdes_reset_cdr_att_boost(lane, regs); | ||
1112 | |||
1113 | usleep_range(10, 50); | ||
1114 | |||
1115 | dev_dbg(dev, | ||
1116 | "SerDes: applying computed Rx att = %d, Rx boost = %d for lane %d\n", | ||
1117 | rx_config[lane].mean_att, | ||
1118 | rx_config[lane].mean_boost, | ||
1119 | lane); | ||
1120 | |||
1121 | /* Apply Rx att/boost values */ | ||
1122 | k2_rio_serdes_set_att_boost(lane, regs, | ||
1123 | &(rx_config[lane])); | ||
1124 | |||
1125 | /* Allow SerDes to re-acquire signal detect */ | ||
1126 | k2_rio_serdes_reacquire_sd(lane, regs); | ||
1127 | |||
1128 | /* Wait at least 10 usecs */ | ||
1129 | usleep_range(10, 50); | ||
1130 | |||
1131 | /* Wait Rx valid */ | ||
1132 | k2_rio_serdes_wait_rx_valid(lane, regs); | ||
1133 | } | ||
1134 | |||
1135 | return; | ||
1136 | } | ||
1137 | |||
837 | /* | 1138 | /* |
838 | * Configure SerDes with appropriate baudrate and do Tx termination workaround | 1139 | * Set the SerDes Tx output swing voltage and boost/att start values |
839 | * Note that all lanes are configured but Serdes are then disabled | ||
840 | */ | 1140 | */ |
841 | static int k2_rio_serdes_config_lanes( | 1141 | static void k2_rio_serdes_tx_rx_set_equalizer(u32 lane, |
1142 | void __iomem *regs, | ||
1143 | int vreg_enable, | ||
1144 | u32 att_start, | ||
1145 | u32 boost_start) | ||
1146 | { | ||
1147 | /* Set Tx output swing voltage */ | ||
1148 | if (vreg_enable) { | ||
1149 | /* pma_ln_vreg */ | ||
1150 | reg_finsr(regs + 0x200 * (lane + 1) + 0x18, 25, 24, 0x2); | ||
1151 | |||
1152 | /* pma_ln_vregh */ | ||
1153 | reg_finsr(regs + 0x200 * (lane + 1) + 0x18, 27, 26, 0x2); | ||
1154 | } | ||
1155 | |||
1156 | /* Set Rx att start for all rates (RATE1, RATE2, RATE3) */ | ||
1157 | reg_finsr(regs + 0x200 * (lane + 1) + 0x8c, 11, 8, att_start); | ||
1158 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 27, 24, att_start); | ||
1159 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 19, 16, att_start); | ||
1160 | |||
1161 | /* Set Rx boost start for all rates (RATE1, RATE2, RATE3) */ | ||
1162 | reg_finsr(regs + 0x200 * (lane + 1) + 0x8c, 15, 12, boost_start); | ||
1163 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 31, 28, boost_start); | ||
1164 | reg_finsr(regs + 0x200 * (lane + 1) + 0x84, 23, 20, boost_start); | ||
1165 | } | ||
1166 | |||
1167 | /* | ||
1168 | * Calculate the SerDes average comparator/tap offset values | ||
1169 | */ | ||
1170 | static void k2_rio_serdes_get_average_offsets( | ||
842 | u32 lanes, | 1171 | u32 lanes, |
843 | u32 baud, | ||
844 | struct device *dev, | ||
845 | void __iomem *regs, | 1172 | void __iomem *regs, |
846 | void __iomem *sts_reg, | 1173 | struct k2_rio_serdes_tap_offsets *tap_offsets) |
847 | struct keystone_serdes_config *serdes_config) | ||
848 | { | 1174 | { |
1175 | u32 i, lane, comp; | ||
1176 | u32 cmp_offset_tmp; | ||
1177 | |||
1178 | /* Find average values */ | ||
1179 | for (i = 0; i < KEYSTONE_SERDES_OFFSETS_RETRIES; i++) { | ||
1180 | for_each_lanes(lanes, lane) { | ||
1181 | /* Serdes assert reset */ | ||
1182 | k2_rio_serdes_sb_assert_full_reset(lane, regs); | ||
1183 | |||
1184 | /* Serdes Deassert reset and wait lane ok */ | ||
1185 | k2_rio_serdes_sb_deassert_reset(lane, regs, 1); | ||
1186 | } | ||
1187 | |||
1188 | for_each_lanes(lanes, lane) { | ||
1189 | for (comp = 1; | ||
1190 | comp < KEYSTONE_SERDES_MAX_COMPS; | ||
1191 | comp++) { | ||
1192 | |||
1193 | /* Write comparator value */ | ||
1194 | reg_finsr(regs + 0x0a00 + 0x8c, 23, 21, comp); | ||
1195 | |||
1196 | /* Set tbus address */ | ||
1197 | reg_finsr(regs + 0x008, 31, 24, | ||
1198 | 0x12 + ((lane + 1) << 5)); | ||
1199 | |||
1200 | cmp_offset_tmp = ( | ||
1201 | k2_rio_serdes_sb_read_selected_tbus( | ||
1202 | regs, | ||
1203 | lane + 1, | ||
1204 | 0x12) & 0x0ff0) >> 4; | ||
1205 | |||
1206 | /* | ||
1207 | * Take a running count of comparator and tap | ||
1208 | * offsets for num_resets number of runs | ||
1209 | */ | ||
1210 | tap_offsets->cmp_offsets[lane][comp] += | ||
1211 | cmp_offset_tmp; | ||
1212 | } | ||
1213 | } | ||
1214 | } | ||
1215 | |||
1216 | /* Get average value for each comparator and tap offset */ | ||
1217 | for_each_lanes(lanes, lane) { | ||
1218 | for (comp = 1; comp < KEYSTONE_SERDES_MAX_COMPS; comp++) { | ||
1219 | /* Set comparator average */ | ||
1220 | tap_offsets->cmp_offsets[lane][comp] /= | ||
1221 | KEYSTONE_SERDES_OFFSETS_RETRIES; | ||
1222 | } | ||
1223 | } | ||
1224 | } | ||
1225 | |||
1226 | /* | ||
1227 | * Force Serdes comparator and tap offsets to override value | ||
1228 | */ | ||
1229 | static void k2_rio_serdes_override_cmp_tap_offsets( | ||
1230 | u32 lane, | ||
1231 | void __iomem *regs, | ||
1232 | u32 comp, | ||
1233 | struct k2_rio_serdes_tap_offsets *tap_offsets) | ||
1234 | |||
1235 | { | ||
1236 | /* Set DFE_SHADOW_LANE_SEL */ | ||
1237 | reg_finsr(regs + 0x0a00 + 0xf0, 27, 26, lane + 1); | ||
1238 | |||
1239 | /* Set CMP_OFFSET_OVR_EN to 0x1 */ | ||
1240 | reg_finsr(regs + 0x0a00 + 0x98, 24, 24, 0x1); | ||
1241 | |||
1242 | /* Set RXEQ_OVR_EN to 0x1 */ | ||
1243 | reg_finsr(regs + 0x200 * (lane + 1) + 0x2c, 2, 2, 0x1); | ||
1244 | |||
1245 | /* Set RXEQ_DFE_CMP_SEL_OVR to comp */ | ||
1246 | reg_finsr(regs + 0x200 * (lane + 1) + 0x30, 7, 5, comp); | ||
1247 | |||
1248 | /* Set DFE_TAP_OVR_EN to 0x1 */ | ||
1249 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 31, 31, 0x1); | ||
1250 | |||
1251 | /* Set CMP_OFFSET_OVR */ | ||
1252 | reg_finsr(regs + 0x0a00 + 0x9c, 7, 0, | ||
1253 | tap_offsets->cmp_offsets[lane][comp]); | ||
1254 | |||
1255 | /* Set tap overrides */ | ||
1256 | reg_finsr(regs + 0x200 * (lane + 1) + 0x58, 30, 24, | ||
1257 | tap_offsets->tap1_offsets[lane][comp]); | ||
1258 | |||
1259 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 5, 0, | ||
1260 | tap_offsets->tap2_offsets[lane][comp]); | ||
1261 | |||
1262 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 13, 8, | ||
1263 | tap_offsets->tap3_offsets[lane][comp]); | ||
1264 | |||
1265 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 21, 16, | ||
1266 | tap_offsets->tap4_offsets[lane][comp]); | ||
1267 | |||
1268 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 29, 24, | ||
1269 | tap_offsets->tap5_offsets[lane][comp]); | ||
1270 | |||
1271 | /* Set RXEQ_OVR_LATCH_O = 0x1 */ | ||
1272 | reg_finsr(regs + 0x200 * (lane + 1) + 0x2c, 10, 10, 0x1); | ||
1273 | |||
1274 | /* Set RXEQ_OVR_LATCH_O = 0x0 */ | ||
1275 | reg_finsr(regs + 0x200 * (lane + 1) + 0x2c, 10, 10, 0x0); | ||
1276 | |||
1277 | /* Set CMP_OFFSET_OVR_EN to 0x0 */ | ||
1278 | reg_finsr(regs + 0x0a00 + 0x98, 24, 24, 0x0); | ||
1279 | |||
1280 | /* Set RXEQ_OVR_EN to 0x0 */ | ||
1281 | reg_finsr(regs + 0x200 * (lane + 1) + 0x2c, 2, 2, 0x0); | ||
1282 | |||
1283 | /* Set DFE_TAP_OVR_EN to 0x0 */ | ||
1284 | reg_finsr(regs + 0x200 * (lane + 1) + 0x5c, 31, 31, 0x0); | ||
1285 | } | ||
1286 | |||
1287 | /* | ||
1288 | * Write out the average rx comparator offsets during every SerDes | ||
1289 | * initialization | ||
1290 | */ | ||
1291 | static void k2_rio_serdes_write_average_offsets( | ||
1292 | u32 lanes, | ||
1293 | void __iomem *regs, | ||
1294 | struct k2_rio_serdes_tap_offsets *tap_offsets) | ||
1295 | { | ||
1296 | u32 lane; | ||
1297 | u32 comp; | ||
1298 | |||
1299 | /* Rewrite average comparator and tap offsets to comparators/taps */ | ||
1300 | for_each_lanes(lanes, lane) { | ||
1301 | for (comp = 1; comp < KEYSTONE_SERDES_MAX_COMPS; comp++) { | ||
1302 | k2_rio_serdes_override_cmp_tap_offsets(lane, | ||
1303 | regs, | ||
1304 | comp, | ||
1305 | tap_offsets); | ||
1306 | } | ||
1307 | } | ||
1308 | } | ||
1309 | |||
1310 | /* | ||
1311 | * Calibrates the SerDes DFE | ||
1312 | */ | ||
1313 | static void k2_rio_serdes_dfe_offset_calibration( | ||
1314 | u32 lanes, | ||
1315 | void __iomem *regs, | ||
1316 | struct device *dev, | ||
1317 | struct keystone_serdes_lane_tx_config *tx_config) | ||
1318 | { | ||
1319 | struct k2_rio_serdes_tap_offsets tap_offsets; | ||
1320 | u32 lane; | ||
1321 | |||
1322 | /* Reset CDR, attenuation and boost */ | ||
1323 | for_each_lanes(lanes, lane) | ||
1324 | k2_rio_serdes_reset_cdr_att_boost(lane, regs); | ||
1325 | |||
1326 | /* Wait at least 10 usecs */ | ||
1327 | usleep_range(10, 50); | ||
1328 | |||
1329 | /* Compute average comparator/tap offsets */ | ||
1330 | k2_rio_serdes_get_average_offsets(lanes, regs, &tap_offsets); | ||
1331 | |||
1332 | /* Display comparators */ | ||
1333 | for_each_lanes(lanes, lane) { | ||
1334 | u32 i; | ||
1335 | |||
1336 | for (i = 1; i < KEYSTONE_SERDES_MAX_COMPS; i++) { | ||
1337 | dev_dbg(dev, | ||
1338 | "SerDes: %s() lane %d cmp_offsets[%d] %d\n", | ||
1339 | __func__, lane, i, | ||
1340 | tap_offsets.cmp_offsets[lane][i]); | ||
1341 | } | ||
1342 | } | ||
1343 | |||
1344 | dev_dbg(dev, "SerDes: %s() write average offsets\n", __func__); | ||
1345 | |||
1346 | /* Offset compensation workaround */ | ||
1347 | k2_rio_serdes_write_average_offsets(lanes, regs, &tap_offsets); | ||
1348 | |||
1349 | /* Wait at least 10 usecs */ | ||
1350 | usleep_range(10, 50); | ||
1351 | } | ||
1352 | |||
1353 | /* | ||
1354 | * Check that PHY has successfully detected the PRBS data or not | ||
1355 | */ | ||
1356 | static inline int k2_rio_serdes_wait_bist_chk_synch(u32 lanes, | ||
1357 | void __iomem *regs, | ||
1358 | int valid) | ||
1359 | { | ||
1360 | u32 lane; | ||
1361 | u32 temp; | ||
1362 | u32 bist_valid[KEYSTONE_SERDES_MAX_LANES]; | ||
1363 | unsigned long timeout = jiffies | ||
1364 | + msecs_to_jiffies(KEYSTONE_SERDES_TIMEOUT); | ||
1365 | |||
1366 | do { | ||
1367 | for_each_lanes(lanes, lane) { | ||
1368 | bist_valid[lane] = | ||
1369 | (k2_rio_serdes_sb_read_selected_tbus(regs, | ||
1370 | lane + 1, | ||
1371 | 0xc) | ||
1372 | & 0x0400) >> 10; | ||
1373 | |||
1374 | if ((__raw_readl(regs + 0x1fc0 + 0x34) | ||
1375 | & BIT(lane)) == 0) | ||
1376 | bist_valid[lane] = 0; | ||
1377 | } | ||
1378 | |||
1379 | temp = 1; | ||
1380 | for_each_lanes(lanes, lane) | ||
1381 | temp &= bist_valid[lane]; | ||
1382 | |||
1383 | if (time_after(jiffies, timeout)) | ||
1384 | return 1; | ||
1385 | |||
1386 | usleep_range(10, 50); | ||
1387 | |||
1388 | } while (temp != valid); | ||
1389 | |||
1390 | return 0; | ||
1391 | } | ||
1392 | |||
1393 | /* | ||
1394 | * Check the transmitter PRBS generator | ||
1395 | */ | ||
1396 | static int k2_rio_serdes_prbs_check(u32 lane, void __iomem *regs) | ||
1397 | { | ||
1398 | /* Clear BCHK_CLR */ | ||
1399 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 4, 4, 0x0); | ||
1400 | |||
1401 | /* Set BCHK_EN */ | ||
1402 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 3, 3, 0x1); | ||
1403 | |||
1404 | /* Check bist_valid for lane */ | ||
1405 | return k2_rio_serdes_wait_bist_chk_synch(BIT(lane), regs, 1); | ||
1406 | } | ||
1407 | |||
1408 | /* | ||
1409 | * Setting up the transmitter PRBS generator for BER testing | ||
1410 | */ | ||
1411 | static void k2_rio_serdes_ber_test_tx(u32 lanes, void __iomem *regs) | ||
1412 | { | ||
1413 | u32 lane; | ||
1414 | |||
1415 | for_each_lanes(lanes, lane) { | ||
1416 | /* Set bit 5 of LANE_034 to 0 (bist_gen_en) */ | ||
1417 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 5, 5, 0); | ||
1418 | |||
1419 | /* | ||
1420 | * Set bit 2 [bist_chk_data_mode], 6 [bist_tx_clk_en], | ||
1421 | * 7 [bist_rx_clk_en] of LANE_032 to 1 | ||
1422 | */ | ||
1423 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 22, 22, 1); | ||
1424 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 23, 23, 1); | ||
1425 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 18, 18, 1); | ||
1426 | |||
1427 | /* | ||
1428 | * Set bus width to 20 bit interface for SRIO SerDes | ||
1429 | * | ||
1430 | * Clear bit 0 [bist_gen_mode8B] of LANE_032 (PHY-A) and set | ||
1431 | * bit 1 of LANE_034 [bist_gen_word] | ||
1432 | */ | ||
1433 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 16, 16, 0); | ||
1434 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 6, 6, 1); | ||
1435 | |||
1436 | /* | ||
1437 | * Set bit 6 [bist_gen_word] & 7 [bist_gen_en] of LANE_034 | ||
1438 | * to 1 and 0 respectively | ||
1439 | */ | ||
1440 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 7, 7, 0); | ||
1441 | |||
1442 | /* Set bit 3 [bist_gen_send_pream] of LANE_037 to 0 */ | ||
1443 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 27, 27, 0); | ||
1444 | |||
1445 | /* Set bit 5:3 to 0x1 on LANE_032 to PRBS-31 */ | ||
1446 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 21, 19, | ||
1447 | KEYSTONE_SERDES_PRBS_31); | ||
1448 | } | ||
1449 | |||
1450 | /* | ||
1451 | * Set bit 1:0 of COMLANE_017 to 0 respectively | ||
1452 | * 1 bist_gen_inv_prbs, 0 bist_chk_inv_prbs | ||
1453 | */ | ||
1454 | reg_finsr(regs + (5 * 0x200) + 0x14, 25, 24, 0); | ||
1455 | |||
1456 | for_each_lanes(lanes, lane) { | ||
1457 | /* | ||
1458 | * Set LANE_033 and 034 bits 1:0 and 7:0 to 0x283 | ||
1459 | * (bist_chk_pream0) | ||
1460 | */ | ||
1461 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x30, 31, 24, 0x83); | ||
1462 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 1, 0, 0x2); | ||
1463 | |||
1464 | /* | ||
1465 | * Set LANE_036 and 035 bits 1:0 and 7:0 to 0x17C | ||
1466 | * (bist_chk_pream1) | ||
1467 | */ | ||
1468 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 17, 8, 0x17c); | ||
1469 | |||
1470 | /* | ||
1471 | * Clear LANE_038-03C; 042-043; 044-045; 03D-041: | ||
1472 | * 34[4:2]; 37 [6:4] & 47 [3:0], 46[7:0] | ||
1473 | * bist_chk_udp, bist_gen_en_low, bist_gen_en_high, | ||
1474 | * bist_chk_insert_word, bist_chk_insert_length, | ||
1475 | * bist_gen_insert_count, bist_gen_insert_delay | ||
1476 | */ | ||
1477 | __raw_writel(0, regs + (0x200 * lane) + 0x200 + 0x38); | ||
1478 | __raw_writel(0, regs + (0x200 * lane) + 0x200 + 0x3c); | ||
1479 | __raw_writel(0, regs + (0x200 * lane) + 0x200 + 0x40); | ||
1480 | |||
1481 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x44, 27, 0, 0x0); | ||
1482 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 4, 2, 0x0); | ||
1483 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 30, 28, 0x0); | ||
1484 | } | ||
1485 | |||
1486 | /* Wait a minimum of 20ns let us put 50ns just in case */ | ||
1487 | ndelay(50); | ||
1488 | |||
1489 | for_each_lanes(lanes, lane) { | ||
1490 | /* De-assert BIST_GEN_CDN by setting 1 on bit 5 of LANE_034 */ | ||
1491 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 5, 5, 0x1); | ||
1492 | |||
1493 | /* | ||
1494 | * Set LANE_000 [7:6] (dmux_txa_sel) to 0x2 and LANE_002 [6:4] | ||
1495 | * (dmux_txb_sel) to 0x0 | ||
1496 | */ | ||
1497 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x00, 7, 6, 0x2); | ||
1498 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x00, 22, 20, 0x0); | ||
1499 | } | ||
1500 | |||
1501 | /* Wait a minimum of 20ns let us put 50ns just in case */ | ||
1502 | ndelay(50); | ||
1503 | |||
1504 | /* Assert bist_gen_en by setting bit 7 of LANE_034 */ | ||
1505 | for_each_lanes(lanes, lane) | ||
1506 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 7, 7, 0x1); | ||
1507 | |||
1508 | /* Wait at least 10 usecs */ | ||
1509 | usleep_range(10, 50); | ||
1510 | |||
1511 | /* Signal detect enable */ | ||
1512 | for_each_lanes(lanes, lane) | ||
1513 | k2_rio_serdes_reacquire_sd(lane, regs); | ||
1514 | |||
1515 | /* Wait at least 10 usecs */ | ||
1516 | usleep_range(10, 50); | ||
1517 | |||
1518 | /* | ||
1519 | * Wait a minimum of 2us for the analog Tx/Rx paths to obtain the | ||
1520 | * bit lock on to the training pattern. | ||
1521 | * While this is ocurring set LANE_004 to [3] - 0, [4] - 1, [6:5] - 2 | ||
1522 | * (for PHY-A only). | ||
1523 | */ | ||
1524 | for_each_lanes(lanes, lane) | ||
1525 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 6, 3, | ||
1526 | (BIT(1) | (0x2 << 2))); | ||
1527 | |||
1528 | return; | ||
1529 | } | ||
1530 | |||
1531 | static int k2_rio_serdes_prbs_test_start(u32 lane, | ||
1532 | void __iomem *regs, | ||
1533 | struct device *dev) | ||
1534 | { | ||
1535 | int res; | ||
1536 | |||
1537 | dev_dbg(dev, "SerDes: enable the Tx PRBS pattern for lane %d\n", lane); | ||
1538 | |||
1539 | /* Enable the Tx PRBS pattern */ | ||
1540 | k2_rio_serdes_ber_test_tx(BIT(lane), regs); | ||
1541 | |||
1542 | dev_dbg(dev, "SerDes: check PRBS pattern for lane %d\n", lane); | ||
1543 | |||
1544 | res = k2_rio_serdes_prbs_check(lane, regs); | ||
1545 | if (res) { | ||
1546 | dev_dbg(dev, | ||
1547 | "SerDes: timeout when checking PRBS pattern for lane %d\n", | ||
1548 | lane); | ||
1549 | return -EAGAIN; | ||
1550 | } | ||
1551 | |||
1552 | return 0; | ||
1553 | } | ||
1554 | |||
1555 | static void k2_rio_serdes_prbs_test_stop(u32 lanes, | ||
1556 | void __iomem *regs, | ||
1557 | struct device *dev) | ||
1558 | { | ||
1559 | u32 lane; | ||
1560 | u32 value; | ||
1561 | |||
1562 | dev_dbg(dev, "SerDes: disable Tx PRBS pattern for lanes 0x%x\n", lanes); | ||
1563 | |||
1564 | for_each_lanes(lanes, lane) { | ||
1565 | /* Set BCHK_CLR */ | ||
1566 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 4, 4, 0x1); | ||
1567 | |||
1568 | /* Clear BCHK_EN */ | ||
1569 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x04, 3, 3, 0x0); | ||
1570 | |||
1571 | /* Set bit 5 of LANE_034 to 0 (bist_gen_en) */ | ||
1572 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x34, 5, 5, 0); | ||
1573 | } | ||
1574 | |||
1575 | /* Check bist_valid de-asserted for all lanes */ | ||
1576 | if (k2_rio_serdes_wait_bist_chk_synch(lanes, regs, 0)) | ||
1577 | dev_warn(dev, | ||
1578 | "SerDes: Tx PRBS not successfuly disabled for lanes 0x%x\n", | ||
1579 | lanes); | ||
1580 | |||
1581 | for_each_lanes(lanes, lane) { | ||
1582 | /* Verify BIST_CHK_ERRORS is 0 */ | ||
1583 | value = __raw_readl(regs + (0x200 * lane) + 0x200 + 0x48); | ||
1584 | if (value & 0xffff) | ||
1585 | dev_warn(dev, | ||
1586 | "SerDes: Tx PRBS BIST error detected (0x%x) for lanes 0x%x\n", | ||
1587 | value & 0xffff, lanes); | ||
1588 | |||
1589 | /* | ||
1590 | * Set LANE_000 [7:6] (dmux_txa_sel) and LANE_002 [6:4] | ||
1591 | * (dmux_txb_sel) to 0x0 | ||
1592 | */ | ||
1593 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x00, 7, 6, 0x0); | ||
1594 | reg_finsr(regs + (0x200 * lane) + 0x200 + 0x00, 22, 20, 0x0); | ||
1595 | |||
1596 | /* Wait 100 ns before PHY will be back in normal mode */ | ||
1597 | ndelay(100); | ||
1598 | } | ||
1599 | |||
1600 | return; | ||
1601 | } | ||
1602 | |||
1603 | static int __k2_rio_serdes_calibrate_lane( | ||
1604 | u32 lane, | ||
1605 | u32 lanes, | ||
1606 | struct keystone_serdes_data *serdes) | ||
1607 | { | ||
1608 | struct device *dev = serdes->dev; | ||
1609 | void __iomem *regs = serdes->regs; | ||
1610 | int res = 0; | ||
1611 | |||
1612 | /* Wait lanes OK and SD */ | ||
1613 | res = k2_rio_serdes_wait_lanes_sd(BIT(lane), serdes); | ||
1614 | if (res < 0) { | ||
1615 | dev_dbg(dev, "SerDes: %s() lane %d not OK\n", | ||
1616 | __func__, lane); | ||
1617 | return res; | ||
1618 | } | ||
1619 | |||
1620 | /* PRBS test to calibrate the attenuation and boost in the receiver */ | ||
1621 | res = k2_rio_serdes_prbs_test_start(lane, regs, dev); | ||
1622 | if (res != 0) | ||
1623 | return res; | ||
1624 | |||
1625 | /* Do the att/boost calibration */ | ||
1626 | dev_dbg(dev, "SerDes: do the att/boost calibration\n"); | ||
1627 | k2_rio_serdes_att_boost_calibration(lane, | ||
1628 | lanes, | ||
1629 | regs, | ||
1630 | serdes->config->rx, | ||
1631 | serdes->config->rate); | ||
1632 | |||
1633 | /* Display new computed att/boost values */ | ||
1634 | dev_dbg(dev, | ||
1635 | "SerDes: computed Rx att = %d, Rx boost = %d for lane %d\n", | ||
1636 | serdes->config->rx[lane].mean_att, | ||
1637 | serdes->config->rx[lane].mean_boost, | ||
1638 | lane); | ||
1639 | |||
1640 | return res; | ||
1641 | } | ||
1642 | |||
1643 | /* | ||
1644 | * Calibrate SerDes using PRBS training | ||
1645 | */ | ||
1646 | static int k2_rio_serdes_calibrate_lanes(u32 lanes, | ||
1647 | struct keystone_serdes_data *serdes) | ||
1648 | { | ||
1649 | unsigned long timeout = jiffies + msecs_to_jiffies( | ||
1650 | serdes->config->cal_timeout * MSEC_PER_SEC); | ||
1651 | struct device *dev = serdes->dev; | ||
1652 | void __iomem *regs = serdes->regs; | ||
1653 | int res = 0; | ||
1654 | u32 lane; | ||
1655 | u32 __lanes = lanes; | ||
1656 | |||
1657 | /* Do not use Rx coefficients yet */ | ||
1658 | for_each_lanes(lanes, lane) { | ||
1659 | serdes->config->rx[lane].mean_att = -1; | ||
1660 | serdes->config->rx[lane].mean_boost = -1; | ||
1661 | } | ||
1662 | |||
1663 | /* Start lanes */ | ||
1664 | k2_rio_serdes_start_tx_lanes(lanes, serdes); | ||
1665 | |||
1666 | /* Try to calibrate all lanes */ | ||
1667 | while (__lanes) { | ||
1668 | for (lane = 0; | ||
1669 | lane < KEYSTONE_SERDES_MAX_LANES; | ||
1670 | lane++) { | ||
1671 | if (BIT(lane) & __lanes) { | ||
1672 | /* Calibrate SerDes */ | ||
1673 | if (__k2_rio_serdes_calibrate_lane( | ||
1674 | lane, lanes, serdes) == 0) | ||
1675 | __lanes &= ~(BIT(lane)); | ||
1676 | } | ||
1677 | } | ||
1678 | |||
1679 | if (time_after(jiffies, timeout)) { | ||
1680 | res = -EAGAIN; | ||
1681 | break; | ||
1682 | } | ||
1683 | } | ||
1684 | |||
1685 | /* Wait at least 10ms for remote to finish */ | ||
1686 | usleep_range(10000, 20000); | ||
1687 | |||
1688 | /* Stop PRBS test and restore lanes to normal state */ | ||
1689 | k2_rio_serdes_prbs_test_stop(lanes, regs, dev); | ||
1690 | |||
1691 | /* Disable transmitter for all lanes */ | ||
1692 | for_each_lanes(lanes, lane) | ||
1693 | k2_rio_serdes_force_tx_idle(lane, regs); | ||
1694 | |||
1695 | /* Apply computed Rx coefficients */ | ||
1696 | k2_rio_serdes_config_set_rx_coeffs(lanes, serdes->regs, serdes->dev, | ||
1697 | serdes->config->rx); | ||
1698 | |||
1699 | /* Disable SerDes for these lanes */ | ||
1700 | for_each_lanes(lanes, lane) | ||
1701 | k2_rio_serdes_lane_disable(lane, regs); | ||
1702 | |||
1703 | return res; | ||
1704 | } | ||
1705 | |||
1706 | /* | ||
1707 | * Configure SerDes with appropriate baudrate and do Tx termination workaround | ||
1708 | * plus DFE offset calibration. | ||
1709 | * Note that all lanes are configured but Serdes are then disabled | ||
1710 | */ | ||
1711 | static int k2_rio_serdes_config_lanes(u32 lanes, | ||
1712 | u32 baud, | ||
1713 | struct keystone_serdes_data *serdes) | ||
1714 | { | ||
1715 | struct device *dev = serdes->dev; | ||
1716 | void __iomem *regs = serdes->regs; | ||
849 | u32 rate; | 1717 | u32 rate; |
850 | u32 val; | 1718 | u32 val; |
851 | u32 lane; | 1719 | u32 lane; |
@@ -878,18 +1746,19 @@ static int k2_rio_serdes_config_lanes( | |||
878 | return -EINVAL; | 1746 | return -EINVAL; |
879 | } | 1747 | } |
880 | 1748 | ||
1749 | /* Store current rate */ | ||
1750 | serdes->config->rate = rate; | ||
1751 | |||
881 | /* We need to always use lane 0 even if not part of the lane mask */ | 1752 | /* We need to always use lane 0 even if not part of the lane mask */ |
882 | lanes |= KEYSTONE_SERDES_LANE(0); | 1753 | lanes |= KEYSTONE_SERDES_LANE(0); |
883 | 1754 | ||
884 | /* Disable transmitter for all lanes */ | 1755 | /* Disable transmitter for all lanes */ |
885 | for_each_lanes(lanes, lane) { | 1756 | for_each_lanes(lanes, lane) |
886 | k2_rio_serdes_force_tx_idle(regs, lane); | 1757 | k2_rio_serdes_force_tx_idle(lane, regs); |
887 | } | ||
888 | 1758 | ||
889 | /* Initialize SerDes for requested lanes */ | 1759 | /* Initialize SerDes for requested lanes */ |
890 | for_each_lanes(lanes, lane) { | 1760 | for_each_lanes(lanes, lane) |
891 | k2_rio_serdes_lane_init(lane, rate, regs); | 1761 | k2_rio_serdes_lane_init(lane, regs, rate); |
892 | } | ||
893 | 1762 | ||
894 | /* Enable PLL via the PLL_ctrl */ | 1763 | /* Enable PLL via the PLL_ctrl */ |
895 | __raw_writel(0xe0000000, regs + 0x1ff4); | 1764 | __raw_writel(0xe0000000, regs + 0x1ff4); |
@@ -904,82 +1773,166 @@ static int k2_rio_serdes_config_lanes( | |||
904 | if (res < 0) { | 1773 | if (res < 0) { |
905 | dev_dbg(dev, "SerDes: %s() lane mask 0x%x not OK\n", | 1774 | dev_dbg(dev, "SerDes: %s() lane mask 0x%x not OK\n", |
906 | __func__, lanes); | 1775 | __func__, lanes); |
907 | return -1; | 1776 | return res; |
908 | } | 1777 | } |
909 | 1778 | ||
910 | /* Read the Tx termination */ | 1779 | /* Read the Tx termination */ |
911 | tx_term_np = k2_rio_serdes_get_termination(regs); | 1780 | tx_term_np = k2_rio_serdes_get_termination(regs); |
912 | dev_dbg(dev, "SerDes: termination tx is 0x%x\n", tx_term_np); | 1781 | dev_dbg(dev, "SerDes: termination tx is 0x%x\n", tx_term_np); |
913 | 1782 | ||
1783 | /* Set regulator output voltage and Rx boost/att start values */ | ||
1784 | for_each_lanes(lanes, lane) { | ||
1785 | dev_dbg(dev, | ||
1786 | "SerDes: Tx vdreg = %d, Rx att start = %d, Rx boost start = %d for lane %d\n", | ||
1787 | serdes->config->tx[lane].vdreg, | ||
1788 | serdes->config->rx[lane].start_att, | ||
1789 | serdes->config->rx[lane].start_boost, | ||
1790 | lane); | ||
1791 | |||
1792 | k2_rio_serdes_tx_rx_set_equalizer( | ||
1793 | lane, | ||
1794 | regs, | ||
1795 | serdes->config->tx[lane].vdreg, | ||
1796 | serdes->config->rx[lane].start_att, | ||
1797 | serdes->config->rx[lane].start_boost); | ||
1798 | } | ||
1799 | |||
914 | for_each_lanes(lanes, lane) { | 1800 | for_each_lanes(lanes, lane) { |
1801 | /* Serdes assert reset */ | ||
1802 | k2_rio_serdes_sb_assert_full_reset(lane, regs); | ||
1803 | |||
1804 | /* Set the Tx coefficients */ | ||
1805 | k2_rio_serdes_config_set_tx_coeffs(lane, regs, | ||
1806 | &(serdes->config->tx[lane])); | ||
1807 | |||
1808 | /* Force signal detect low, reset CDR, attenuation and boost */ | ||
1809 | k2_rio_serdes_reset_cdr_att_boost(lane, regs); | ||
1810 | |||
1811 | /* Serdes deassert reset */ | ||
1812 | k2_rio_serdes_sb_deassert_reset(lane, regs, 1); | ||
1813 | |||
915 | /* Set the saved Tx termination */ | 1814 | /* Set the saved Tx termination */ |
916 | k2_rio_serdes_termination_config(regs, lane, tx_term_np); | 1815 | k2_rio_serdes_termination_config(lane, regs, tx_term_np); |
1816 | } | ||
917 | 1817 | ||
918 | /* Disable SerDes for this lane */ | 1818 | /* Wait lanes OK */ |
919 | k2_rio_serdes_lane_disable(lane, regs); | 1819 | k2_rio_serdes_wait_lanes_ok(lanes, regs); |
1820 | |||
1821 | /* Eventually perform the DFE offset calibration */ | ||
1822 | if (serdes->config->do_dfe_cal) { | ||
1823 | dev_dbg(dev, "SerDes: lanes OK, start offset calibration\n"); | ||
1824 | |||
1825 | k2_rio_serdes_dfe_offset_calibration(lanes, regs, dev, | ||
1826 | serdes->config->tx); | ||
920 | } | 1827 | } |
921 | 1828 | ||
922 | return 0; | 1829 | /* Allow SerDes to re-acquire Signal Detect */ |
1830 | for_each_lanes(lanes, lane) | ||
1831 | k2_rio_serdes_reacquire_sd(lane, regs); | ||
1832 | |||
1833 | /* Wait at least 10 usecs */ | ||
1834 | usleep_range(10, 50); | ||
1835 | |||
1836 | /* Apply Rx coefficients if any */ | ||
1837 | k2_rio_serdes_config_set_rx_coeffs(lanes, serdes->regs, serdes->dev, | ||
1838 | serdes->config->rx); | ||
1839 | |||
1840 | /* Check lane OK */ | ||
1841 | k2_rio_serdes_wait_lanes_ok(lanes, regs); | ||
1842 | |||
1843 | /* Disable lanes */ | ||
1844 | for_each_lanes(lanes, lane) | ||
1845 | k2_rio_serdes_lane_disable(lane, regs); | ||
1846 | |||
1847 | return res; | ||
923 | } | 1848 | } |
924 | 1849 | ||
925 | static int k2_rio_serdes_shutdown_lanes(u32 lanes, void __iomem *regs) | 1850 | static int k2_rio_serdes_shutdown_lanes(u32 lanes, |
1851 | struct keystone_serdes_data *serdes) | ||
926 | { | 1852 | { |
1853 | void __iomem *regs = serdes->regs; | ||
927 | u32 lane; | 1854 | u32 lane; |
928 | 1855 | ||
1856 | dev_dbg(serdes->dev, "shutdown lanes 0x%x\n", lanes); | ||
1857 | |||
929 | /* Disable lanes */ | 1858 | /* Disable lanes */ |
930 | for_each_lanes(lanes, lane) { | 1859 | for_each_lanes(lanes, lane) { |
931 | k2_rio_serdes_lane_disable(lane, regs); | 1860 | k2_rio_serdes_lane_disable(lane, regs); |
1861 | k2_rio_serdes_sb_set_overlay_bit29(lane, regs); | ||
932 | } | 1862 | } |
933 | 1863 | ||
934 | /* Disable PLL */ | 1864 | /* Disable CMU TX PLL */ |
935 | __raw_writel(0x80000000, regs + 0x1ff4); | 1865 | reg_finsr(regs + 0x1fc0 + 0x34, 30, 29, 0x0); |
936 | 1866 | ||
937 | /* Reset CMU PLL for all lanes */ | 1867 | /* Reset CMU PLL for all lanes */ |
938 | reg_rmw(regs + 0x10, BIT(28), BIT(28)); | 1868 | reg_finsr(regs + 0x10, 28, 28, 0x1); |
939 | 1869 | ||
940 | return 0; | 1870 | return 0; |
941 | } | 1871 | } |
942 | 1872 | ||
943 | static void k2_rio_serdes_fix_unstable_single_lane(int lane, | 1873 | static void __k2_rio_serdes_fix_unstable_lane( |
944 | struct device *dev, | 1874 | int lane, |
945 | void __iomem *regs) | 1875 | void __iomem *regs, |
1876 | struct device *dev, | ||
1877 | struct keystone_serdes_config *serdes_config) | ||
946 | { | 1878 | { |
1879 | int res; | ||
1880 | struct keystone_serdes_lane_rx_config rx_coeff; | ||
1881 | |||
947 | dev_dbg(dev, "SerDes: fix unstable lane %d\n", lane); | 1882 | dev_dbg(dev, "SerDes: fix unstable lane %d\n", lane); |
948 | 1883 | ||
949 | /* Display serdes boost/att */ | 1884 | /* Get serdes current Rx boost/att */ |
950 | k2_rio_serdes_display_att_boost(regs, lane, dev); | 1885 | k2_rio_serdes_get_att_boost(lane, regs, &rx_coeff); |
1886 | |||
1887 | /* Display Rx att/boost values */ | ||
1888 | dev_dbg(dev, | ||
1889 | "SerDes: current Rx att = %d, boost = %d for lane %d\n", | ||
1890 | rx_coeff.att, rx_coeff.boost, lane); | ||
951 | 1891 | ||
952 | /* Force SerDes signal detect LO (reset CDR, Att and Boost) */ | 1892 | /* Force signal detect low, reset CDR, attenuation and boost */ |
953 | reg_fill_field(regs + (lane * 0x200) + 0x200 + 0x04, 1, 2, 2); | 1893 | k2_rio_serdes_reset_cdr_att_boost(lane, regs); |
954 | 1894 | ||
955 | usleep_range(10, 50); | 1895 | usleep_range(10, 50); |
956 | 1896 | ||
957 | /* Allow SerDes to re-acquire signal detect */ | 1897 | /* Allow SerDes to re-acquire signal detect */ |
958 | k2_rio_serdes_reacquire_sd(regs, lane); | 1898 | k2_rio_serdes_reacquire_sd(lane, regs); |
959 | 1899 | ||
960 | dev_dbg(dev, "SerDes: lane %d Rx path reset done\n", lane); | 1900 | dev_dbg(dev, "SerDes: lane %d Rx path reset done\n", lane); |
961 | 1901 | ||
962 | /* Force att/boost calibration */ | 1902 | /* Force boost calibration */ |
963 | k2_rio_serdes_force_att_boost(regs, lane); | 1903 | res = k2_rio_serdes_force_boost_calibration(lane, regs); |
1904 | if (res) { | ||
1905 | dev_warn(dev, | ||
1906 | "SerDes: lane %d boost calibration workaround failed\n", | ||
1907 | lane); | ||
1908 | return; | ||
1909 | } | ||
964 | 1910 | ||
965 | dev_dbg(dev, "SerDes: lane %d boost/att forcing done\n", lane); | 1911 | dev_dbg(dev, "SerDes: lane %d boost/att forcing done\n", lane); |
966 | 1912 | ||
967 | /* Display serdes boost/att */ | 1913 | /* Get serdes current Rx boost/att */ |
968 | k2_rio_serdes_display_att_boost(regs, lane, dev); | 1914 | k2_rio_serdes_get_att_boost(lane, regs, &rx_coeff); |
1915 | |||
1916 | /* Display Rx att/boost values */ | ||
1917 | dev_dbg(dev, | ||
1918 | "SerDes: current Rx att = %d, boost = %d for lane %d\n", | ||
1919 | rx_coeff.att, rx_coeff.boost, lane); | ||
969 | 1920 | ||
970 | dev_dbg(dev, "SerDes: lane %d fixed\n", lane); | 1921 | dev_dbg(dev, "SerDes: lane %d fixed\n", lane); |
971 | } | 1922 | } |
972 | 1923 | ||
973 | static void k2_rio_serdes_fix_unstable_lanes(u32 lanes, | 1924 | static void k2_rio_serdes_fix_unstable_lanes( |
974 | struct device *dev, | 1925 | u32 lanes, |
975 | void __iomem *regs) | 1926 | struct keystone_serdes_data *serdes) |
976 | { | 1927 | { |
1928 | struct device *dev = serdes->dev; | ||
1929 | void __iomem *regs = serdes->regs; | ||
977 | unsigned int stat; | 1930 | unsigned int stat; |
978 | unsigned int i_dlpf; | 1931 | unsigned int i_dlpf; |
979 | u32 lane; | 1932 | u32 lane; |
980 | 1933 | ||
981 | for_each_lanes(lanes, lane) { | 1934 | for_each_lanes(lanes, lane) { |
982 | /* Check rx valid */ | 1935 | /* Check Rx valid */ |
983 | stat = (k2_rio_serdes_sb_read_selected_tbus(regs, | 1936 | stat = (k2_rio_serdes_sb_read_selected_tbus(regs, |
984 | lane + 1, | 1937 | lane + 1, |
985 | 0x2) & 0x0060) >> 5; | 1938 | 0x2) & 0x0060) >> 5; |
@@ -992,18 +1945,18 @@ static void k2_rio_serdes_fix_unstable_lanes(u32 lanes, | |||
992 | regs, lane + 1, 5) >> 10; | 1945 | regs, lane + 1, 5) >> 10; |
993 | 1946 | ||
994 | if ((i_dlpf == 0) || (i_dlpf == 3)) | 1947 | if ((i_dlpf == 0) || (i_dlpf == 3)) |
995 | k2_rio_serdes_fix_unstable_single_lane( | 1948 | __k2_rio_serdes_fix_unstable_lane( |
996 | lane, dev, regs); | 1949 | lane, regs, dev, serdes->config); |
997 | } | 1950 | } |
998 | } | 1951 | } |
999 | } | 1952 | } |
1000 | 1953 | ||
1001 | static int k2_rio_serdes_start_tx_lanes( | 1954 | static int k2_rio_serdes_start_tx_lanes( |
1002 | u32 lanes, | 1955 | u32 lanes, |
1003 | struct device *dev, | 1956 | struct keystone_serdes_data *serdes) |
1004 | void __iomem *regs, | ||
1005 | struct keystone_serdes_config *serdes_config) | ||
1006 | { | 1957 | { |
1958 | struct device *dev = serdes->dev; | ||
1959 | void __iomem *regs = serdes->regs; | ||
1007 | u32 lane; | 1960 | u32 lane; |
1008 | int res; | 1961 | int res; |
1009 | 1962 | ||
@@ -1011,46 +1964,45 @@ static int k2_rio_serdes_start_tx_lanes( | |||
1011 | dev_dbg(dev, "SerDes: start transmit for lane %d\n", lane); | 1964 | dev_dbg(dev, "SerDes: start transmit for lane %d\n", lane); |
1012 | 1965 | ||
1013 | /* Serdes assert reset */ | 1966 | /* Serdes assert reset */ |
1014 | k2_rio_serdes_sb_assert_reset(regs, lane); | 1967 | k2_rio_serdes_sb_assert_reset(lane, regs); |
1015 | 1968 | ||
1016 | /* Set tx coefficients */ | 1969 | /* Set the Tx coefficients */ |
1017 | k2_rio_serdes_config_set_tx_coeffs( | 1970 | k2_rio_serdes_config_set_tx_coeffs(lane, regs, |
1018 | lane, regs, &(serdes_config->lane[lane])); | 1971 | &(serdes->config->tx[lane])); |
1019 | 1972 | ||
1020 | dev_dbg(dev, | 1973 | dev_dbg(dev, |
1021 | "SerDes: lane %d: c1 = %d, c2 = %d, cm = %d, att = %d, 1lsb = %d, vreg = %d\n", | 1974 | "SerDes: lane %d: c1 = %d, c2 = %d, cm = %d, att = %d, 1lsb = %d, vreg = %d\n", |
1022 | lane, | 1975 | lane, |
1023 | serdes_config->lane[lane].c1_coeff, | 1976 | serdes->config->tx[lane].c1_coeff, |
1024 | serdes_config->lane[lane].c2_coeff, | 1977 | serdes->config->tx[lane].c2_coeff, |
1025 | serdes_config->lane[lane].cm_coeff, | 1978 | serdes->config->tx[lane].cm_coeff, |
1026 | serdes_config->lane[lane].att, | 1979 | serdes->config->tx[lane].att, |
1027 | serdes_config->lane[lane].pre_1lsb, | 1980 | serdes->config->tx[lane].pre_1lsb, |
1028 | serdes_config->lane[lane].vreg); | 1981 | serdes->config->tx[lane].vreg); |
1029 | 1982 | ||
1030 | /* Force Tx normal to enable the transmitter */ | 1983 | /* Force Tx normal to enable the transmitter */ |
1031 | k2_rio_serdes_force_tx_normal(regs, lane); | 1984 | k2_rio_serdes_force_tx_normal(lane, regs); |
1032 | 1985 | ||
1033 | /* Serdes de-assert reset */ | 1986 | /* Serdes de-assert reset */ |
1034 | k2_rio_serdes_sb_deassert_reset(regs, 0, lane); | 1987 | k2_rio_serdes_sb_deassert_reset(lane, regs, 0); |
1035 | 1988 | ||
1036 | /* Enable corresponding lane */ | 1989 | /* Enable corresponding lane */ |
1037 | k2_rio_serdes_lane_enable(lane, regs); | 1990 | k2_rio_serdes_lane_enable(lane, regs); |
1038 | } | 1991 | } |
1039 | 1992 | ||
1040 | /* Clear overlay bit to bring lane out of reset */ | 1993 | /* Clear overlay bit to bring lanes out of reset */ |
1041 | for_each_lanes(lanes, lane) { | 1994 | for_each_lanes(lanes, lane) |
1042 | k2_rio_serdes_sb_clear_overlay_bit29(regs, lane); | 1995 | k2_rio_serdes_sb_clear_overlay_bit29(lane, regs); |
1043 | } | ||
1044 | 1996 | ||
1045 | /* Wait lanes OK */ | 1997 | /* Wait lanes OK */ |
1046 | res = k2_rio_serdes_wait_lanes_ok(lanes, regs); | 1998 | res = k2_rio_serdes_wait_lanes_ok(lanes, regs); |
1047 | if (res < 0) { | 1999 | if (res < 0) { |
1048 | dev_dbg(dev, "SerDes: %s() lane mask 0x%x not OK\n", | 2000 | dev_dbg(dev, "SerDes: %s() lane mask 0x%x not OK\n", |
1049 | __func__, lanes); | 2001 | __func__, lanes); |
1050 | return -1; | 2002 | return res; |
1051 | } | 2003 | } |
1052 | 2004 | ||
1053 | return 0; | 2005 | return res; |
1054 | } | 2006 | } |
1055 | 2007 | ||
1056 | static const struct keystone_serdes_ops k2_serdes_ops = { | 2008 | static const struct keystone_serdes_ops k2_serdes_ops = { |
@@ -1059,28 +2011,390 @@ static const struct keystone_serdes_ops k2_serdes_ops = { | |||
1059 | .wait_lanes_ok = k2_rio_serdes_wait_lanes_sd, | 2011 | .wait_lanes_ok = k2_rio_serdes_wait_lanes_sd, |
1060 | .shutdown_lanes = k2_rio_serdes_shutdown_lanes, | 2012 | .shutdown_lanes = k2_rio_serdes_shutdown_lanes, |
1061 | .fix_unstable_lanes = k2_rio_serdes_fix_unstable_lanes, | 2013 | .fix_unstable_lanes = k2_rio_serdes_fix_unstable_lanes, |
2014 | .calibrate_lanes = k2_rio_serdes_calibrate_lanes, | ||
1062 | }; | 2015 | }; |
1063 | 2016 | ||
1064 | /*---------------------------------------------------------------------------*/ | 2017 | /*---------------------------------------------------------------------------*/ |
1065 | 2018 | ||
2019 | /* Sysfs management */ | ||
2020 | struct serdes_attribute { | ||
2021 | struct attribute attr; | ||
2022 | ssize_t (*show)(struct kobject *kobj, | ||
2023 | struct serdes_attribute *attr, | ||
2024 | char *buf); | ||
2025 | ssize_t (*store)(struct kobject *kobj, | ||
2026 | struct serdes_attribute *attr, | ||
2027 | const char *, | ||
2028 | size_t); | ||
2029 | struct keystone_serdes_data *serdes; | ||
2030 | void *context; | ||
2031 | }; | ||
2032 | |||
2033 | #define __SERDES_ATTR(_name, _mode, _show, _store, _ctxt) \ | ||
2034 | { \ | ||
2035 | .attr = { \ | ||
2036 | .name = __stringify(_name), \ | ||
2037 | .mode = _mode }, \ | ||
2038 | .show = _show, \ | ||
2039 | .store = _store, \ | ||
2040 | .context = (_ctxt), \ | ||
2041 | } | ||
2042 | |||
2043 | #define to_serdes_attr(_attr) container_of(_attr, struct serdes_attribute, attr) | ||
2044 | |||
2045 | static ssize_t serdes_tx_attr_show(struct kobject *kobj, | ||
2046 | struct serdes_attribute *attr, | ||
2047 | char *buf) | ||
2048 | { | ||
2049 | struct keystone_serdes_data *serdes = | ||
2050 | (struct keystone_serdes_data *) attr->context; | ||
2051 | struct keystone_serdes_config *serdes_config = serdes->config; | ||
2052 | u32 lane; | ||
2053 | int len = 0; | ||
2054 | |||
2055 | for (lane = 0; lane < KEYSTONE_SERDES_MAX_LANES; lane++) { | ||
2056 | u32 val = -1; | ||
2057 | |||
2058 | if (strcmp("c1", attr->attr.name) == 0) | ||
2059 | val = serdes_config->tx[lane].c1_coeff; | ||
2060 | if (strcmp("c2", attr->attr.name) == 0) | ||
2061 | val = serdes_config->tx[lane].c2_coeff; | ||
2062 | if (strcmp("cm", attr->attr.name) == 0) | ||
2063 | val = serdes_config->tx[lane].cm_coeff; | ||
2064 | if (strcmp("pre_1lsb", attr->attr.name) == 0) | ||
2065 | val = serdes_config->tx[lane].pre_1lsb; | ||
2066 | if (strcmp("att", attr->attr.name) == 0) | ||
2067 | val = serdes_config->tx[lane].att; | ||
2068 | if (strcmp("vreg", attr->attr.name) == 0) | ||
2069 | val = serdes_config->tx[lane].vreg; | ||
2070 | |||
2071 | if (lane == 0) | ||
2072 | len = snprintf(buf + len, PAGE_SIZE, "%d", val); | ||
2073 | else | ||
2074 | len += snprintf(buf + len, PAGE_SIZE, " %d", val); | ||
2075 | } | ||
2076 | |||
2077 | len += snprintf(buf + len, PAGE_SIZE, "\n"); | ||
2078 | |||
2079 | return len; | ||
2080 | } | ||
2081 | |||
2082 | static ssize_t serdes_tx_attr_store(struct kobject *kobj, | ||
2083 | struct serdes_attribute *attr, | ||
2084 | const char *buf, | ||
2085 | size_t size) | ||
2086 | { | ||
2087 | struct keystone_serdes_data *serdes = | ||
2088 | (struct keystone_serdes_data *) attr->context; | ||
2089 | struct keystone_serdes_config *serdes_config = serdes->config; | ||
2090 | u32 lane; | ||
2091 | u32 val[4]; | ||
2092 | |||
2093 | if (sscanf(buf, "%d %d %d %d", &val[0], &val[1], &val[2], &val[3]) < 4) | ||
2094 | return -EINVAL; | ||
2095 | |||
2096 | for (lane = 0; lane < KEYSTONE_SERDES_MAX_LANES; lane++) { | ||
2097 | |||
2098 | /* Update Tx coefficients */ | ||
2099 | if (strcmp("c1", attr->attr.name) == 0) | ||
2100 | serdes_config->tx[lane].c1_coeff = val[lane]; | ||
2101 | if (strcmp("c2", attr->attr.name) == 0) | ||
2102 | serdes_config->tx[lane].c2_coeff = val[lane]; | ||
2103 | if (strcmp("cm", attr->attr.name) == 0) | ||
2104 | serdes_config->tx[lane].cm_coeff = val[lane]; | ||
2105 | if (strcmp("pre_1lsb", attr->attr.name) == 0) | ||
2106 | serdes_config->tx[lane].pre_1lsb = val[lane]; | ||
2107 | if (strcmp("att", attr->attr.name) == 0) | ||
2108 | serdes_config->tx[lane].att = val[lane]; | ||
2109 | if (strcmp("vreg", attr->attr.name) == 0) | ||
2110 | serdes_config->tx[lane].vreg = val[lane]; | ||
2111 | |||
2112 | /* Serdes assert reset */ | ||
2113 | k2_rio_serdes_sb_assert_full_reset(lane, serdes->regs); | ||
2114 | |||
2115 | /* Apply the Tx coefficients */ | ||
2116 | k2_rio_serdes_config_set_tx_coeffs(lane, | ||
2117 | serdes->regs, | ||
2118 | &(serdes_config->tx[lane])); | ||
2119 | |||
2120 | /* Serdes de-assert reset */ | ||
2121 | k2_rio_serdes_sb_deassert_reset(lane, serdes->regs, 1); | ||
2122 | } | ||
2123 | |||
2124 | return size; | ||
2125 | } | ||
2126 | |||
2127 | static ssize_t serdes_rx_attr_show(struct kobject *kobj, | ||
2128 | struct serdes_attribute *attr, | ||
2129 | char *buf) | ||
2130 | { | ||
2131 | struct keystone_serdes_lane_rx_config rx_coeff; | ||
2132 | struct keystone_serdes_data *serdes = | ||
2133 | (struct keystone_serdes_data *) attr->context; | ||
2134 | u32 lane; | ||
2135 | int len = 0; | ||
2136 | |||
2137 | memset(&rx_coeff, -1, sizeof(rx_coeff)); | ||
2138 | |||
2139 | for (lane = 0; lane < KEYSTONE_SERDES_MAX_LANES; lane++) { | ||
2140 | u32 val; | ||
2141 | |||
2142 | /* Get current Rx att/boost values */ | ||
2143 | k2_rio_serdes_get_att_boost(lane, serdes->regs, &rx_coeff); | ||
2144 | |||
2145 | /* If lanes are not started yet use the calibrated values */ | ||
2146 | if (rx_coeff.att == 0) | ||
2147 | rx_coeff.att = serdes->config->rx[lane].mean_att; | ||
2148 | |||
2149 | if (rx_coeff.boost == 0) | ||
2150 | rx_coeff.boost = serdes->config->rx[lane].mean_boost; | ||
2151 | |||
2152 | /* If coefficient is not set, set it as zero (lane disabled) */ | ||
2153 | if (rx_coeff.att == -1) | ||
2154 | rx_coeff.att = 0; | ||
2155 | |||
2156 | if (rx_coeff.boost == -1) | ||
2157 | rx_coeff.boost = 0; | ||
2158 | |||
2159 | if (strcmp("att", attr->attr.name) == 0) | ||
2160 | val = rx_coeff.att; | ||
2161 | else | ||
2162 | val = rx_coeff.boost; | ||
2163 | |||
2164 | if (lane == 0) | ||
2165 | len = snprintf(buf + len, PAGE_SIZE, "%d", val); | ||
2166 | else | ||
2167 | len += snprintf(buf + len, PAGE_SIZE, " %d", val); | ||
2168 | } | ||
2169 | |||
2170 | len += snprintf(buf + len, PAGE_SIZE, "\n"); | ||
2171 | |||
2172 | return len; | ||
2173 | } | ||
2174 | |||
2175 | static ssize_t serdes_rx_attr_store(struct kobject *kobj, | ||
2176 | struct serdes_attribute *attr, | ||
2177 | const char *buf, | ||
2178 | size_t size) | ||
2179 | { | ||
2180 | struct keystone_serdes_data *serdes = | ||
2181 | (struct keystone_serdes_data *) attr->context; | ||
2182 | struct keystone_serdes_config *serdes_config = serdes->config; | ||
2183 | u32 lane; | ||
2184 | u32 lanes = 0; | ||
2185 | u32 val[4]; | ||
2186 | |||
2187 | if (sscanf(buf, "%d %d %d %d", &val[0], &val[1], &val[2], &val[3]) < 4) | ||
2188 | return -EINVAL; | ||
2189 | |||
2190 | for (lane = 0; lane < KEYSTONE_SERDES_MAX_LANES; lane++) { | ||
2191 | /* Set att or boost coefficients */ | ||
2192 | if (strcmp("att", attr->attr.name) == 0) | ||
2193 | serdes_config->rx[lane].mean_att = val[lane]; | ||
2194 | else | ||
2195 | serdes_config->rx[lane].mean_boost = val[lane]; | ||
2196 | |||
2197 | lanes |= BIT(lane); | ||
2198 | } | ||
2199 | |||
2200 | return size; | ||
2201 | } | ||
2202 | |||
2203 | static ssize_t serdes_n_attr_show(struct kobject *kobj, | ||
2204 | struct attribute *attr, | ||
2205 | char *buf) | ||
2206 | { | ||
2207 | struct serdes_attribute *attribute = to_serdes_attr(attr); | ||
2208 | |||
2209 | if (!attribute->show) | ||
2210 | return -EIO; | ||
2211 | |||
2212 | return attribute->show(kobj, attribute, buf); | ||
2213 | } | ||
2214 | |||
2215 | static ssize_t serdes_n_attr_store(struct kobject *kobj, | ||
2216 | struct attribute *attr, | ||
2217 | const char *buf, | ||
2218 | size_t count) | ||
2219 | { | ||
2220 | struct serdes_attribute *attribute = to_serdes_attr(attr); | ||
2221 | |||
2222 | if (!attribute->store) | ||
2223 | return -EIO; | ||
2224 | |||
2225 | return attribute->store(kobj, attribute, buf, count); | ||
2226 | } | ||
2227 | |||
2228 | static const struct sysfs_ops serdes_sysfs_ops = { | ||
2229 | .show = serdes_n_attr_show, | ||
2230 | .store = serdes_n_attr_store, | ||
2231 | }; | ||
2232 | |||
2233 | static struct serdes_attribute serdes_rx_att_attribute = | ||
2234 | __SERDES_ATTR(att, S_IRUGO | S_IWUSR, | ||
2235 | serdes_rx_attr_show, | ||
2236 | serdes_rx_attr_store, | ||
2237 | NULL); | ||
2238 | |||
2239 | static struct serdes_attribute serdes_rx_boost_attribute = | ||
2240 | __SERDES_ATTR(boost, S_IRUGO | S_IWUSR, | ||
2241 | serdes_rx_attr_show, | ||
2242 | serdes_rx_attr_store, | ||
2243 | NULL); | ||
2244 | |||
2245 | static struct serdes_attribute serdes_tx_cm_attribute = | ||
2246 | __SERDES_ATTR(cm, S_IRUGO | S_IWUSR, | ||
2247 | serdes_tx_attr_show, | ||
2248 | serdes_tx_attr_store, | ||
2249 | NULL); | ||
2250 | |||
2251 | static struct serdes_attribute serdes_tx_c1_attribute = | ||
2252 | __SERDES_ATTR(c1, S_IRUGO | S_IWUSR, | ||
2253 | serdes_tx_attr_show, | ||
2254 | serdes_tx_attr_store, | ||
2255 | NULL); | ||
2256 | |||
2257 | static struct serdes_attribute serdes_tx_c2_attribute = | ||
2258 | __SERDES_ATTR(c2, S_IRUGO | S_IWUSR, | ||
2259 | serdes_tx_attr_show, | ||
2260 | serdes_tx_attr_store, | ||
2261 | NULL); | ||
2262 | |||
2263 | static struct serdes_attribute serdes_tx_att_attribute = | ||
2264 | __SERDES_ATTR(att, S_IRUGO | S_IWUSR, | ||
2265 | serdes_tx_attr_show, | ||
2266 | serdes_tx_attr_store, | ||
2267 | NULL); | ||
2268 | |||
2269 | static struct serdes_attribute serdes_tx_lsb_attribute = | ||
2270 | __SERDES_ATTR(pre_1lsb, S_IRUGO | S_IWUSR, | ||
2271 | serdes_tx_attr_show, | ||
2272 | serdes_tx_attr_store, | ||
2273 | NULL); | ||
2274 | |||
2275 | static struct serdes_attribute serdes_tx_vreg_attribute = | ||
2276 | __SERDES_ATTR(vreg, S_IRUGO | S_IWUSR, | ||
2277 | serdes_tx_attr_show, | ||
2278 | serdes_tx_attr_store, | ||
2279 | NULL); | ||
2280 | |||
2281 | static struct attribute *serdes_rx_attrs[] = { | ||
2282 | &serdes_rx_att_attribute.attr, | ||
2283 | &serdes_rx_boost_attribute.attr, | ||
2284 | NULL | ||
2285 | }; | ||
2286 | |||
2287 | static struct attribute *serdes_tx_attrs[] = { | ||
2288 | &serdes_tx_cm_attribute.attr, | ||
2289 | &serdes_tx_c1_attribute.attr, | ||
2290 | &serdes_tx_c2_attribute.attr, | ||
2291 | &serdes_tx_att_attribute.attr, | ||
2292 | &serdes_tx_lsb_attribute.attr, | ||
2293 | &serdes_tx_vreg_attribute.attr, | ||
2294 | NULL | ||
2295 | }; | ||
2296 | |||
2297 | static struct kobj_type serdes_rx_type = { | ||
2298 | .sysfs_ops = &serdes_sysfs_ops, | ||
2299 | .default_attrs = serdes_rx_attrs, | ||
2300 | }; | ||
2301 | |||
2302 | static struct kobj_type serdes_tx_type = { | ||
2303 | .sysfs_ops = &serdes_sysfs_ops, | ||
2304 | .default_attrs = serdes_tx_attrs, | ||
2305 | }; | ||
2306 | |||
2307 | static int keystone_rio_serdes_sysfs_create( | ||
2308 | struct keystone_serdes_data *serdes, | ||
2309 | struct keystone_serdes_config *serdes_config) | ||
2310 | { | ||
2311 | struct device *dev = serdes->dev; | ||
2312 | int res; | ||
2313 | |||
2314 | serdes->serdes_kobj = kobject_create_and_add( | ||
2315 | "serdes", | ||
2316 | kobject_get(&dev->kobj)); | ||
2317 | |||
2318 | if (!serdes->serdes_kobj) { | ||
2319 | dev_err(dev, "unable create sysfs serdes file\n"); | ||
2320 | kobject_put(&dev->kobj); | ||
2321 | return -ENOMEM; | ||
2322 | } | ||
2323 | |||
2324 | /* Rx entries */ | ||
2325 | serdes_rx_att_attribute.context = (void *) serdes; | ||
2326 | serdes_rx_boost_attribute.context = (void *) serdes; | ||
2327 | |||
2328 | res = kobject_init_and_add(&serdes->serdes_rx_kobj, | ||
2329 | &serdes_rx_type, | ||
2330 | kobject_get(serdes->serdes_kobj), | ||
2331 | "rx"); | ||
2332 | if (res) { | ||
2333 | dev_err(dev, "unable create sysfs serdes/rx files\n"); | ||
2334 | kobject_put(&dev->kobj); | ||
2335 | kobject_put(serdes->serdes_kobj); | ||
2336 | return res; | ||
2337 | } | ||
2338 | |||
2339 | /* Tx entries */ | ||
2340 | serdes_tx_cm_attribute.context = (void *) serdes; | ||
2341 | serdes_tx_c1_attribute.context = (void *) serdes; | ||
2342 | serdes_tx_c2_attribute.context = (void *) serdes; | ||
2343 | serdes_tx_att_attribute.context = (void *) serdes; | ||
2344 | serdes_tx_lsb_attribute.context = (void *) serdes; | ||
2345 | serdes_tx_vreg_attribute.context = (void *) serdes; | ||
2346 | |||
2347 | res = kobject_init_and_add(&serdes->serdes_tx_kobj, | ||
2348 | &serdes_tx_type, | ||
2349 | kobject_get(serdes->serdes_kobj), | ||
2350 | "tx"); | ||
2351 | if (res) { | ||
2352 | dev_err(dev, "unable create sysfs serdes/tx files\n"); | ||
2353 | kobject_put(&dev->kobj); | ||
2354 | kobject_put(serdes->serdes_kobj); | ||
2355 | return res; | ||
2356 | } | ||
2357 | |||
2358 | return 0; | ||
2359 | } | ||
2360 | |||
2361 | /*---------------------------------------------------------------------------*/ | ||
2362 | |||
1066 | int keystone_rio_serdes_register(u16 serdes_type, | 2363 | int keystone_rio_serdes_register(u16 serdes_type, |
1067 | const struct keystone_serdes_ops **p_ops) | 2364 | void __iomem *regs, |
2365 | void __iomem *sts_reg, | ||
2366 | struct device *dev, | ||
2367 | struct keystone_serdes_data *serdes, | ||
2368 | struct keystone_serdes_config *serdes_config) | ||
1068 | { | 2369 | { |
1069 | int res = 0; | 2370 | int res = 0; |
1070 | 2371 | ||
1071 | if (p_ops == NULL) | 2372 | memset(serdes, 0, sizeof(*serdes)); |
2373 | |||
2374 | if (serdes == NULL) | ||
1072 | return -EINVAL; | 2375 | return -EINVAL; |
1073 | 2376 | ||
1074 | switch (serdes_type) { | 2377 | switch (serdes_type) { |
1075 | case KEYSTONE_SERDES_TYPE_K1: | 2378 | case KEYSTONE_SERDES_TYPE_K1: |
1076 | *p_ops = &k1_serdes_ops; | 2379 | serdes->ops = &k1_serdes_ops; |
1077 | break; | 2380 | break; |
1078 | case KEYSTONE_SERDES_TYPE_K2: | 2381 | case KEYSTONE_SERDES_TYPE_K2: |
1079 | *p_ops = &k2_serdes_ops; | 2382 | serdes->ops = &k2_serdes_ops; |
1080 | break; | 2383 | break; |
1081 | default: | 2384 | default: |
1082 | res = -EINVAL; | 2385 | res = -EINVAL; |
1083 | } | 2386 | } |
1084 | 2387 | ||
2388 | if (res) | ||
2389 | goto error; | ||
2390 | |||
2391 | serdes->dev = dev; | ||
2392 | serdes->config = serdes_config; | ||
2393 | serdes->regs = regs; | ||
2394 | serdes->sts_reg = sts_reg; | ||
2395 | |||
2396 | res = keystone_rio_serdes_sysfs_create(serdes, serdes_config); | ||
2397 | |||
2398 | error: | ||
1085 | return res; | 2399 | return res; |
1086 | } | 2400 | } |
diff --git a/drivers/rapidio/devices/keystone_rio_serdes.h b/drivers/rapidio/devices/keystone_rio_serdes.h index 5327a68a614..713a3de21de 100644 --- a/drivers/rapidio/devices/keystone_rio_serdes.h +++ b/drivers/rapidio/devices/keystone_rio_serdes.h | |||
@@ -30,9 +30,9 @@ | |||
30 | #define KEYSTONE_SERDES_BAUD_5_000 3 | 30 | #define KEYSTONE_SERDES_BAUD_5_000 3 |
31 | #define KEYSTONE_SERDES_BAUD_6_250 4 | 31 | #define KEYSTONE_SERDES_BAUD_6_250 4 |
32 | 32 | ||
33 | #define KEYSTONE_SERDES_FULL_RATE 0 | 33 | #define KEYSTONE_SERDES_QUARTER_RATE 0 |
34 | #define KEYSTONE_SERDES_HALF_RATE 1 | 34 | #define KEYSTONE_SERDES_HALF_RATE 1 |
35 | #define KEYSTONE_SERDES_QUARTER_RATE 2 | 35 | #define KEYSTONE_SERDES_FULL_RATE 2 |
36 | 36 | ||
37 | /* | 37 | /* |
38 | * SerDes PHY transmistter configuration | 38 | * SerDes PHY transmistter configuration |
@@ -44,40 +44,80 @@ struct keystone_serdes_lane_tx_config { | |||
44 | u32 cm_coeff; /* CM coefficient */ | 44 | u32 cm_coeff; /* CM coefficient */ |
45 | u32 att; /* attenuator */ | 45 | u32 att; /* attenuator */ |
46 | u32 vreg; /* regulator voltage */ | 46 | u32 vreg; /* regulator voltage */ |
47 | u32 vdreg; /* output swing voltage regulator */ | ||
48 | }; | ||
49 | |||
50 | struct keystone_serdes_lane_rx_config { | ||
51 | u32 att; /* current attenuator */ | ||
52 | u32 boost; /* current boost */ | ||
53 | u32 mean_att; /* mean request attenuator start coeff */ | ||
54 | u32 mean_boost; /* mean request boost start coeff */ | ||
55 | u32 start_att; /* attenuator start value */ | ||
56 | u32 start_boost; /* boost start value */ | ||
47 | }; | 57 | }; |
48 | 58 | ||
49 | struct keystone_serdes_config { | 59 | struct keystone_serdes_config { |
50 | u32 cfg_cntl; /* setting control reg cfg */ | ||
51 | u16 serdes_cfg_pll; /* SerDes PLL cfg */ | ||
52 | u16 prescalar_srv_clk; /* prescalar fo ip_clk */ | 60 | u16 prescalar_srv_clk; /* prescalar fo ip_clk */ |
53 | 61 | ||
54 | /* Per-lane PHY Tx coefficients */ | 62 | /* Per-lane PHY Tx and Rx coefficients */ |
55 | struct keystone_serdes_lane_tx_config lane[KEYSTONE_SERDES_MAX_LANES]; | 63 | struct keystone_serdes_lane_tx_config tx[KEYSTONE_SERDES_MAX_LANES]; |
64 | struct keystone_serdes_lane_rx_config rx[KEYSTONE_SERDES_MAX_LANES]; | ||
65 | |||
66 | u32 cal_timeout; /* calibration timeout */ | ||
67 | int do_dfe_cal; /* if 1, perform DFE offset calibration */ | ||
68 | u32 rate; /* Configurated rate */ | ||
56 | }; | 69 | }; |
57 | 70 | ||
71 | struct keystone_serdes_data; | ||
72 | |||
58 | /* | 73 | /* |
59 | * SerDes ops | 74 | * SerDes ops |
60 | */ | 75 | */ |
61 | struct keystone_serdes_ops { | 76 | struct keystone_serdes_ops { |
62 | int (*config_lanes)(u32 lanes, | 77 | int (*config_lanes)(u32 lanes, |
63 | u32 baud, | 78 | u32 baud, |
64 | struct device *dev, | 79 | struct keystone_serdes_data *serdes); |
65 | void __iomem *regs, | ||
66 | void __iomem *sts_reg, | ||
67 | struct keystone_serdes_config *serdes_config); | ||
68 | int (*start_tx_lanes)(u32 lanes, | 80 | int (*start_tx_lanes)(u32 lanes, |
69 | struct device *dev, | 81 | struct keystone_serdes_data *serdes); |
70 | void __iomem *regs, | 82 | int (*wait_lanes_ok)(u32 lanes, |
71 | struct keystone_serdes_config *serdes_config); | 83 | struct keystone_serdes_data *serdes); |
72 | int (*wait_lanes_ok)(u32 lanes, void __iomem *regs); | 84 | int (*shutdown_lanes)(u32 lanes, |
73 | int (*shutdown_lanes)(u32 lanes, void __iomem *regs); | 85 | struct keystone_serdes_data *serdes); |
74 | void (*fix_unstable_lanes)(u32 lanes, | 86 | void (*fix_unstable_lanes)(u32 lanes, |
75 | struct device *dev, | 87 | struct keystone_serdes_data *serdes); |
76 | void __iomem *regs); | 88 | int (*calibrate_lanes)(u32 lanes, |
89 | struct keystone_serdes_data *serdes); | ||
90 | }; | ||
91 | |||
92 | /* | ||
93 | * SerDes structure | ||
94 | */ | ||
95 | struct keystone_serdes_data { | ||
96 | /* SerDes Ops */ | ||
97 | const struct keystone_serdes_ops *ops; | ||
98 | |||
99 | /* Associated device */ | ||
100 | struct device *dev; | ||
101 | |||
102 | /* SerDes register base and STS register for K1 */ | ||
103 | void __iomem *regs; | ||
104 | void __iomem *sts_reg; | ||
105 | |||
106 | /* Pointer to the SerDes configuration */ | ||
107 | struct keystone_serdes_config *config; | ||
108 | |||
109 | /* Sysfs management */ | ||
110 | struct kobject *serdes_kobj; | ||
111 | struct kobject serdes_rx_kobj; | ||
112 | struct kobject serdes_tx_kobj; | ||
77 | }; | 113 | }; |
78 | 114 | ||
79 | extern int keystone_rio_serdes_register( | 115 | extern int keystone_rio_serdes_register( |
80 | u16 serdes_type, | 116 | u16 serdes_type, |
81 | const struct keystone_serdes_ops **p_ops); | 117 | void __iomem *regs, |
118 | void __iomem *sts_reg, | ||
119 | struct device *dev, | ||
120 | struct keystone_serdes_data *serdes, | ||
121 | struct keystone_serdes_config *serdes_config); | ||
82 | 122 | ||
83 | #endif /* KEYSTONE_RIO_SERDES_H */ | 123 | #endif /* KEYSTONE_RIO_SERDES_H */ |