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authorHao Zhang2014-06-06 09:09:25 -0500
committerMurali Karicheri2014-12-03 10:30:08 -0600
commitfe6e8973450c974d520ce961a9b7447e49021859 (patch)
tree4237a94128d65f633202b53a8660e9c5453d20c1 /drivers/net/ethernet/ti/keystone_ethss2.c
parentfd0548f818eefc6cfd1c291c80781a1990ca2359 (diff)
downloadlinux-fe6e8973450c974d520ce961a9b7447e49021859.tar.gz
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net: keystone: ethernet: create ethss2 plugin driver
This patch creates a new 1GB Ethernet driver plugin driver to support the NSS (Network Sub-System) for TI Keystone II K2E and K2L devices. The new driver supports a Ethernet switch with up to 8 EMAC (slave) ports and 1 host port. Signed-off-by: Hao Zhang <hzhang@ti.com>
Diffstat (limited to 'drivers/net/ethernet/ti/keystone_ethss2.c')
-rw-r--r--drivers/net/ethernet/ti/keystone_ethss2.c4062
1 files changed, 4062 insertions, 0 deletions
diff --git a/drivers/net/ethernet/ti/keystone_ethss2.c b/drivers/net/ethernet/ti/keystone_ethss2.c
new file mode 100644
index 00000000000..3d92e164b97
--- /dev/null
+++ b/drivers/net/ethernet/ti/keystone_ethss2.c
@@ -0,0 +1,4062 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated
3 * Authors: Hao Zhang <hzhang@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/clk.h>
18#include <linux/phy.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/uaccess.h>
23#include <linux/if_vlan.h>
24#include <linux/of_mdio.h>
25#include <linux/ethtool.h>
26#include <linux/if_ether.h>
27#include <linux/net_tstamp.h>
28#include <linux/netdevice.h>
29#include <linux/interrupt.h>
30#include <linux/dmaengine.h>
31#include <linux/dma-mapping.h>
32#include <linux/scatterlist.h>
33#include <linux/etherdevice.h>
34#include <linux/platform_device.h>
35#include <linux/ptp_classify.h>
36
37#include "cpsw_ale.h"
38#include "keystone_net.h"
39#include "cpts.h"
40#include "keystone_serdes.h"
41
42#define NETCP2_DRIVER_NAME "TI KeyStone Ethernet Driver 2"
43#define NETCP2_DRIVER_VERSION "v0.0.0"
44
45#define CPSW2_MODULE_NAME "keystone-cpsw2"
46
47#define CPSW2_SGMII_IDENT(reg) ((reg >> 16) & 0xffff)
48#define CPSW2_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
49#define CPSW2_MINOR_VERSION(reg) (reg & 0xff)
50#define CPSW2_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
51
52#define DEVICE_EMACSL_RESET_POLL_COUNT 100
53
54#define CPSW2_TIMER_INTERVAL (HZ / 10)
55
56/* Soft reset register values */
57#define SOFT_RESET_MASK BIT(0)
58#define SOFT_RESET BIT(0)
59
60#define MACSL_RX_ENABLE_CSF BIT(23)
61#define MACSL_RX_ENABLE_EXT_CTL BIT(18)
62#define MACSL_ENABLE BIT(5)
63#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
64
65#define CPSW2_NUM_PORTS 9
66#define CPSW2_CTL_P0_ENABLE BIT(2)
67#define CPSW2_CTL_VLAN_AWARE BIT(1)
68#define CPSW2_REG_VAL_STAT_ENABLE_ALL(x) ((1 << (x)) - 1)
69
70#define CPSW2_MASK_ALL_PORTS(x) ((1 << (x)) - 1)
71#define CPSW2_MASK_PHYS_PORTS(x) ((1 << (x)) - 2)
72#define CPSW2_MASK_NO_PORTS 0
73
74#define CPSW2_STATS0_MODULE 0
75#define CPSW2_STATS1_MODULE 1
76#define CPSW2_STATS2_MODULE 2
77#define CPSW2_STATS3_MODULE 3
78#define CPSW2_STATS4_MODULE 4
79#define CPSW2_STATS5_MODULE 5
80#define CPSW2_STATS6_MODULE 6
81#define CPSW2_STATS7_MODULE 7
82#define CPSW2_STATS8_MODULE 8
83
84#define MAX_SIZE_STREAM_BUFFER 9504
85
86/* Px_TS_CTL register */
87#define CPSW2_TS_RX_ANX_F_EN BIT(0)
88#define CPSW2_TS_RX_VLAN_LT1_EN BIT(1)
89#define CPSW2_TS_RX_VLAN_LT2_EN BIT(2)
90#define CPSW2_TS_RX_ANX_D_EN BIT(3)
91#define CPSW2_TS_TX_ANX_F_EN BIT(4)
92#define CPSW2_TS_TX_VLAN_LT1_EN BIT(5)
93#define CPSW2_TS_TX_VLAN_LT2_EN BIT(6)
94#define CPSW2_TS_TX_ANX_D_EN BIT(7)
95#define CPSW2_TS_LT2_EN BIT(8)
96#define CPSW2_TS_RX_ANX_E_EN BIT(9)
97#define CPSW2_TS_TX_ANX_E_EN BIT(10)
98#define CPSW2_TS_TX_HOST_TS_EN BIT(11)
99#define CPSW2_TS_MSG_TYPE_EN_SHIFT 16
100#define CPSW2_TS_MSG_TYPE_EN_MASK 0xffff
101
102/* Px_TS_SEQ_LTYPE */
103#define CPSW2_TS_LTYPE1_SHIFT 0
104#define CPSW2_TS_LTYPE1_MASK 0xffff
105#define CPSW2_TS_SEQ_ID_OFS_SHIFT 16
106#define CPSW2_TS_SEQ_ID_OFS_MASK 0x3f
107
108/* Px_TS_VLAN_LTYPE */
109#define CPSW2_TS_VLAN_LTYPE1_SHIFT 0
110#define CPSW2_TS_VLAN_LTYPE1_MASK 0xffff
111#define CPSW2_TS_VLAN_LTYPE2_SHIFT 16
112#define CPSW2_TS_VLAN_LTYPE2_MASK 0xffff
113
114/* Px_TS_CTL_LTYPE2 */
115#define CPSW2_TS_LTYPE2_SHIFT 0
116#define CPSW2_TS_LTYPE2_MASK 0xffff
117#define CPSW2_TS_107 BIT(16)
118#define CPSW2_TS_129 BIT(17)
119#define CPSW2_TS_130 BIT(18)
120#define CPSW2_TS_131 BIT(19)
121#define CPSW2_TS_132 BIT(20)
122#define CPSW2_TS_319 BIT(21)
123#define CPSW2_TS_320 BIT(22)
124#define CPSW2_TS_TTL_NONZERO BIT(23)
125#define CPSW2_TS_UNI_EN BIT(24)
126#define CPSW2_TS_UNI_EN_SHIFT 24
127
128/* Px_TS_CTL2 */
129#define CPSW2_TS_MCAST_TYPE_EN_SHIFT 0
130#define CPSW2_TS_MCAST_TYPE_EN_MASK 0xff
131#define CPSW2_TS_DOMAIN_OFFSET_SHIFT 16
132#define CPSW2_TS_DOMAIN_OFFSET_MASK 0x3f
133
134#define CPSW2_TS_TX_ANX_ALL_EN \
135 (CPSW2_TS_TX_ANX_D_EN |\
136 CPSW2_TS_TX_ANX_E_EN |\
137 CPSW2_TS_TX_ANX_F_EN)
138
139
140#define CPSW2_TS_RX_ANX_ALL_EN \
141 (CPSW2_TS_RX_ANX_D_EN |\
142 CPSW2_TS_RX_ANX_E_EN |\
143 CPSW2_TS_RX_ANX_F_EN)
144
145#define CPSW2_TS_CTL_DST_PORT (CPSW2_TS_319)
146#define CPSW2_TS_CTL_DST_PORT_SHIFT 21
147
148#define CPSW2_TS_CTL_MADDR_ALL \
149 (CPSW2_TS_107 | CPSW2_TS_129 | CPSW2_TS_130 | \
150 CPSW2_TS_131 | CPSW2_TS_132)
151
152#define CPSW2_TS_CTL_MADDR_SHIFT 16
153
154/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
155#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
156
157#define MAX_SLAVES (CPSW2_NUM_PORTS - 1)
158
159/* s: 0-based slave_port */
160#define SGMII2_BASE(s) (((s) < 2) ? cpsw_dev->sgmii_port_regs : \
161 cpsw_dev->sgmii_port_regs + SGMII_REGS_SIZE * 2)
162
163
164/* CPSW Statistics register map size */
165#define CPSW2_STATS_REGS_SIZE 0x200
166
167/* CPSW slave port register map size */
168#define CPSW2_SLAVE_REGS_SIZE 0x1000
169
170/* CPSW SERDES */
171#define CPSW2_SERDES_MAX_NUM 2
172#define CPSW2_LANE_NUM_PER_SERDES 4
173
174struct cpts2_port_ts_ctl {
175 int uni;
176 u8 dst_port_map;
177 u8 maddr_map;
178 u8 ts_mcast_type;
179};
180
181struct cpsw2_slave {
182 struct cpsw2_slave_regs __iomem *regs;
183 int slave_num;
184 int port_num;
185 u32 mac_control;
186 struct phy_device *phy;
187 const char *phy_id;
188 struct cpsw_ale *ale;
189 u32 link_interface;
190 u8 phy_port_t;
191 struct cpts2_port_ts_ctl ts_ctl;
192};
193
194/* Offset 0x0000 */
195struct cpsw2_ss_regs {
196 u32 id_ver;
197 u32 synce_count;
198 u32 synce_mux;
199 u32 rsvd;
200 u32 ecc_control;
201 u32 ecc_int_stat_raw;
202 u32 ecc_int_stat_mask;
203 u32 ecc_int_en;
204};
205
206/* Offset 0x20000 */
207struct cpsw2_regs {
208 u32 id_ver;
209 u32 control;
210 u32 rsvd0[2];
211 u32 soft_reset;
212 u32 stat_port_en;
213 u32 ptype;
214 u32 soft_idle;
215 u32 thru_rate;
216 u32 gap_thresh;
217 u32 tx_start_wds;
218 u32 rsvd1;
219 u32 tx_glb_out_flow_thresh_set;
220 u32 tx_glb_out_flow_thresh_clr;
221 u32 tx_glb_buf_thresh_set_l;
222 u32 tx_glb_buf_thresh_set_h;
223 u32 tx_glb_buf_thresh_clr_l;
224 u32 tx_glb_buf_thresh_clr_h;
225};
226
227/* Offset 0x22000 + (0x1000 * slave port #) */
228struct cpsw2_slave_regs {
229 u32 rsvd0;
230 u32 control;
231 u32 rsvd1[2];
232 u32 blk_cnt;
233 u32 port_vlan;
234 u32 tx_pri_map;
235 u32 pri_ctl;
236 u32 rx_pri_map;
237 u32 rx_maxlen;
238 u32 tx_blks_pri;
239 u32 rsvd2[53];
240 u32 rx_dscp_ipv4_map[8];
241 u32 rx_dscp_ipv6_map[8];
242 u32 pri_send[8];
243 u32 pri_idle[8];
244 u32 tx_dest_thresh_set_l;
245 u32 tx_dest_thresh_set_h;
246 u32 tx_dest_thresh_clr_l;
247 u32 tx_dest_thresh_clr_h;
248 u32 tx_glb_buf_thresh_set_l;
249 u32 tx_glb_buf_thresh_set_h;
250 u32 tx_glb_buf_thresh_clr_l;
251 u32 tx_glb_buf_thresh_clr_h;
252 u32 rsvd3[88];
253 u32 tx_dest_out_flow_add_val_l;
254 u32 tx_dest_out_flow_add_val_h;
255 u32 sa_lo;
256 u32 sa_hi;
257 u32 ts_ctl;
258 u32 ts_seq_ltype;
259 u32 ts_vlan_ltype;
260 u32 ts_ctl_ltype2;
261 u32 ts_ctl2;
262 u32 rsvd4[3];
263 u32 mac_control;
264 u32 mac_status;
265 u32 soft_reset;
266 u32 mac_backoff_test;
267 u32 mac_rx_pause_timer;
268 u32 rsvd5[3];
269 u32 mac_rxn_pause_timer[8];
270 u32 mac_tx_pauset_imer;
271 u32 rsvd6[3];
272 u32 mac_txn_pause_timer[8];
273 u32 mac_emu_ctl;
274 u32 mac_tx_gap;
275};
276
277/* Offset 0x21000 */
278struct cpsw2_host_regs {
279 u32 rsvd0;
280 u32 control;
281 u32 rsvd1[2];
282 u32 blk_cnt;
283 u32 port_vlan;
284 u32 tx_pri_map;
285 u32 pri_ctl;
286 u32 rx_pri_map;
287 u32 rx_maxlen;
288 u32 tx_blks_pri;
289 u32 rsvd2[53];
290 u32 rx_dscp_ipv4_map[8];
291 u32 rx_dscp_ipv6_map[8];
292 u32 pri_send[8];
293 u32 pri_idle[8];
294 u32 tx_dest_thresh_set_l;
295 u32 tx_dest_thresh_set_h;
296 u32 tx_dest_thresh_clr_l;
297 u32 tx_dest_thresh_clr_h;
298 u32 tx_glb_buf_thresh_set_l;
299 u32 tx_glb_buf_thresh_set_h;
300 u32 tx_glb_buf_thresh_clr_l;
301 u32 tx_glb_buf_thresh_clr_h;
302 u32 rsvd3[88];
303 u32 src_id_a;
304 u32 src_id_b;
305 u32 rsvd4[6];
306 u32 host_blks_pri;
307};
308
309/* Offset 0x3a000 + (0x1000 * port #)*/
310struct cpsw2_hw_stats {
311 u32 rx_good_frames;
312 u32 rx_broadcast_frames;
313 u32 rx_multicast_frames;
314 u32 rx_pause_frames;
315 u32 rx_crc_errors;
316 u32 rx_align_code_errors;
317 u32 rx_oversized_frames;
318 u32 rx_jabber_frames;
319 u32 rx_undersized_frames;
320 u32 rx_fragments;
321 u32 ale_drop;
322 u32 ale_overrun_drop;
323 u32 rx_bytes;
324 u32 tx_good_frames;
325 u32 tx_broadcast_frames;
326 u32 tx_multicast_frames;
327 u32 tx_pause_frames;
328 u32 tx_deferred_frames;
329 u32 tx_collision_frames;
330 u32 tx_single_coll_frames;
331 u32 tx_mult_coll_frames;
332 u32 tx_excessive_collisions;
333 u32 tx_late_collisions;
334 u32 rx_ipg_error; /* Rx inter packet Gap error, 10G only */
335 u32 tx_carrier_sense_errors;
336 u32 tx_bytes;
337 u32 tx_64byte_frames;
338 u32 tx_65_to_127byte_frames;
339 u32 tx_128_to_255byte_frames;
340 u32 tx_256_to_511byte_frames;
341 u32 tx_512_to_1023byte_frames;
342 u32 tx_1024byte_frames;
343 u32 net_bytes;
344 u32 rx_drop;
345 u32 rx_port_mask_drop;
346 u32 tx_drop;
347 u32 ale_rate_limit_drop;
348 u32 ale_vid_ingress_drop;
349 u32 ale_da_eq_sa_drop;
350 u32 ale_block_drop;
351 u32 ale_secure_drop;
352 u32 ale_auth_drop;
353};
354
355/* Offset 0x3e000 */
356struct cpsw2_ale_regs {
357 u32 ale_idver;
358 u32 ale_status;
359 u32 ale_control;
360 u32 ale_control2;
361 u32 ale_prescale;
362 u32 ale_aging_timer;
363 u32 rsvd0[2];
364 u32 ale_tblctl;
365 u32 rsvd1[4];
366 u32 ale_tblw2;
367 u32 ale_tblw1;
368 u32 ale_tblw0;
369 u32 ale_portctl[9];
370 u32 rsvd2[11];
371 u32 unkn_vlan;
372 u32 unkn_mcast_flood;
373 u32 unkn_reg_mcast_flood;
374 u32 force_untag_egress;
375 u32 rsvd3[8];
376 u32 vlan_mask_mux[8];
377 u32 rsvd4[8];
378 u32 policer_port_oui;
379 u32 policer_da_sa;
380 u32 policer_vlan;
381 u32 policer_ethertype_ipsa;
382 u32 policer_ipda;
383 u32 rsvd5;
384 u32 policer_pir;
385 u32 policer_cir;
386 u32 policer_tbl_ctl;
387 u32 policer_control;
388 u32 policer_test_ctl;
389 u32 policer_hit_status;
390 u32 rsvd6;
391 u32 thread_default;
392 u32 thread_control;
393 u32 thread_map;
394};
395
396struct cpsw2_priv {
397 struct device *dev;
398 struct clk *cpgmac;
399 struct netcp_device *netcp_device;
400 u32 num_slaves;
401 u32 ale_ageout;
402 u32 ale_entries;
403 u32 ale_ports;
404 u32 sgmii_module_ofs;
405 u32 switch_module_ofs;
406 u32 host_port_reg_ofs;
407 u32 slave_reg_ofs;
408 u32 hw_stats_reg_ofs;
409 u32 ale_reg_ofs;
410 u32 cpts_reg_ofs;
411
412 int host_port;
413 u32 rx_packet_max;
414
415 struct cpsw2_regs __iomem *regs;
416 struct cpsw2_ss_regs __iomem *ss_regs;
417 struct cpsw2_hw_stats __iomem *hw_stats_regs[CPSW2_NUM_PORTS];
418 struct cpsw2_host_regs __iomem *host_port_regs;
419 struct cpsw2_ale_regs __iomem *ale_reg;
420
421 void __iomem *sgmii_port_regs;
422
423 struct cpsw_ale *ale;
424 u32 ale_refcnt;
425
426 u32 link[MAX_SLAVES];
427 struct device_node *phy_node[MAX_SLAVES];
428
429 u32 intf_tx_queues;
430
431 u32 multi_if;
432 u32 slaves_per_interface;
433 u32 num_interfaces;
434 struct device_node *interfaces;
435 struct list_head cpsw_intf_head;
436
437 u64 hw_stats[72];
438 int init_serdes_at_probe;
439 struct kobject kobj;
440 struct kobject tx_pri_kobj;
441 struct kobject pvlan_kobj;
442 struct kobject port_ts_kobj[MAX_SLAVES];
443 struct kobject stats_kobj;
444 spinlock_t hw_stats_lock;
445 struct cpts cpts;
446 int cpts_registered;
447 int force_no_hwtstamp;
448 void __iomem *serdes_regs[CPSW2_SERDES_MAX_NUM];
449 u32 num_serdes;
450 u32 serdes_lanes;
451 struct serdes serdes;
452};
453
454struct cpsw2_intf {
455 struct net_device *ndev;
456 struct device *dev;
457 struct cpsw2_priv *cpsw_priv;
458 struct device_node *phy_node;
459 u32 num_slaves;
460 u32 slave_port;
461 struct cpsw2_slave *slaves;
462 u32 intf_tx_queues;
463 const char *tx_chan_name;
464 u32 tx_queue_depth;
465 struct netcp_tx_pipe tx_pipe;
466 u32 multi_if;
467 struct list_head cpsw_intf_list;
468 struct timer_list timer;
469 u32 sgmii_link;
470 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
471};
472
473/*
474 * Statistic management
475 */
476struct netcp2_ethtool_stat {
477 char desc[ETH_GSTRING_LEN];
478 int type;
479 u32 size;
480 int offset;
481};
482
483#define for_each_slave(priv, func, arg...) \
484 do { \
485 int idx, port; \
486 port = (priv)->slave_port; \
487 if ((priv)->multi_if) \
488 (func)((priv)->slaves, ##arg); \
489 else \
490 for (idx = 0; idx < (priv)->num_slaves; idx++) \
491 (func)((priv)->slaves + idx, ##arg); \
492 } while (0)
493
494#define FIELDINFO(_struct, field) FIELD_SIZEOF(_struct, field), \
495 offsetof(_struct, field)
496#define CPSW2_STATS0_INFO(field) "CPSW_0:"#field, CPSW2_STATS0_MODULE,\
497 FIELDINFO(struct cpsw2_hw_stats,\
498 field)
499#define CPSW2_STATS1_INFO(field) "CPSW_1:"#field, CPSW2_STATS1_MODULE,\
500 FIELDINFO(struct cpsw2_hw_stats,\
501 field)
502#define CPSW2_STATS2_INFO(field) "CPSW_2:"#field, CPSW2_STATS2_MODULE,\
503 FIELDINFO(struct cpsw2_hw_stats,\
504 field)
505#define CPSW2_STATS3_INFO(field) "CPSW_3:"#field, CPSW2_STATS3_MODULE,\
506 FIELDINFO(struct cpsw2_hw_stats,\
507 field)
508#define CPSW2_STATS4_INFO(field) "CPSW_4:"#field, CPSW2_STATS4_MODULE,\
509 FIELDINFO(struct cpsw2_hw_stats,\
510 field)
511#define CPSW2_STATS5_INFO(field) "CPSW_5:"#field, CPSW2_STATS5_MODULE,\
512 FIELDINFO(struct cpsw2_hw_stats,\
513 field)
514#define CPSW2_STATS6_INFO(field) "CPSW_6:"#field, CPSW2_STATS6_MODULE,\
515 FIELDINFO(struct cpsw2_hw_stats,\
516 field)
517#define CPSW2_STATS7_INFO(field) "CPSW_7:"#field, CPSW2_STATS7_MODULE,\
518 FIELDINFO(struct cpsw2_hw_stats,\
519 field)
520#define CPSW2_STATS8_INFO(field) "CPSW_8:"#field, CPSW2_STATS8_MODULE,\
521 FIELDINFO(struct cpsw2_hw_stats,\
522 field)
523
524static const struct netcp2_ethtool_stat et_stats[] = {
525 /* CPSW module 0 */
526 {CPSW2_STATS0_INFO(rx_good_frames)},
527 {CPSW2_STATS0_INFO(rx_broadcast_frames)},
528 {CPSW2_STATS0_INFO(rx_multicast_frames)},
529 {CPSW2_STATS0_INFO(rx_pause_frames)},
530 {CPSW2_STATS0_INFO(rx_crc_errors)},
531 {CPSW2_STATS0_INFO(rx_align_code_errors)},
532 {CPSW2_STATS0_INFO(rx_oversized_frames)},
533 {CPSW2_STATS0_INFO(rx_jabber_frames)},
534 {CPSW2_STATS0_INFO(rx_undersized_frames)},
535 {CPSW2_STATS0_INFO(rx_fragments)},
536 {CPSW2_STATS0_INFO(ale_drop)},
537 {CPSW2_STATS0_INFO(ale_overrun_drop)},
538 {CPSW2_STATS0_INFO(rx_bytes)},
539 {CPSW2_STATS0_INFO(tx_good_frames)},
540 {CPSW2_STATS0_INFO(tx_broadcast_frames)},
541 {CPSW2_STATS0_INFO(tx_multicast_frames)},
542 {CPSW2_STATS0_INFO(tx_pause_frames)},
543 {CPSW2_STATS0_INFO(tx_deferred_frames)},
544 {CPSW2_STATS0_INFO(tx_collision_frames)},
545 {CPSW2_STATS0_INFO(tx_single_coll_frames)},
546 {CPSW2_STATS0_INFO(tx_mult_coll_frames)},
547 {CPSW2_STATS0_INFO(tx_excessive_collisions)},
548 {CPSW2_STATS0_INFO(tx_late_collisions)},
549 {CPSW2_STATS0_INFO(rx_ipg_error)},
550 {CPSW2_STATS0_INFO(tx_carrier_sense_errors)},
551 {CPSW2_STATS0_INFO(tx_bytes)},
552 {CPSW2_STATS0_INFO(tx_64byte_frames)},
553 {CPSW2_STATS0_INFO(tx_65_to_127byte_frames)},
554 {CPSW2_STATS0_INFO(tx_128_to_255byte_frames)},
555 {CPSW2_STATS0_INFO(tx_256_to_511byte_frames)},
556 {CPSW2_STATS0_INFO(tx_512_to_1023byte_frames)},
557 {CPSW2_STATS0_INFO(tx_1024byte_frames)},
558 {CPSW2_STATS0_INFO(net_bytes)},
559 {CPSW2_STATS0_INFO(rx_drop)},
560 {CPSW2_STATS0_INFO(rx_port_mask_drop)},
561 {CPSW2_STATS0_INFO(tx_drop)},
562 {CPSW2_STATS0_INFO(ale_rate_limit_drop)},
563 {CPSW2_STATS0_INFO(ale_vid_ingress_drop)},
564 {CPSW2_STATS0_INFO(ale_da_eq_sa_drop)},
565 {CPSW2_STATS0_INFO(ale_block_drop)},
566 {CPSW2_STATS0_INFO(ale_secure_drop)},
567 {CPSW2_STATS0_INFO(ale_auth_drop)},
568 /* CPSW module 1 */
569 {CPSW2_STATS1_INFO(rx_good_frames)},
570 {CPSW2_STATS1_INFO(rx_broadcast_frames)},
571 {CPSW2_STATS1_INFO(rx_multicast_frames)},
572 {CPSW2_STATS1_INFO(rx_pause_frames)},
573 {CPSW2_STATS1_INFO(rx_crc_errors)},
574 {CPSW2_STATS1_INFO(rx_align_code_errors)},
575 {CPSW2_STATS1_INFO(rx_oversized_frames)},
576 {CPSW2_STATS1_INFO(rx_jabber_frames)},
577 {CPSW2_STATS1_INFO(rx_undersized_frames)},
578 {CPSW2_STATS1_INFO(rx_fragments)},
579 {CPSW2_STATS1_INFO(ale_drop)},
580 {CPSW2_STATS1_INFO(ale_overrun_drop)},
581 {CPSW2_STATS1_INFO(rx_bytes)},
582 {CPSW2_STATS1_INFO(tx_good_frames)},
583 {CPSW2_STATS1_INFO(tx_broadcast_frames)},
584 {CPSW2_STATS1_INFO(tx_multicast_frames)},
585 {CPSW2_STATS1_INFO(tx_pause_frames)},
586 {CPSW2_STATS1_INFO(tx_deferred_frames)},
587 {CPSW2_STATS1_INFO(tx_collision_frames)},
588 {CPSW2_STATS1_INFO(tx_single_coll_frames)},
589 {CPSW2_STATS1_INFO(tx_mult_coll_frames)},
590 {CPSW2_STATS1_INFO(tx_excessive_collisions)},
591 {CPSW2_STATS1_INFO(tx_late_collisions)},
592 {CPSW2_STATS1_INFO(rx_ipg_error)},
593 {CPSW2_STATS1_INFO(tx_carrier_sense_errors)},
594 {CPSW2_STATS1_INFO(tx_bytes)},
595 {CPSW2_STATS1_INFO(tx_64byte_frames)},
596 {CPSW2_STATS1_INFO(tx_65_to_127byte_frames)},
597 {CPSW2_STATS1_INFO(tx_128_to_255byte_frames)},
598 {CPSW2_STATS1_INFO(tx_256_to_511byte_frames)},
599 {CPSW2_STATS1_INFO(tx_512_to_1023byte_frames)},
600 {CPSW2_STATS1_INFO(tx_1024byte_frames)},
601 {CPSW2_STATS1_INFO(net_bytes)},
602 {CPSW2_STATS1_INFO(rx_drop)},
603 {CPSW2_STATS1_INFO(rx_port_mask_drop)},
604 {CPSW2_STATS1_INFO(tx_drop)},
605 {CPSW2_STATS1_INFO(ale_rate_limit_drop)},
606 {CPSW2_STATS1_INFO(ale_vid_ingress_drop)},
607 {CPSW2_STATS1_INFO(ale_da_eq_sa_drop)},
608 {CPSW2_STATS1_INFO(ale_block_drop)},
609 {CPSW2_STATS1_INFO(ale_secure_drop)},
610 {CPSW2_STATS1_INFO(ale_auth_drop)},
611 /* CPSW module 2 */
612 {CPSW2_STATS2_INFO(rx_good_frames)},
613 {CPSW2_STATS2_INFO(rx_broadcast_frames)},
614 {CPSW2_STATS2_INFO(rx_multicast_frames)},
615 {CPSW2_STATS2_INFO(rx_pause_frames)},
616 {CPSW2_STATS2_INFO(rx_crc_errors)},
617 {CPSW2_STATS2_INFO(rx_align_code_errors)},
618 {CPSW2_STATS2_INFO(rx_oversized_frames)},
619 {CPSW2_STATS2_INFO(rx_jabber_frames)},
620 {CPSW2_STATS2_INFO(rx_undersized_frames)},
621 {CPSW2_STATS2_INFO(rx_fragments)},
622 {CPSW2_STATS2_INFO(ale_drop)},
623 {CPSW2_STATS2_INFO(ale_overrun_drop)},
624 {CPSW2_STATS2_INFO(rx_bytes)},
625 {CPSW2_STATS2_INFO(tx_good_frames)},
626 {CPSW2_STATS2_INFO(tx_broadcast_frames)},
627 {CPSW2_STATS2_INFO(tx_multicast_frames)},
628 {CPSW2_STATS2_INFO(tx_pause_frames)},
629 {CPSW2_STATS2_INFO(tx_deferred_frames)},
630 {CPSW2_STATS2_INFO(tx_collision_frames)},
631 {CPSW2_STATS2_INFO(tx_single_coll_frames)},
632 {CPSW2_STATS2_INFO(tx_mult_coll_frames)},
633 {CPSW2_STATS2_INFO(tx_excessive_collisions)},
634 {CPSW2_STATS2_INFO(tx_late_collisions)},
635 {CPSW2_STATS2_INFO(rx_ipg_error)},
636 {CPSW2_STATS2_INFO(tx_carrier_sense_errors)},
637 {CPSW2_STATS2_INFO(tx_bytes)},
638 {CPSW2_STATS2_INFO(tx_64byte_frames)},
639 {CPSW2_STATS2_INFO(tx_65_to_127byte_frames)},
640 {CPSW2_STATS2_INFO(tx_128_to_255byte_frames)},
641 {CPSW2_STATS2_INFO(tx_256_to_511byte_frames)},
642 {CPSW2_STATS2_INFO(tx_512_to_1023byte_frames)},
643 {CPSW2_STATS2_INFO(tx_1024byte_frames)},
644 {CPSW2_STATS2_INFO(net_bytes)},
645 {CPSW2_STATS2_INFO(rx_drop)},
646 {CPSW2_STATS2_INFO(rx_port_mask_drop)},
647 {CPSW2_STATS2_INFO(tx_drop)},
648 {CPSW2_STATS2_INFO(ale_rate_limit_drop)},
649 {CPSW2_STATS2_INFO(ale_vid_ingress_drop)},
650 {CPSW2_STATS2_INFO(ale_da_eq_sa_drop)},
651 {CPSW2_STATS2_INFO(ale_block_drop)},
652 {CPSW2_STATS2_INFO(ale_secure_drop)},
653 {CPSW2_STATS2_INFO(ale_auth_drop)},
654 /* CPSW module 3 */
655 {CPSW2_STATS3_INFO(rx_good_frames)},
656 {CPSW2_STATS3_INFO(rx_broadcast_frames)},
657 {CPSW2_STATS3_INFO(rx_multicast_frames)},
658 {CPSW2_STATS3_INFO(rx_pause_frames)},
659 {CPSW2_STATS3_INFO(rx_crc_errors)},
660 {CPSW2_STATS3_INFO(rx_align_code_errors)},
661 {CPSW2_STATS3_INFO(rx_oversized_frames)},
662 {CPSW2_STATS3_INFO(rx_jabber_frames)},
663 {CPSW2_STATS3_INFO(rx_undersized_frames)},
664 {CPSW2_STATS3_INFO(rx_fragments)},
665 {CPSW2_STATS3_INFO(ale_drop)},
666 {CPSW2_STATS3_INFO(ale_overrun_drop)},
667 {CPSW2_STATS3_INFO(rx_bytes)},
668 {CPSW2_STATS3_INFO(tx_good_frames)},
669 {CPSW2_STATS3_INFO(tx_broadcast_frames)},
670 {CPSW2_STATS3_INFO(tx_multicast_frames)},
671 {CPSW2_STATS3_INFO(tx_pause_frames)},
672 {CPSW2_STATS3_INFO(tx_deferred_frames)},
673 {CPSW2_STATS3_INFO(tx_collision_frames)},
674 {CPSW2_STATS3_INFO(tx_single_coll_frames)},
675 {CPSW2_STATS3_INFO(tx_mult_coll_frames)},
676 {CPSW2_STATS3_INFO(tx_excessive_collisions)},
677 {CPSW2_STATS3_INFO(tx_late_collisions)},
678 {CPSW2_STATS3_INFO(rx_ipg_error)},
679 {CPSW2_STATS3_INFO(tx_carrier_sense_errors)},
680 {CPSW2_STATS3_INFO(tx_bytes)},
681 {CPSW2_STATS3_INFO(tx_64byte_frames)},
682 {CPSW2_STATS3_INFO(tx_65_to_127byte_frames)},
683 {CPSW2_STATS3_INFO(tx_128_to_255byte_frames)},
684 {CPSW2_STATS3_INFO(tx_256_to_511byte_frames)},
685 {CPSW2_STATS3_INFO(tx_512_to_1023byte_frames)},
686 {CPSW2_STATS3_INFO(tx_1024byte_frames)},
687 {CPSW2_STATS3_INFO(net_bytes)},
688 {CPSW2_STATS3_INFO(rx_drop)},
689 {CPSW2_STATS3_INFO(rx_port_mask_drop)},
690 {CPSW2_STATS3_INFO(tx_drop)},
691 {CPSW2_STATS3_INFO(ale_rate_limit_drop)},
692 {CPSW2_STATS3_INFO(ale_vid_ingress_drop)},
693 {CPSW2_STATS3_INFO(ale_da_eq_sa_drop)},
694 {CPSW2_STATS3_INFO(ale_block_drop)},
695 {CPSW2_STATS3_INFO(ale_secure_drop)},
696 {CPSW2_STATS3_INFO(ale_auth_drop)},
697 /* CPSW module 4 */
698 {CPSW2_STATS4_INFO(rx_good_frames)},
699 {CPSW2_STATS4_INFO(rx_broadcast_frames)},
700 {CPSW2_STATS4_INFO(rx_multicast_frames)},
701 {CPSW2_STATS4_INFO(rx_pause_frames)},
702 {CPSW2_STATS4_INFO(rx_crc_errors)},
703 {CPSW2_STATS4_INFO(rx_align_code_errors)},
704 {CPSW2_STATS4_INFO(rx_oversized_frames)},
705 {CPSW2_STATS4_INFO(rx_jabber_frames)},
706 {CPSW2_STATS4_INFO(rx_undersized_frames)},
707 {CPSW2_STATS4_INFO(rx_fragments)},
708 {CPSW2_STATS4_INFO(ale_drop)},
709 {CPSW2_STATS4_INFO(ale_overrun_drop)},
710 {CPSW2_STATS4_INFO(rx_bytes)},
711 {CPSW2_STATS4_INFO(tx_good_frames)},
712 {CPSW2_STATS4_INFO(tx_broadcast_frames)},
713 {CPSW2_STATS4_INFO(tx_multicast_frames)},
714 {CPSW2_STATS4_INFO(tx_pause_frames)},
715 {CPSW2_STATS4_INFO(tx_deferred_frames)},
716 {CPSW2_STATS4_INFO(tx_collision_frames)},
717 {CPSW2_STATS4_INFO(tx_single_coll_frames)},
718 {CPSW2_STATS4_INFO(tx_mult_coll_frames)},
719 {CPSW2_STATS4_INFO(tx_excessive_collisions)},
720 {CPSW2_STATS4_INFO(tx_late_collisions)},
721 {CPSW2_STATS4_INFO(rx_ipg_error)},
722 {CPSW2_STATS4_INFO(tx_carrier_sense_errors)},
723 {CPSW2_STATS4_INFO(tx_bytes)},
724 {CPSW2_STATS4_INFO(tx_64byte_frames)},
725 {CPSW2_STATS4_INFO(tx_65_to_127byte_frames)},
726 {CPSW2_STATS4_INFO(tx_128_to_255byte_frames)},
727 {CPSW2_STATS4_INFO(tx_256_to_511byte_frames)},
728 {CPSW2_STATS4_INFO(tx_512_to_1023byte_frames)},
729 {CPSW2_STATS4_INFO(tx_1024byte_frames)},
730 {CPSW2_STATS4_INFO(net_bytes)},
731 {CPSW2_STATS4_INFO(rx_drop)},
732 {CPSW2_STATS4_INFO(rx_port_mask_drop)},
733 {CPSW2_STATS4_INFO(tx_drop)},
734 {CPSW2_STATS4_INFO(ale_rate_limit_drop)},
735 {CPSW2_STATS4_INFO(ale_vid_ingress_drop)},
736 {CPSW2_STATS4_INFO(ale_da_eq_sa_drop)},
737 {CPSW2_STATS4_INFO(ale_block_drop)},
738 {CPSW2_STATS4_INFO(ale_secure_drop)},
739 {CPSW2_STATS4_INFO(ale_auth_drop)},
740 /* CPSW module 5 */
741 {CPSW2_STATS5_INFO(rx_good_frames)},
742 {CPSW2_STATS5_INFO(rx_broadcast_frames)},
743 {CPSW2_STATS5_INFO(rx_multicast_frames)},
744 {CPSW2_STATS5_INFO(rx_pause_frames)},
745 {CPSW2_STATS5_INFO(rx_crc_errors)},
746 {CPSW2_STATS5_INFO(rx_align_code_errors)},
747 {CPSW2_STATS5_INFO(rx_oversized_frames)},
748 {CPSW2_STATS5_INFO(rx_jabber_frames)},
749 {CPSW2_STATS5_INFO(rx_undersized_frames)},
750 {CPSW2_STATS5_INFO(rx_fragments)},
751 {CPSW2_STATS5_INFO(ale_drop)},
752 {CPSW2_STATS5_INFO(ale_overrun_drop)},
753 {CPSW2_STATS5_INFO(rx_bytes)},
754 {CPSW2_STATS5_INFO(tx_good_frames)},
755 {CPSW2_STATS5_INFO(tx_broadcast_frames)},
756 {CPSW2_STATS5_INFO(tx_multicast_frames)},
757 {CPSW2_STATS5_INFO(tx_pause_frames)},
758 {CPSW2_STATS5_INFO(tx_deferred_frames)},
759 {CPSW2_STATS5_INFO(tx_collision_frames)},
760 {CPSW2_STATS5_INFO(tx_single_coll_frames)},
761 {CPSW2_STATS5_INFO(tx_mult_coll_frames)},
762 {CPSW2_STATS5_INFO(tx_excessive_collisions)},
763 {CPSW2_STATS5_INFO(tx_late_collisions)},
764 {CPSW2_STATS5_INFO(rx_ipg_error)},
765 {CPSW2_STATS5_INFO(tx_carrier_sense_errors)},
766 {CPSW2_STATS5_INFO(tx_bytes)},
767 {CPSW2_STATS5_INFO(tx_64byte_frames)},
768 {CPSW2_STATS5_INFO(tx_65_to_127byte_frames)},
769 {CPSW2_STATS5_INFO(tx_128_to_255byte_frames)},
770 {CPSW2_STATS5_INFO(tx_256_to_511byte_frames)},
771 {CPSW2_STATS5_INFO(tx_512_to_1023byte_frames)},
772 {CPSW2_STATS5_INFO(tx_1024byte_frames)},
773 {CPSW2_STATS5_INFO(net_bytes)},
774 {CPSW2_STATS5_INFO(rx_drop)},
775 {CPSW2_STATS5_INFO(rx_port_mask_drop)},
776 {CPSW2_STATS5_INFO(tx_drop)},
777 {CPSW2_STATS5_INFO(ale_rate_limit_drop)},
778 {CPSW2_STATS5_INFO(ale_vid_ingress_drop)},
779 {CPSW2_STATS5_INFO(ale_da_eq_sa_drop)},
780 {CPSW2_STATS5_INFO(ale_block_drop)},
781 {CPSW2_STATS5_INFO(ale_secure_drop)},
782 {CPSW2_STATS5_INFO(ale_auth_drop)},
783 /* CPSW module 6 */
784 {CPSW2_STATS6_INFO(rx_good_frames)},
785 {CPSW2_STATS6_INFO(rx_broadcast_frames)},
786 {CPSW2_STATS6_INFO(rx_multicast_frames)},
787 {CPSW2_STATS6_INFO(rx_pause_frames)},
788 {CPSW2_STATS6_INFO(rx_crc_errors)},
789 {CPSW2_STATS6_INFO(rx_align_code_errors)},
790 {CPSW2_STATS6_INFO(rx_oversized_frames)},
791 {CPSW2_STATS6_INFO(rx_jabber_frames)},
792 {CPSW2_STATS6_INFO(rx_undersized_frames)},
793 {CPSW2_STATS6_INFO(rx_fragments)},
794 {CPSW2_STATS6_INFO(ale_drop)},
795 {CPSW2_STATS6_INFO(ale_overrun_drop)},
796 {CPSW2_STATS6_INFO(rx_bytes)},
797 {CPSW2_STATS6_INFO(tx_good_frames)},
798 {CPSW2_STATS6_INFO(tx_broadcast_frames)},
799 {CPSW2_STATS6_INFO(tx_multicast_frames)},
800 {CPSW2_STATS6_INFO(tx_pause_frames)},
801 {CPSW2_STATS6_INFO(tx_deferred_frames)},
802 {CPSW2_STATS6_INFO(tx_collision_frames)},
803 {CPSW2_STATS6_INFO(tx_single_coll_frames)},
804 {CPSW2_STATS6_INFO(tx_mult_coll_frames)},
805 {CPSW2_STATS6_INFO(tx_excessive_collisions)},
806 {CPSW2_STATS6_INFO(tx_late_collisions)},
807 {CPSW2_STATS6_INFO(rx_ipg_error)},
808 {CPSW2_STATS6_INFO(tx_carrier_sense_errors)},
809 {CPSW2_STATS6_INFO(tx_bytes)},
810 {CPSW2_STATS6_INFO(tx_64byte_frames)},
811 {CPSW2_STATS6_INFO(tx_65_to_127byte_frames)},
812 {CPSW2_STATS6_INFO(tx_128_to_255byte_frames)},
813 {CPSW2_STATS6_INFO(tx_256_to_511byte_frames)},
814 {CPSW2_STATS6_INFO(tx_512_to_1023byte_frames)},
815 {CPSW2_STATS6_INFO(tx_1024byte_frames)},
816 {CPSW2_STATS6_INFO(net_bytes)},
817 {CPSW2_STATS6_INFO(rx_drop)},
818 {CPSW2_STATS6_INFO(rx_port_mask_drop)},
819 {CPSW2_STATS6_INFO(tx_drop)},
820 {CPSW2_STATS6_INFO(ale_rate_limit_drop)},
821 {CPSW2_STATS6_INFO(ale_vid_ingress_drop)},
822 {CPSW2_STATS6_INFO(ale_da_eq_sa_drop)},
823 {CPSW2_STATS6_INFO(ale_block_drop)},
824 {CPSW2_STATS6_INFO(ale_secure_drop)},
825 {CPSW2_STATS6_INFO(ale_auth_drop)},
826 /* CPSW module 7 */
827 {CPSW2_STATS7_INFO(rx_good_frames)},
828 {CPSW2_STATS7_INFO(rx_broadcast_frames)},
829 {CPSW2_STATS7_INFO(rx_multicast_frames)},
830 {CPSW2_STATS7_INFO(rx_pause_frames)},
831 {CPSW2_STATS7_INFO(rx_crc_errors)},
832 {CPSW2_STATS7_INFO(rx_align_code_errors)},
833 {CPSW2_STATS7_INFO(rx_oversized_frames)},
834 {CPSW2_STATS7_INFO(rx_jabber_frames)},
835 {CPSW2_STATS7_INFO(rx_undersized_frames)},
836 {CPSW2_STATS7_INFO(rx_fragments)},
837 {CPSW2_STATS7_INFO(ale_drop)},
838 {CPSW2_STATS7_INFO(ale_overrun_drop)},
839 {CPSW2_STATS7_INFO(rx_bytes)},
840 {CPSW2_STATS7_INFO(tx_good_frames)},
841 {CPSW2_STATS7_INFO(tx_broadcast_frames)},
842 {CPSW2_STATS7_INFO(tx_multicast_frames)},
843 {CPSW2_STATS7_INFO(tx_pause_frames)},
844 {CPSW2_STATS7_INFO(tx_deferred_frames)},
845 {CPSW2_STATS7_INFO(tx_collision_frames)},
846 {CPSW2_STATS7_INFO(tx_single_coll_frames)},
847 {CPSW2_STATS7_INFO(tx_mult_coll_frames)},
848 {CPSW2_STATS7_INFO(tx_excessive_collisions)},
849 {CPSW2_STATS7_INFO(tx_late_collisions)},
850 {CPSW2_STATS7_INFO(rx_ipg_error)},
851 {CPSW2_STATS7_INFO(tx_carrier_sense_errors)},
852 {CPSW2_STATS7_INFO(tx_bytes)},
853 {CPSW2_STATS7_INFO(tx_64byte_frames)},
854 {CPSW2_STATS7_INFO(tx_65_to_127byte_frames)},
855 {CPSW2_STATS7_INFO(tx_128_to_255byte_frames)},
856 {CPSW2_STATS7_INFO(tx_256_to_511byte_frames)},
857 {CPSW2_STATS7_INFO(tx_512_to_1023byte_frames)},
858 {CPSW2_STATS7_INFO(tx_1024byte_frames)},
859 {CPSW2_STATS7_INFO(net_bytes)},
860 {CPSW2_STATS7_INFO(rx_drop)},
861 {CPSW2_STATS7_INFO(rx_port_mask_drop)},
862 {CPSW2_STATS7_INFO(tx_drop)},
863 {CPSW2_STATS7_INFO(ale_rate_limit_drop)},
864 {CPSW2_STATS7_INFO(ale_vid_ingress_drop)},
865 {CPSW2_STATS7_INFO(ale_da_eq_sa_drop)},
866 {CPSW2_STATS7_INFO(ale_block_drop)},
867 {CPSW2_STATS7_INFO(ale_secure_drop)},
868 {CPSW2_STATS7_INFO(ale_auth_drop)},
869 /* CPSW module 8 */
870 {CPSW2_STATS8_INFO(rx_good_frames)},
871 {CPSW2_STATS8_INFO(rx_broadcast_frames)},
872 {CPSW2_STATS8_INFO(rx_multicast_frames)},
873 {CPSW2_STATS8_INFO(rx_pause_frames)},
874 {CPSW2_STATS8_INFO(rx_crc_errors)},
875 {CPSW2_STATS8_INFO(rx_align_code_errors)},
876 {CPSW2_STATS8_INFO(rx_oversized_frames)},
877 {CPSW2_STATS8_INFO(rx_jabber_frames)},
878 {CPSW2_STATS8_INFO(rx_undersized_frames)},
879 {CPSW2_STATS8_INFO(rx_fragments)},
880 {CPSW2_STATS8_INFO(ale_drop)},
881 {CPSW2_STATS8_INFO(ale_overrun_drop)},
882 {CPSW2_STATS8_INFO(rx_bytes)},
883 {CPSW2_STATS8_INFO(tx_good_frames)},
884 {CPSW2_STATS8_INFO(tx_broadcast_frames)},
885 {CPSW2_STATS8_INFO(tx_multicast_frames)},
886 {CPSW2_STATS8_INFO(tx_pause_frames)},
887 {CPSW2_STATS8_INFO(tx_deferred_frames)},
888 {CPSW2_STATS8_INFO(tx_collision_frames)},
889 {CPSW2_STATS8_INFO(tx_single_coll_frames)},
890 {CPSW2_STATS8_INFO(tx_mult_coll_frames)},
891 {CPSW2_STATS8_INFO(tx_excessive_collisions)},
892 {CPSW2_STATS8_INFO(tx_late_collisions)},
893 {CPSW2_STATS8_INFO(rx_ipg_error)},
894 {CPSW2_STATS8_INFO(tx_carrier_sense_errors)},
895 {CPSW2_STATS8_INFO(tx_bytes)},
896 {CPSW2_STATS8_INFO(tx_64byte_frames)},
897 {CPSW2_STATS8_INFO(tx_65_to_127byte_frames)},
898 {CPSW2_STATS8_INFO(tx_128_to_255byte_frames)},
899 {CPSW2_STATS8_INFO(tx_256_to_511byte_frames)},
900 {CPSW2_STATS8_INFO(tx_512_to_1023byte_frames)},
901 {CPSW2_STATS8_INFO(tx_1024byte_frames)},
902 {CPSW2_STATS8_INFO(net_bytes)},
903 {CPSW2_STATS8_INFO(rx_drop)},
904 {CPSW2_STATS8_INFO(rx_port_mask_drop)},
905 {CPSW2_STATS8_INFO(tx_drop)},
906 {CPSW2_STATS8_INFO(ale_rate_limit_drop)},
907 {CPSW2_STATS8_INFO(ale_vid_ingress_drop)},
908 {CPSW2_STATS8_INFO(ale_da_eq_sa_drop)},
909 {CPSW2_STATS8_INFO(ale_block_drop)},
910 {CPSW2_STATS8_INFO(ale_secure_drop)},
911 {CPSW2_STATS8_INFO(ale_auth_drop)},
912};
913
914#define ETHTOOL_PORT_STATS_NUM (ARRAY_SIZE(et_stats)/CPSW2_NUM_PORTS)
915#define ETHTOOL_STATS_NUM(num_ports) (ETHTOOL_PORT_STATS_NUM * num_ports)
916
917struct cpsw2_attribute {
918 struct attribute attr;
919 ssize_t (*show)(struct cpsw2_priv *cpsw_dev,
920 struct cpsw2_attribute *attr, char *buf);
921 ssize_t (*store)(struct cpsw2_priv *cpsw_dev,
922 struct cpsw2_attribute *attr, const char *, size_t);
923 const struct cpsw2_mod_info *info;
924 ssize_t info_size;
925 void *context;
926};
927#define to_cpsw2_attr(_attr) container_of(_attr, struct cpsw2_attribute, attr)
928
929#define to_cpsw2_dev(obj) container_of(obj, struct cpsw2_priv, kobj)
930#define tx_pri_to_cpsw2_dev(obj) container_of(obj, struct cpsw2_priv, \
931 tx_pri_kobj)
932#define pvlan_to_cpsw2_dev(obj) container_of(obj, struct cpsw2_priv, pvlan_kobj)
933#define stats_to_cpsw2_dev(obj) container_of(obj, struct cpsw2_priv, stats_kobj)
934
935#define BITS(x) (BIT(x) - 1)
936#define BITMASK(n, s) (BITS(n) << (s))
937#define cpsw2_mod_info_field_val(r, i) \
938 ((r & BITMASK(i->bits, i->shift)) >> i->shift)
939
940#define for_each_intf(i, priv) \
941 list_for_each_entry((i), &(priv)->cpsw_intf_head, cpsw_intf_list)
942
943#define __CPSW2_ATTR_FULL(_name, _mode, _show, _store, _info, \
944 _info_size, _ctxt) \
945 { \
946 .attr = {.name = __stringify(_name), .mode = _mode }, \
947 .show = _show, \
948 .store = _store, \
949 .info = _info, \
950 .info_size = _info_size, \
951 .context = (_ctxt), \
952 }
953
954#define __CPSW2_ATTR(_name, _mode, _show, _store, _info) \
955 __CPSW2_ATTR_FULL(_name, _mode, _show, _store, _info, \
956 (ARRAY_SIZE(_info)), NULL)
957
958#define __CPSW2_CTXT_ATTR(_name, _mode, _show, _store, _info, _ctxt) \
959 __CPSW2_ATTR_FULL(_name, _mode, _show, _store, _info, \
960 (ARRAY_SIZE(_info)), _ctxt)
961
962struct cpsw2_mod_info {
963 const char *name;
964 int shift;
965 int bits;
966};
967
968struct cpsw2_parse_result {
969 int control;
970 int port;
971 u32 value;
972};
973
974static ssize_t cpsw2_attr_info_show(const struct cpsw2_mod_info *info,
975 int info_size, u32 reg, char *buf)
976{
977 int i, len = 0;
978
979 for (i = 0; i < info_size; i++, info++) {
980 len += snprintf(buf + len, PAGE_SIZE - len,
981 "%s=%d\n", info->name,
982 (int)cpsw2_mod_info_field_val(reg, info));
983 }
984
985 return len;
986}
987
988static ssize_t cpsw2_attr_parse_set_command(struct cpsw2_priv *cpsw_dev,
989 struct cpsw2_attribute *attr,
990 const char *buf, size_t count,
991 struct cpsw2_parse_result *res)
992{
993 char ctrl_str[33], tmp_str[9];
994 int port = -1, value, len, control;
995 unsigned long end;
996 const struct cpsw2_mod_info *info = attr->info;
997
998 len = strcspn(buf, ".=");
999 if (len >= 32)
1000 return -ENOMEM;
1001
1002 strncpy(ctrl_str, buf, len);
1003 ctrl_str[len] = '\0';
1004 buf += len;
1005
1006 if (*buf == '.') {
1007 ++buf;
1008 len = strcspn(buf, "=");
1009 if (len >= 8)
1010 return -ENOMEM;
1011 strncpy(tmp_str, buf, len);
1012 tmp_str[len] = '\0';
1013 if (kstrtoul(tmp_str, 0, &end))
1014 return -EINVAL;
1015 port = (int)end;
1016 buf += len;
1017 }
1018
1019 if (*buf != '=')
1020 return -EINVAL;
1021
1022 if (kstrtoul(buf + 1, 0, &end))
1023 return -EINVAL;
1024
1025 value = (int)end;
1026
1027 for (control = 0; control < attr->info_size; control++)
1028 if (strcmp(ctrl_str, info[control].name) == 0)
1029 break;
1030
1031 if (control >= attr->info_size)
1032 return -ENOENT;
1033
1034 res->control = control;
1035 res->port = port;
1036 res->value = value;
1037
1038 dev_info(cpsw_dev->dev, "parsed command %s.%d=%d\n",
1039 attr->info[control].name, port, value);
1040
1041 return 0;
1042}
1043
1044static inline void cpsw2_info_set_reg_field(void __iomem *r,
1045 const struct cpsw2_mod_info *info, int val)
1046{
1047 u32 rv;
1048
1049 rv = readl(r);
1050 rv = ((rv & ~BITMASK(info->bits, info->shift)) | (val << info->shift));
1051 writel(rv, r);
1052}
1053
1054static ssize_t cpsw2_version_show(struct cpsw2_priv *cpsw_dev,
1055 struct cpsw2_attribute *attr,
1056 char *buf)
1057{
1058 u32 reg;
1059
1060 reg = readl(&cpsw_dev->regs->id_ver);
1061
1062 return snprintf(buf, PAGE_SIZE,
1063 "cpsw version %d.%d (%d) SGMII identification value 0x%x\n",
1064 CPSW2_MAJOR_VERSION(reg), CPSW2_MINOR_VERSION(reg),
1065 CPSW2_RTL_VERSION(reg), CPSW2_SGMII_IDENT(reg));
1066}
1067
1068static struct cpsw2_attribute cpsw_version_attribute =
1069 __ATTR(version, S_IRUGO, cpsw2_version_show, NULL);
1070
1071static const struct cpsw2_mod_info cpsw_controls[] = {
1072 {
1073 .name = "vlan_aware",
1074 .shift = 1,
1075 .bits = 1,
1076 },
1077 {
1078 .name = "p0_enable",
1079 .shift = 2,
1080 .bits = 1,
1081 },
1082 {
1083 .name = "p0_pass_pri_tagged",
1084 .shift = 3,
1085 .bits = 1,
1086 },
1087 {
1088 .name = "p1_pass_pri_tagged",
1089 .shift = 4,
1090 .bits = 1,
1091 },
1092 {
1093 .name = "p2_pass_pri_tagged",
1094 .shift = 5,
1095 .bits = 1,
1096 },
1097 {
1098 .name = "p3_pass_pri_tagged",
1099 .shift = 6,
1100 .bits = 1,
1101 },
1102 {
1103 .name = "p4_pass_pri_tagged",
1104 .shift = 7,
1105 .bits = 1,
1106 },
1107 {
1108 .name = "p5_pass_pri_tagged",
1109 .shift = 8,
1110 .bits = 1,
1111 },
1112 {
1113 .name = "p6_pass_pri_tagged",
1114 .shift = 9,
1115 .bits = 1,
1116 },
1117 {
1118 .name = "p7_pass_pri_tagged",
1119 .shift = 10,
1120 .bits = 1,
1121 },
1122 {
1123 .name = "p8_pass_pri_tagged",
1124 .shift = 11,
1125 .bits = 1,
1126 },
1127 {
1128 .name = "p0_tx_crc_type",
1129 .shift = 12,
1130 .bits = 1,
1131 },
1132 {
1133 .name = "p0_tx_crc_remove",
1134 .shift = 13,
1135 .bits = 1,
1136 },
1137 {
1138 .name = "p0_rx_pad",
1139 .shift = 14,
1140 .bits = 1,
1141 },
1142 {
1143 .name = "p0_rx_pass_crc_err",
1144 .shift = 15,
1145 .bits = 1,
1146 },
1147};
1148
1149static ssize_t cpsw2_control_show(struct cpsw2_priv *cpsw_dev,
1150 struct cpsw2_attribute *attr,
1151 char *buf)
1152{
1153 u32 reg;
1154
1155 reg = readl(&cpsw_dev->regs->control);
1156 return cpsw2_attr_info_show(attr->info, attr->info_size, reg, buf);
1157}
1158
1159static ssize_t cpsw2_control_store(struct cpsw2_priv *cpsw_dev,
1160 struct cpsw2_attribute *attr,
1161 const char *buf, size_t count)
1162{
1163 const struct cpsw2_mod_info *i;
1164 struct cpsw2_parse_result res;
1165 void __iomem *r = NULL;
1166 int ret;
1167
1168
1169 ret = cpsw2_attr_parse_set_command(cpsw_dev, attr, buf, count, &res);
1170 if (ret)
1171 return ret;
1172
1173 i = &(attr->info[res.control]);
1174 r = &cpsw_dev->regs->control;
1175
1176 cpsw2_info_set_reg_field(r, i, res.value);
1177 return count;
1178}
1179
1180static struct cpsw2_attribute cpsw_control_attribute =
1181 __CPSW2_ATTR(control, S_IRUGO | S_IWUSR,
1182 cpsw2_control_show, cpsw2_control_store, cpsw_controls);
1183
1184static const struct cpsw2_mod_info cpsw_ptypes[] = {
1185 {
1186 .name = "escalate_pri_load_val",
1187 .shift = 0,
1188 .bits = 5,
1189 },
1190 {
1191 .name = "port0_pri_type_escalate",
1192 .shift = 8,
1193 .bits = 1,
1194 },
1195 {
1196 .name = "port1_pri_type_escalate",
1197 .shift = 9,
1198 .bits = 1,
1199 },
1200 {
1201 .name = "port2_pri_type_escalate",
1202 .shift = 10,
1203 .bits = 1,
1204 },
1205 {
1206 .name = "port3_pri_type_escalate",
1207 .shift = 11,
1208 .bits = 1,
1209 },
1210 {
1211 .name = "port4_pri_type_escalate",
1212 .shift = 12,
1213 .bits = 1,
1214 },
1215 {
1216 .name = "port5_pri_type_escalate",
1217 .shift = 13,
1218 .bits = 1,
1219 },
1220 {
1221 .name = "port6_pri_type_escalate",
1222 .shift = 14,
1223 .bits = 1,
1224 },
1225 {
1226 .name = "port7_pri_type_escalate",
1227 .shift = 15,
1228 .bits = 1,
1229 },
1230 {
1231 .name = "port8_pri_type_escalate",
1232 .shift = 16,
1233 .bits = 1,
1234 },
1235};
1236
1237static ssize_t cpsw2_pri_type_show(struct cpsw2_priv *cpsw_dev,
1238 struct cpsw2_attribute *attr,
1239 char *buf)
1240{
1241 u32 reg;
1242
1243 reg = readl(&cpsw_dev->regs->ptype);
1244
1245 return cpsw2_attr_info_show(attr->info, attr->info_size, reg, buf);
1246}
1247
1248static ssize_t cpsw2_pri_type_store(struct cpsw2_priv *cpsw_dev,
1249 struct cpsw2_attribute *attr,
1250 const char *buf, size_t count)
1251{
1252 const struct cpsw2_mod_info *i;
1253 struct cpsw2_parse_result res;
1254 void __iomem *r = NULL;
1255 int ret;
1256
1257
1258 ret = cpsw2_attr_parse_set_command(cpsw_dev, attr, buf, count, &res);
1259 if (ret)
1260 return ret;
1261
1262 i = &(attr->info[res.control]);
1263 r = &cpsw_dev->regs->ptype;
1264
1265 cpsw2_info_set_reg_field(r, i, res.value);
1266 return count;
1267}
1268
1269static struct cpsw2_attribute cpsw_pri_type_attribute =
1270 __CPSW2_ATTR(priority_type, S_IRUGO | S_IWUSR,
1271 cpsw2_pri_type_show,
1272 cpsw2_pri_type_store,
1273 cpsw_ptypes);
1274
1275static const struct cpsw2_mod_info cpsw_port_tx_pri_maps[] = {
1276 {
1277 .name = "port_tx_pri_0",
1278 .shift = 0,
1279 .bits = 3,
1280 },
1281 {
1282 .name = "port_tx_pri_1",
1283 .shift = 4,
1284 .bits = 3,
1285 },
1286 {
1287 .name = "port_tx_pri_2",
1288 .shift = 8,
1289 .bits = 3,
1290 },
1291 {
1292 .name = "port_tx_pri_3",
1293 .shift = 12,
1294 .bits = 3,
1295 },
1296 {
1297 .name = "port_tx_pri_4",
1298 .shift = 16,
1299 .bits = 3,
1300 },
1301 {
1302 .name = "port_tx_pri_5",
1303 .shift = 20,
1304 .bits = 3,
1305 },
1306 {
1307 .name = "port_tx_pri_6",
1308 .shift = 24,
1309 .bits = 3,
1310 },
1311 {
1312 .name = "port_tx_pri_7",
1313 .shift = 28,
1314 .bits = 3,
1315 },
1316};
1317
1318static ssize_t cpsw2_port_tx_pri_map_show(struct cpsw2_priv *cpsw_dev,
1319 struct cpsw2_attribute *attr,
1320 char *buf)
1321{
1322 int idx, len = 0, total_len = 0, port;
1323 struct cpsw2_intf *cpsw_intf;
1324 struct cpsw2_slave *slave;
1325 u32 reg;
1326
1327 port = (int)(attr->context);
1328
1329 for_each_intf(cpsw_intf, cpsw_dev) {
1330 if (cpsw_intf->multi_if) {
1331 slave = cpsw_intf->slaves;
1332 if (slave->port_num != port)
1333 continue;
1334 reg = readl(&slave->regs->tx_pri_map);
1335 len = cpsw2_attr_info_show(attr->info, attr->info_size,
1336 reg, buf+total_len);
1337 total_len += len;
1338 } else {
1339 for (idx = 0; idx < cpsw_intf->num_slaves; idx++) {
1340 slave = cpsw_intf->slaves + idx;
1341 if (slave->port_num != port)
1342 continue;
1343 reg = readl(&slave->regs->tx_pri_map);
1344 len = cpsw2_attr_info_show(attr->info,
1345 attr->info_size, reg, buf+total_len);
1346 total_len += len;
1347 }
1348 }
1349 }
1350 return total_len;
1351}
1352
1353static ssize_t cpsw2_port_tx_pri_map_store(struct cpsw2_priv *cpsw_dev,
1354 struct cpsw2_attribute *attr,
1355 const char *buf, size_t count)
1356{
1357 const struct cpsw2_mod_info *i;
1358 struct cpsw2_parse_result res;
1359 struct cpsw2_intf *cpsw_intf;
1360 struct cpsw2_slave *slave;
1361 void __iomem *r = NULL;
1362 int ret, idx, port;
1363
1364 port = (int)(attr->context);
1365
1366 ret = cpsw2_attr_parse_set_command(cpsw_dev, attr, buf, count, &res);
1367 if (ret)
1368 return ret;
1369
1370 i = &(attr->info[res.control]);
1371
1372 /* Slave port */
1373 for_each_intf(cpsw_intf, cpsw_dev) {
1374 if (cpsw_intf->multi_if) {
1375 slave = cpsw_intf->slaves;
1376 if (slave->port_num == port) {
1377 r = &slave->regs->tx_pri_map;
1378 goto set;
1379 }
1380 } else
1381 for (idx = 0; idx < cpsw_intf->num_slaves; idx++) {
1382 slave = cpsw_intf->slaves + idx;
1383 if (slave->port_num == port) {
1384 r = &slave->regs->tx_pri_map;
1385 goto set;
1386 }
1387 }
1388 }
1389
1390 if (!r)
1391 return -ENOENT;
1392
1393set:
1394 cpsw2_info_set_reg_field(r, i, res.value);
1395 return count;
1396}
1397
1398static struct cpsw2_attribute cpsw_tx_pri_1_attribute =
1399 __CPSW2_CTXT_ATTR(1, S_IRUGO | S_IWUSR,
1400 cpsw2_port_tx_pri_map_show,
1401 cpsw2_port_tx_pri_map_store,
1402 cpsw_port_tx_pri_maps, (void *)1);
1403
1404static struct cpsw2_attribute cpsw_tx_pri_2_attribute =
1405 __CPSW2_CTXT_ATTR(2, S_IRUGO | S_IWUSR,
1406 cpsw2_port_tx_pri_map_show,
1407 cpsw2_port_tx_pri_map_store,
1408 cpsw_port_tx_pri_maps, (void *)2);
1409
1410static struct cpsw2_attribute cpsw_tx_pri_3_attribute =
1411 __CPSW2_CTXT_ATTR(3, S_IRUGO | S_IWUSR,
1412 cpsw2_port_tx_pri_map_show,
1413 cpsw2_port_tx_pri_map_store,
1414 cpsw_port_tx_pri_maps, (void *)3);
1415
1416static struct cpsw2_attribute cpsw_tx_pri_4_attribute =
1417 __CPSW2_CTXT_ATTR(4, S_IRUGO | S_IWUSR,
1418 cpsw2_port_tx_pri_map_show,
1419 cpsw2_port_tx_pri_map_store,
1420 cpsw_port_tx_pri_maps, (void *)4);
1421static struct cpsw2_attribute cpsw_tx_pri_5_attribute =
1422 __CPSW2_CTXT_ATTR(5, S_IRUGO | S_IWUSR,
1423 cpsw2_port_tx_pri_map_show,
1424 cpsw2_port_tx_pri_map_store,
1425 cpsw_port_tx_pri_maps, (void *)5);
1426
1427static struct cpsw2_attribute cpsw_tx_pri_6_attribute =
1428 __CPSW2_CTXT_ATTR(6, S_IRUGO | S_IWUSR,
1429 cpsw2_port_tx_pri_map_show,
1430 cpsw2_port_tx_pri_map_store,
1431 cpsw_port_tx_pri_maps, (void *)6);
1432
1433static struct cpsw2_attribute cpsw_tx_pri_7_attribute =
1434 __CPSW2_CTXT_ATTR(7, S_IRUGO | S_IWUSR,
1435 cpsw2_port_tx_pri_map_show,
1436 cpsw2_port_tx_pri_map_store,
1437 cpsw_port_tx_pri_maps, (void *)7);
1438
1439static struct cpsw2_attribute cpsw_tx_pri_8_attribute =
1440 __CPSW2_CTXT_ATTR(8, S_IRUGO | S_IWUSR,
1441 cpsw2_port_tx_pri_map_show,
1442 cpsw2_port_tx_pri_map_store,
1443 cpsw_port_tx_pri_maps, (void *)8);
1444
1445static struct attribute *cpsw_tx_pri_default_attrs[] = {
1446 &cpsw_tx_pri_1_attribute.attr,
1447 &cpsw_tx_pri_2_attribute.attr,
1448 &cpsw_tx_pri_3_attribute.attr,
1449 &cpsw_tx_pri_4_attribute.attr,
1450 &cpsw_tx_pri_5_attribute.attr,
1451 &cpsw_tx_pri_6_attribute.attr,
1452 &cpsw_tx_pri_7_attribute.attr,
1453 &cpsw_tx_pri_8_attribute.attr,
1454 NULL
1455};
1456
1457static ssize_t cpsw2_tx_pri_attr_show(struct kobject *kobj,
1458 struct attribute *attr, char *buf)
1459{
1460 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
1461 struct cpsw2_priv *cpsw_dev = tx_pri_to_cpsw2_dev(kobj);
1462
1463 if (!attribute->show)
1464 return -EIO;
1465
1466 return attribute->show(cpsw_dev, attribute, buf);
1467}
1468
1469static ssize_t cpsw2_tx_pri_attr_store(struct kobject *kobj,
1470 struct attribute *attr, const char *buf, size_t count)
1471{
1472 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
1473 struct cpsw2_priv *cpsw_dev = tx_pri_to_cpsw2_dev(kobj);
1474
1475 if (!attribute->store)
1476 return -EIO;
1477
1478 return attribute->store(cpsw_dev, attribute, buf, count);
1479}
1480
1481static const struct sysfs_ops cpsw_tx_pri_sysfs_ops = {
1482 .show = cpsw2_tx_pri_attr_show,
1483 .store = cpsw2_tx_pri_attr_store,
1484};
1485
1486static struct kobj_type cpsw_tx_pri_ktype = {
1487 .sysfs_ops = &cpsw_tx_pri_sysfs_ops,
1488 .default_attrs = cpsw_tx_pri_default_attrs,
1489};
1490
1491static const struct cpsw2_mod_info cpsw_port_vlans[] = {
1492 {
1493 .name = "port_vlan_id",
1494 .shift = 0,
1495 .bits = 12,
1496 },
1497 {
1498 .name = "port_cfi",
1499 .shift = 12,
1500 .bits = 1,
1501 },
1502 {
1503 .name = "port_vlan_pri",
1504 .shift = 13,
1505 .bits = 3,
1506 },
1507};
1508
1509static ssize_t cpsw2_port_vlan_show(struct cpsw2_priv *cpsw_dev,
1510 struct cpsw2_attribute *attr,
1511 char *buf)
1512{
1513 int idx, len = 0, total_len = 0, port;
1514 struct cpsw2_intf *cpsw_intf;
1515 struct cpsw2_slave *slave;
1516 u32 reg;
1517
1518 port = (int)(attr->context);
1519
1520 if (port == cpsw_dev->host_port) {
1521 /* Host port */
1522 reg = readl(&cpsw_dev->host_port_regs->port_vlan);
1523 len = cpsw2_attr_info_show(attr->info, attr->info_size,
1524 reg, buf);
1525 return len;
1526 }
1527
1528 /* Slave ports */
1529 for_each_intf(cpsw_intf, cpsw_dev) {
1530 if (cpsw_intf->multi_if) {
1531 slave = cpsw_intf->slaves;
1532 if (slave->port_num != port)
1533 continue;
1534 reg = readl(&slave->regs->port_vlan);
1535 len = cpsw2_attr_info_show(attr->info, attr->info_size,
1536 reg, buf+total_len);
1537 total_len += len;
1538 } else {
1539 for (idx = 0; idx < cpsw_intf->num_slaves; idx++) {
1540 slave = cpsw_intf->slaves + idx;
1541 if (slave->port_num != port)
1542 continue;
1543 reg = readl(&slave->regs->port_vlan);
1544 len = cpsw2_attr_info_show(attr->info,
1545 attr->info_size, reg, buf+total_len);
1546 total_len += len;
1547 }
1548 }
1549 }
1550 return total_len;
1551}
1552
1553static ssize_t cpsw2_port_vlan_store(struct cpsw2_priv *cpsw_dev,
1554 struct cpsw2_attribute *attr,
1555 const char *buf, size_t count)
1556{
1557 const struct cpsw2_mod_info *i;
1558 struct cpsw2_parse_result res;
1559 struct cpsw2_intf *cpsw_intf;
1560 struct cpsw2_slave *slave;
1561 void __iomem *r = NULL;
1562 int ret, idx, port;
1563
1564 port = (int)(attr->context);
1565
1566 ret = cpsw2_attr_parse_set_command(cpsw_dev, attr, buf, count, &res);
1567 if (ret)
1568 return ret;
1569
1570 i = &(attr->info[res.control]);
1571
1572 /* Host port */
1573 if (port == cpsw_dev->host_port) {
1574 r = &cpsw_dev->host_port_regs->port_vlan;
1575 goto set;
1576 }
1577
1578 /* Slave port */
1579 for_each_intf(cpsw_intf, cpsw_dev) {
1580 if (cpsw_intf->multi_if) {
1581 slave = cpsw_intf->slaves;
1582 if (slave->port_num == port) {
1583 r = &slave->regs->port_vlan;
1584 goto set;
1585 }
1586 } else
1587 for (idx = 0; idx < cpsw_intf->num_slaves; idx++) {
1588 slave = cpsw_intf->slaves + idx;
1589 if (slave->port_num == port) {
1590 r = &slave->regs->port_vlan;
1591 goto set;
1592 }
1593 }
1594 }
1595
1596 if (!r)
1597 return -ENOENT;
1598
1599set:
1600 cpsw2_info_set_reg_field(r, i, res.value);
1601 return count;
1602}
1603
1604static struct cpsw2_attribute cpsw_pvlan_0_attribute =
1605 __CPSW2_CTXT_ATTR(0, S_IRUGO | S_IWUSR,
1606 cpsw2_port_vlan_show,
1607 cpsw2_port_vlan_store,
1608 cpsw_port_vlans, (void *)0);
1609
1610static struct cpsw2_attribute cpsw_pvlan_1_attribute =
1611 __CPSW2_CTXT_ATTR(1, S_IRUGO | S_IWUSR,
1612 cpsw2_port_vlan_show,
1613 cpsw2_port_vlan_store,
1614 cpsw_port_vlans, (void *)1);
1615
1616static struct cpsw2_attribute cpsw_pvlan_2_attribute =
1617 __CPSW2_CTXT_ATTR(2, S_IRUGO | S_IWUSR,
1618 cpsw2_port_vlan_show,
1619 cpsw2_port_vlan_store,
1620 cpsw_port_vlans, (void *)2);
1621
1622static struct cpsw2_attribute cpsw_pvlan_3_attribute =
1623 __CPSW2_CTXT_ATTR(3, S_IRUGO | S_IWUSR,
1624 cpsw2_port_vlan_show,
1625 cpsw2_port_vlan_store,
1626 cpsw_port_vlans, (void *)3);
1627
1628static struct cpsw2_attribute cpsw_pvlan_4_attribute =
1629 __CPSW2_CTXT_ATTR(4, S_IRUGO | S_IWUSR,
1630 cpsw2_port_vlan_show,
1631 cpsw2_port_vlan_store,
1632 cpsw_port_vlans, (void *)4);
1633static struct cpsw2_attribute cpsw_pvlan_5_attribute =
1634 __CPSW2_CTXT_ATTR(5, S_IRUGO | S_IWUSR,
1635 cpsw2_port_vlan_show,
1636 cpsw2_port_vlan_store,
1637 cpsw_port_vlans, (void *)5);
1638
1639static struct cpsw2_attribute cpsw_pvlan_6_attribute =
1640 __CPSW2_CTXT_ATTR(6, S_IRUGO | S_IWUSR,
1641 cpsw2_port_vlan_show,
1642 cpsw2_port_vlan_store,
1643 cpsw_port_vlans, (void *)6);
1644
1645static struct cpsw2_attribute cpsw_pvlan_7_attribute =
1646 __CPSW2_CTXT_ATTR(7, S_IRUGO | S_IWUSR,
1647 cpsw2_port_vlan_show,
1648 cpsw2_port_vlan_store,
1649 cpsw_port_vlans, (void *)7);
1650
1651static struct cpsw2_attribute cpsw_pvlan_8_attribute =
1652 __CPSW2_CTXT_ATTR(8, S_IRUGO | S_IWUSR,
1653 cpsw2_port_vlan_show,
1654 cpsw2_port_vlan_store,
1655 cpsw_port_vlans, (void *)8);
1656
1657static struct attribute *cpsw_pvlan_default_attrs[] = {
1658 &cpsw_pvlan_0_attribute.attr,
1659 &cpsw_pvlan_1_attribute.attr,
1660 &cpsw_pvlan_2_attribute.attr,
1661 &cpsw_pvlan_3_attribute.attr,
1662 &cpsw_pvlan_4_attribute.attr,
1663 &cpsw_pvlan_5_attribute.attr,
1664 &cpsw_pvlan_6_attribute.attr,
1665 &cpsw_pvlan_7_attribute.attr,
1666 &cpsw_pvlan_8_attribute.attr,
1667 NULL
1668};
1669
1670static ssize_t cpsw2_pvlan_attr_show(struct kobject *kobj,
1671 struct attribute *attr, char *buf)
1672{
1673 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
1674 struct cpsw2_priv *cpsw_dev = pvlan_to_cpsw2_dev(kobj);
1675
1676 if (!attribute->show)
1677 return -EIO;
1678
1679 return attribute->show(cpsw_dev, attribute, buf);
1680}
1681
1682static ssize_t cpsw2_pvlan_attr_store(struct kobject *kobj,
1683 struct attribute *attr, const char *buf, size_t count)
1684{
1685 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
1686 struct cpsw2_priv *cpsw_dev = pvlan_to_cpsw2_dev(kobj);
1687
1688 if (!attribute->store)
1689 return -EIO;
1690
1691 return attribute->store(cpsw_dev, attribute, buf, count);
1692}
1693
1694static const struct sysfs_ops cpsw_pvlan_sysfs_ops = {
1695 .show = cpsw2_pvlan_attr_show,
1696 .store = cpsw2_pvlan_attr_store,
1697};
1698
1699static struct kobj_type cpsw_pvlan_ktype = {
1700 .sysfs_ops = &cpsw_pvlan_sysfs_ops,
1701 .default_attrs = cpsw_pvlan_default_attrs,
1702};
1703
1704struct cpsw2_ts_attribute {
1705 struct attribute attr;
1706 ssize_t (*show)(struct cpsw2_priv *cpsw_dev,
1707 struct cpsw2_ts_attribute *attr, char *buf, void *);
1708 ssize_t (*store)(struct cpsw2_priv *cpsw_dev,
1709 struct cpsw2_ts_attribute *attr, const char *, size_t, void *);
1710};
1711#define to_cpsw2_ts_attr(_attr) \
1712 container_of(_attr, struct cpsw2_ts_attribute, attr)
1713
1714#define __CPSW2_TS_ATTR(_name, _mode, _show, _store) \
1715 { \
1716 .attr = {.name = __stringify(_name), .mode = _mode }, \
1717 .show = _show, \
1718 .store = _store, \
1719 }
1720
1721#define pts_to_cpsw2_dev(obj) container_of(obj, struct cpsw2_priv, pts_kobj)
1722
1723#define pts_n_to_cpsw2_dev(obj, n) \
1724 container_of(obj, struct cpsw2_priv, port_ts_kobj[n])
1725
1726static struct cpsw2_slave *cpsw2_port_num_get_slave(struct cpsw2_priv *cpsw_dev,
1727 int port)
1728{
1729 struct cpsw2_intf *cpsw_intf;
1730 struct cpsw2_slave *slave = NULL;
1731 int idx;
1732
1733 for_each_intf(cpsw_intf, cpsw_dev) {
1734 if (cpsw_intf->multi_if) {
1735 slave = cpsw_intf->slaves;
1736 if (slave->port_num == port)
1737 return slave;
1738 } else {
1739 for (idx = 0; idx < cpsw_intf->num_slaves; idx++) {
1740 slave = cpsw_intf->slaves + idx;
1741 if (slave->port_num == port)
1742 return slave;
1743 }
1744 }
1745 }
1746 return NULL;
1747}
1748
1749static ssize_t cpsw2_port_ts_uni_show(struct cpsw2_priv *cpsw_dev,
1750 struct cpsw2_ts_attribute *attr,
1751 char *buf, void *context)
1752{
1753 struct cpsw2_slave *slave;
1754 int len, port;
1755 u32 reg;
1756
1757 port = (int)context;
1758
1759 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1760 if (!slave)
1761 return 0;
1762
1763 reg = readl(&slave->regs->ts_ctl_ltype2);
1764 len = snprintf(buf, PAGE_SIZE, "%lu\n",
1765 ((reg & CPSW2_TS_UNI_EN) >> CPSW2_TS_UNI_EN_SHIFT));
1766
1767 return len;
1768}
1769
1770static ssize_t cpsw2_port_ts_uni_store(struct cpsw2_priv *cpsw_dev,
1771 struct cpsw2_ts_attribute *attr,
1772 const char *buf, size_t count, void *context)
1773{
1774 struct cpsw2_slave *slave;
1775 int port, val;
1776 u32 reg, mode;
1777
1778 port = (int)context;
1779
1780 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1781 if (!slave)
1782 return 0;
1783
1784 if (kstrtoint(buf, 0, &val) < 0)
1785 return -EINVAL;
1786
1787
1788 if (val)
1789 mode = CPSW2_TS_UNI_EN;
1790 else
1791 mode = (slave->ts_ctl.maddr_map << CPSW2_TS_CTL_MADDR_SHIFT);
1792
1793 reg = readl(&slave->regs->ts_ctl_ltype2);
1794 reg &= ~(CPSW2_TS_UNI_EN | CPSW2_TS_CTL_MADDR_ALL);
1795 reg |= mode;
1796 writel(reg, &slave->regs->ts_ctl_ltype2);
1797
1798 slave->ts_ctl.uni = (val ? 1 : 0);
1799 return count;
1800}
1801
1802static struct cpsw2_ts_attribute cpsw_pts_uni_attribute =
1803 __CPSW2_TS_ATTR(uni_en, S_IRUGO | S_IWUSR,
1804 cpsw2_port_ts_uni_show,
1805 cpsw2_port_ts_uni_store);
1806
1807static ssize_t cpsw2_port_ts_maddr_show(struct cpsw2_priv *cpsw_dev,
1808 struct cpsw2_ts_attribute *attr, char *buf, void *context)
1809{
1810 struct cpsw2_slave *slave;
1811 int len, port;
1812 u32 reg;
1813
1814 port = (int)context;
1815
1816 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1817 if (!slave)
1818 return 0;
1819
1820 reg = readl(&slave->regs->ts_ctl_ltype2);
1821 len = snprintf(buf, PAGE_SIZE, "%02x\n",
1822 (reg >> CPSW2_TS_CTL_MADDR_SHIFT) & 0x1f);
1823 return len;
1824}
1825
1826static ssize_t cpsw2_port_ts_maddr_store(struct cpsw2_priv *cpsw_dev,
1827 struct cpsw2_ts_attribute *attr,
1828 const char *buf, size_t count, void *context)
1829{
1830 struct cpsw2_slave *slave;
1831 int port;
1832 u32 reg;
1833 u8 val;
1834
1835 port = (int)context;
1836
1837 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1838 if (!slave)
1839 return 0;
1840
1841 if (kstrtou8(buf, 0, &val) < 0)
1842 return -EINVAL;
1843
1844 reg = readl(&slave->regs->ts_ctl_ltype2);
1845 reg &= ~CPSW2_TS_CTL_MADDR_ALL;
1846 reg |= ((val & 0x1f) << CPSW2_TS_CTL_MADDR_SHIFT);
1847 writel(reg, &slave->regs->ts_ctl_ltype2);
1848
1849 slave->ts_ctl.maddr_map = val & 0x1f;
1850 return count;
1851}
1852
1853static struct cpsw2_ts_attribute cpsw_pts_maddr_attribute =
1854 __CPSW2_TS_ATTR(mcast_addr, S_IRUGO | S_IWUSR,
1855 cpsw2_port_ts_maddr_show,
1856 cpsw2_port_ts_maddr_store);
1857
1858static ssize_t cpsw2_port_ts_dst_port_show(struct cpsw2_priv *cpsw_dev,
1859 struct cpsw2_ts_attribute *attr, char *buf, void *context)
1860{
1861 struct cpsw2_slave *slave;
1862 int len, port;
1863 u32 reg;
1864
1865 port = (int)context;
1866
1867 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1868 if (!slave)
1869 return 0;
1870
1871 reg = readl(&slave->regs->ts_ctl_ltype2);
1872 len = snprintf(buf, PAGE_SIZE, "%01x\n",
1873 (reg >> CPSW2_TS_CTL_DST_PORT_SHIFT) & 0x3);
1874 return len;
1875}
1876
1877static ssize_t cpsw2_port_ts_dst_port_store(struct cpsw2_priv *cpsw_dev,
1878 struct cpsw2_ts_attribute *attr,
1879 const char *buf, size_t count, void *context)
1880{
1881 struct cpsw2_slave *slave;
1882 int port;
1883 u32 reg;
1884 u8 val;
1885
1886 port = (int)context;
1887
1888 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1889 if (!slave)
1890 return 0;
1891
1892 if (kstrtou8(buf, 0, &val) < 0)
1893 return -EINVAL;
1894
1895 reg = readl(&slave->regs->ts_ctl_ltype2);
1896 reg &= ~CPSW2_TS_CTL_DST_PORT;
1897 reg |= ((val & 0x3) << CPSW2_TS_CTL_DST_PORT_SHIFT);
1898 writel(reg, &slave->regs->ts_ctl_ltype2);
1899
1900 slave->ts_ctl.dst_port_map = val & 0x3;
1901 return count;
1902}
1903
1904static struct cpsw2_ts_attribute cpsw_pts_dst_port_attribute =
1905 __CPSW2_TS_ATTR(dst_port, S_IRUGO | S_IWUSR,
1906 cpsw2_port_ts_dst_port_show,
1907 cpsw2_port_ts_dst_port_store);
1908
1909static ssize_t cpsw2_port_ts_config_show(struct cpsw2_priv *cpsw_dev,
1910 struct cpsw2_ts_attribute *attr, char *buf, void *context)
1911{
1912 struct cpsw2_slave *slave;
1913 int len, port, total_len = 0;
1914 u32 reg;
1915 char *p = buf;
1916
1917 port = (int)context;
1918
1919 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1920 if (!slave)
1921 return 0;
1922
1923 reg = readl(&slave->regs->ts_ctl);
1924 len = snprintf(p, PAGE_SIZE, "%08x ", reg);
1925 p += len;
1926 total_len += len;
1927
1928 reg = readl(&slave->regs->ts_seq_ltype);
1929 len = snprintf(p, PAGE_SIZE, "%08x ", reg);
1930 p += len;
1931 total_len += len;
1932
1933 reg = readl(&slave->regs->ts_vlan_ltype);
1934 len = snprintf(p, PAGE_SIZE, "%08x ", reg);
1935 p += len;
1936 total_len += len;
1937
1938 reg = readl(&slave->regs->ts_ctl_ltype2);
1939 len = snprintf(p, PAGE_SIZE, "%08x ", reg);
1940 p += len;
1941 total_len += len;
1942
1943 reg = readl(&slave->regs->ts_ctl2);
1944 len = snprintf(p, PAGE_SIZE, "%08x\n", reg);
1945 p += len;
1946 total_len += len;
1947
1948 return total_len;
1949}
1950
1951static ssize_t cpsw2_port_ts_config_store(struct cpsw2_priv *cpsw_dev,
1952 struct cpsw2_ts_attribute *attr,
1953 const char *buf, size_t count, void *context)
1954{
1955 struct cpsw2_slave *slave;
1956 unsigned long reg, val;
1957 int len, port;
1958 char tmp_str[4];
1959 u8 reg_num = 0;
1960 u32 __iomem *p;
1961
1962 port = (int)context;
1963
1964 slave = cpsw2_port_num_get_slave(cpsw_dev, port);
1965 if (!slave)
1966 return 0;
1967
1968 len = strcspn(buf, " ");
1969 if (len > 1)
1970 return -ENOMEM;
1971
1972 strncpy(tmp_str, buf, len);
1973 tmp_str[len] = '\0';
1974 if (kstrtou8(tmp_str, 0, &reg_num))
1975 return -EINVAL;
1976
1977 buf += (len + 1);
1978 if (kstrtoul(buf, 0, &val))
1979 return -EINVAL;
1980
1981 switch (reg_num) {
1982 case 1:
1983 p = &slave->regs->ts_ctl;
1984 break;
1985 case 2:
1986 p = &slave->regs->ts_seq_ltype;
1987 break;
1988 case 3:
1989 p = &slave->regs->ts_vlan_ltype;
1990 break;
1991 case 4:
1992 p = &slave->regs->ts_ctl_ltype2;
1993 break;
1994 case 5:
1995 p = &slave->regs->ts_ctl2;
1996 break;
1997 default:
1998 return -EINVAL;
1999 }
2000
2001 reg = readl(p);
2002 if (reg != val)
2003 writel(val, p);
2004
2005 return count;
2006}
2007
2008static struct cpsw2_ts_attribute cpsw_pts_config_attribute =
2009 __CPSW2_TS_ATTR(config, S_IRUGO | S_IWUSR,
2010 cpsw2_port_ts_config_show,
2011 cpsw2_port_ts_config_store);
2012
2013static struct attribute *cpsw_pts_n_default_attrs[] = {
2014 &cpsw_pts_uni_attribute.attr,
2015 &cpsw_pts_maddr_attribute.attr,
2016 &cpsw_pts_dst_port_attribute.attr,
2017 &cpsw_pts_config_attribute.attr,
2018 NULL
2019};
2020
2021static struct cpsw2_priv *cpsw2_port_ts_kobj_to_priv(struct kobject *kobj,
2022 int *port)
2023{
2024 char *port_name[] = {"1", "2", "3", "4", "5", "6", "7", "8", NULL};
2025 struct cpsw2_priv *cpsw_dev;
2026 struct kobject *kobj_0;
2027 int i = 0;
2028
2029 *port = -1;
2030
2031 while (i < MAX_SLAVES && port_name[i]) {
2032 if (strncmp(port_name[i], kobject_name(kobj), 1) == 0)
2033 *port = i+1;
2034 i++;
2035 }
2036
2037 if (*port < 0)
2038 return NULL;
2039
2040 kobj_0 = kobj - (*port - 1);
2041 cpsw_dev = pts_n_to_cpsw2_dev(kobj_0, 0);
2042 return cpsw_dev;
2043}
2044
2045static ssize_t cpsw2_pts_n_attr_show(struct kobject *kobj,
2046 struct attribute *attr, char *buf)
2047{
2048 struct cpsw2_ts_attribute *attribute = to_cpsw2_ts_attr(attr);
2049 struct cpsw2_priv *cpsw_dev;
2050 int port = -1;
2051
2052 if (!attribute->show)
2053 return -EIO;
2054
2055 cpsw_dev = cpsw2_port_ts_kobj_to_priv(kobj, &port);
2056 if (!cpsw_dev)
2057 return -EIO;
2058
2059 return attribute->show(cpsw_dev, attribute, buf, (void *)port);
2060}
2061
2062static ssize_t cpsw2_pts_n_attr_store(struct kobject *kobj,
2063 struct attribute *attr, const char *buf, size_t count)
2064{
2065 struct cpsw2_ts_attribute *attribute = to_cpsw2_ts_attr(attr);
2066 struct cpsw2_priv *cpsw_dev;
2067 int port = -1;
2068
2069 if (!attribute->store)
2070 return -EIO;
2071
2072 cpsw_dev = cpsw2_port_ts_kobj_to_priv(kobj, &port);
2073 if (!cpsw_dev)
2074 return -EIO;
2075
2076 return attribute->store(cpsw_dev, attribute, buf, count, (void *)port);
2077}
2078
2079static const struct sysfs_ops cpsw_pts_n_sysfs_ops = {
2080 .show = cpsw2_pts_n_attr_show,
2081 .store = cpsw2_pts_n_attr_store,
2082};
2083
2084static struct kobj_type cpsw_pts_n_ktype = {
2085 .sysfs_ops = &cpsw_pts_n_sysfs_ops,
2086 .default_attrs = cpsw_pts_n_default_attrs,
2087};
2088
2089static void cpsw2_reset_mod_stats(struct cpsw2_priv *cpsw_dev, int stat_mod)
2090{
2091 void __iomem *base = cpsw_dev->hw_stats_regs[stat_mod];
2092 u32 __iomem *p;
2093 int i;
2094
2095 for (i = 0; i < ETHTOOL_STATS_NUM(cpsw_dev->num_slaves + 1); i++) {
2096 if (et_stats[i].type == stat_mod) {
2097 cpsw_dev->hw_stats[i] = 0;
2098 p = base + et_stats[i].offset;
2099 *p = 0xffffffff;
2100 }
2101 }
2102 return;
2103}
2104
2105static ssize_t cpsw2_stats_mod_store(struct cpsw2_priv *cpsw_dev,
2106 struct cpsw2_attribute *attr,
2107 const char *buf, size_t count)
2108{
2109 unsigned long end;
2110 int stat_mod;
2111
2112 if (kstrtoul(buf, 0, &end) != 0 || (end != 0))
2113 return -EINVAL;
2114
2115 stat_mod = (int)(attr->context);
2116 spin_lock_bh(&cpsw_dev->hw_stats_lock);
2117 cpsw2_reset_mod_stats(cpsw_dev, stat_mod);
2118 spin_unlock_bh(&cpsw_dev->hw_stats_lock);
2119 return count;
2120}
2121
2122static struct cpsw2_attribute cpsw_stats_0_attribute =
2123 __CPSW2_ATTR_FULL(0, S_IWUSR, NULL, cpsw2_stats_mod_store,
2124 NULL, 0, (void *)CPSW2_STATS0_MODULE);
2125
2126static struct cpsw2_attribute cpsw_stats_1_attribute =
2127 __CPSW2_ATTR_FULL(1, S_IWUSR, NULL, cpsw2_stats_mod_store,
2128 NULL, 0, (void *)CPSW2_STATS1_MODULE);
2129
2130static struct cpsw2_attribute cpsw_stats_2_attribute =
2131 __CPSW2_ATTR_FULL(2, S_IWUSR, NULL, cpsw2_stats_mod_store,
2132 NULL, 0, (void *)CPSW2_STATS2_MODULE);
2133
2134static struct cpsw2_attribute cpsw_stats_3_attribute =
2135 __CPSW2_ATTR_FULL(3, S_IWUSR, NULL, cpsw2_stats_mod_store,
2136 NULL, 0, (void *)CPSW2_STATS3_MODULE);
2137
2138static struct cpsw2_attribute cpsw_stats_4_attribute =
2139 __CPSW2_ATTR_FULL(4, S_IWUSR, NULL, cpsw2_stats_mod_store,
2140 NULL, 0, (void *)CPSW2_STATS4_MODULE);
2141
2142static struct cpsw2_attribute cpsw_stats_5_attribute =
2143 __CPSW2_ATTR_FULL(5, S_IWUSR, NULL, cpsw2_stats_mod_store,
2144 NULL, 0, (void *)CPSW2_STATS5_MODULE);
2145
2146static struct cpsw2_attribute cpsw_stats_6_attribute =
2147 __CPSW2_ATTR_FULL(6, S_IWUSR, NULL, cpsw2_stats_mod_store,
2148 NULL, 0, (void *)CPSW2_STATS6_MODULE);
2149
2150static struct cpsw2_attribute cpsw_stats_7_attribute =
2151 __CPSW2_ATTR_FULL(7, S_IWUSR, NULL, cpsw2_stats_mod_store,
2152 NULL, 0, (void *)CPSW2_STATS7_MODULE);
2153
2154static struct cpsw2_attribute cpsw_stats_8_attribute =
2155 __CPSW2_ATTR_FULL(8, S_IWUSR, NULL, cpsw2_stats_mod_store,
2156 NULL, 0, (void *)CPSW2_STATS8_MODULE);
2157
2158static struct attribute *cpsw_stats_default_attrs[] = {
2159 &cpsw_stats_0_attribute.attr,
2160 &cpsw_stats_1_attribute.attr,
2161 &cpsw_stats_2_attribute.attr,
2162 &cpsw_stats_3_attribute.attr,
2163 &cpsw_stats_4_attribute.attr,
2164 &cpsw_stats_5_attribute.attr,
2165 &cpsw_stats_6_attribute.attr,
2166 &cpsw_stats_7_attribute.attr,
2167 &cpsw_stats_8_attribute.attr,
2168 NULL
2169};
2170
2171static ssize_t cpsw2_stats_attr_store(struct kobject *kobj,
2172 struct attribute *attr, const char *buf, size_t count)
2173{
2174 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
2175 struct cpsw2_priv *cpsw_dev = stats_to_cpsw2_dev(kobj);
2176
2177 if (!attribute->store)
2178 return -EIO;
2179
2180 return attribute->store(cpsw_dev, attribute, buf, count);
2181}
2182
2183static const struct sysfs_ops cpsw_stats_sysfs_ops = {
2184 .store = cpsw2_stats_attr_store,
2185};
2186
2187static struct kobj_type cpsw_stats_ktype = {
2188 .sysfs_ops = &cpsw_stats_sysfs_ops,
2189 .default_attrs = cpsw_stats_default_attrs,
2190};
2191
2192static struct attribute *cpsw_default_attrs[] = {
2193 &cpsw_version_attribute.attr,
2194 &cpsw_control_attribute.attr,
2195 &cpsw_pri_type_attribute.attr,
2196 NULL
2197};
2198
2199static ssize_t cpsw2_attr_show(struct kobject *kobj, struct attribute *attr,
2200 char *buf)
2201{
2202 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
2203 struct cpsw2_priv *cpsw_dev = to_cpsw2_dev(kobj);
2204
2205 if (!attribute->show)
2206 return -EIO;
2207
2208 return attribute->show(cpsw_dev, attribute, buf);
2209}
2210
2211static ssize_t cpsw2_attr_store(struct kobject *kobj, struct attribute *attr,
2212 const char *buf, size_t count)
2213{
2214 struct cpsw2_attribute *attribute = to_cpsw2_attr(attr);
2215 struct cpsw2_priv *cpsw_dev = to_cpsw2_dev(kobj);
2216
2217 if (!attribute->store)
2218 return -EIO;
2219
2220 return attribute->store(cpsw_dev, attribute, buf, count);
2221}
2222
2223static const struct sysfs_ops cpsw_sysfs_ops = {
2224 .show = cpsw2_attr_show,
2225 .store = cpsw2_attr_store,
2226};
2227
2228static struct kobj_type cpsw_ktype = {
2229 .sysfs_ops = &cpsw_sysfs_ops,
2230 .default_attrs = cpsw_default_attrs,
2231};
2232
2233static void keystone_get_drvinfo2(struct net_device *ndev,
2234 struct ethtool_drvinfo *info)
2235{
2236 strncpy(info->driver, NETCP2_DRIVER_NAME, sizeof(info->driver));
2237 strncpy(info->version, NETCP2_DRIVER_VERSION, sizeof(info->version));
2238}
2239
2240static u32 keystone_get_msglevel2(struct net_device *ndev)
2241{
2242 struct netcp_priv *netcp = netdev_priv(ndev);
2243 return netcp->msg_enable;
2244}
2245
2246static void keystone_set_msglevel2(struct net_device *ndev, u32 value)
2247{
2248 struct netcp_priv *netcp = netdev_priv(ndev);
2249 netcp->msg_enable = value;
2250}
2251
2252static void keystone_get_stat_strings2(struct net_device *ndev,
2253 uint32_t stringset, uint8_t *data)
2254{
2255 struct netcp_priv *netcp = netdev_priv(ndev);
2256 struct netcp_device *netcp_device = netcp->netcp_device;
2257 struct cpsw2_priv *priv;
2258 int i;
2259
2260 /* find the instance of the module registered to the netcp_device */
2261 priv = (struct cpsw2_priv *)netcp_device_find_module(netcp_device,
2262 CPSW2_MODULE_NAME);
2263
2264 switch (stringset) {
2265 case ETH_SS_STATS:
2266 for (i = 0; i < ETHTOOL_STATS_NUM(priv->num_slaves + 1); i++) {
2267 memcpy(data, et_stats[i].desc, ETH_GSTRING_LEN);
2268 data += ETH_GSTRING_LEN;
2269 }
2270 break;
2271 case ETH_SS_TEST:
2272 break;
2273 }
2274}
2275
2276static int keystone_get_sset_count2(struct net_device *ndev, int stringset)
2277{
2278 struct netcp_priv *netcp = netdev_priv(ndev);
2279 struct netcp_device *netcp_device = netcp->netcp_device;
2280 struct cpsw2_priv *priv;
2281
2282 /* find the instance of the module registered to the netcp_device */
2283 priv = (struct cpsw2_priv *)netcp_device_find_module(netcp_device,
2284 CPSW2_MODULE_NAME);
2285 switch (stringset) {
2286 case ETH_SS_TEST:
2287 return 0;
2288 case ETH_SS_STATS:
2289 return ETHTOOL_STATS_NUM(priv->num_slaves + 1);
2290 default:
2291 return -EINVAL;
2292 }
2293}
2294
2295static void cpsw2_update_stats(struct cpsw2_priv *cpsw_dev, uint64_t *data)
2296{
2297 void __iomem *base = NULL;
2298 u32 __iomem *p;
2299 u32 tmp = 0;
2300 int i;
2301
2302 for (i = 0; i < ETHTOOL_STATS_NUM(cpsw_dev->num_slaves + 1); i++) {
2303 base = cpsw_dev->hw_stats_regs[et_stats[i].type];
2304 p = base + et_stats[i].offset;
2305 tmp = *p;
2306 cpsw_dev->hw_stats[i] = cpsw_dev->hw_stats[i] + tmp;
2307 if (data)
2308 data[i] = cpsw_dev->hw_stats[i];
2309 *p = tmp;
2310 }
2311
2312 return;
2313}
2314
2315static void keystone_get_ethtool_stats2(struct net_device *ndev,
2316 struct ethtool_stats *stats,
2317 uint64_t *data)
2318{
2319 struct netcp_priv *netcp = netdev_priv(ndev);
2320 struct netcp_device *netcp_device = netcp->netcp_device;
2321 struct cpsw2_priv *priv;
2322
2323 /* find the instance of the module registered to the netcp_device */
2324 priv = (struct cpsw2_priv *)netcp_device_find_module(netcp_device,
2325 CPSW2_MODULE_NAME);
2326 if (priv) {
2327 spin_lock_bh(&priv->hw_stats_lock);
2328 cpsw2_update_stats(priv, data);
2329 spin_unlock_bh(&priv->hw_stats_lock);
2330 }
2331
2332 return;
2333}
2334
2335static int keystone_get_settings2(struct net_device *ndev,
2336 struct ethtool_cmd *cmd)
2337{
2338 struct phy_device *phy = ndev->phydev;
2339 struct cpsw2_slave *slave;
2340 int ret;
2341
2342 if (!phy)
2343 return -EINVAL;
2344
2345 slave = (struct cpsw2_slave *)phy->context;
2346 if (!slave)
2347 return -EINVAL;
2348
2349 ret = phy_ethtool_gset(phy, cmd);
2350 if (!ret)
2351 cmd->port = slave->phy_port_t;
2352
2353 return ret;
2354}
2355
2356static int keystone_set_settings2(struct net_device *ndev,
2357 struct ethtool_cmd *cmd)
2358{
2359 struct phy_device *phy = ndev->phydev;
2360 struct cpsw2_slave *slave;
2361 u32 features = cmd->advertising & cmd->supported;
2362
2363 if (!phy)
2364 return -EINVAL;
2365
2366 slave = (struct cpsw2_slave *)phy->context;
2367 if (!slave)
2368 return -EINVAL;
2369
2370 if (cmd->port != slave->phy_port_t) {
2371 if ((cmd->port == PORT_TP) && !(features & ADVERTISED_TP))
2372 return -EINVAL;
2373
2374 if ((cmd->port == PORT_AUI) && !(features & ADVERTISED_AUI))
2375 return -EINVAL;
2376
2377 if ((cmd->port == PORT_BNC) && !(features & ADVERTISED_BNC))
2378 return -EINVAL;
2379
2380 if ((cmd->port == PORT_MII) && !(features & ADVERTISED_MII))
2381 return -EINVAL;
2382
2383 if ((cmd->port == PORT_FIBRE) && !(features & ADVERTISED_FIBRE))
2384 return -EINVAL;
2385 }
2386
2387 slave->phy_port_t = cmd->port;
2388
2389 return phy_ethtool_sset(phy, cmd);
2390}
2391
2392#ifdef CONFIG_TI_CPTS
2393static int keystone_get_ts_info2(struct net_device *ndev,
2394 struct ethtool_ts_info *info)
2395{
2396 struct netcp_priv *netcp = netdev_priv(ndev);
2397 struct netcp_device *netcp_device = netcp->netcp_device;
2398 struct cpsw2_priv *priv;
2399
2400 /* find the instance of the module registered to the netcp_device */
2401 priv = netcp_device_find_module(netcp_device, CPSW2_MODULE_NAME);
2402 if (!priv)
2403 return -EINVAL;
2404
2405 info->so_timestamping =
2406 SOF_TIMESTAMPING_TX_HARDWARE |
2407 SOF_TIMESTAMPING_TX_SOFTWARE |
2408 SOF_TIMESTAMPING_RX_HARDWARE |
2409 SOF_TIMESTAMPING_RX_SOFTWARE |
2410 SOF_TIMESTAMPING_SOFTWARE |
2411 SOF_TIMESTAMPING_RAW_HARDWARE;
2412 info->phc_index = priv->cpts.phc_index;
2413 info->tx_types =
2414 (1 << HWTSTAMP_TX_OFF) |
2415 (1 << HWTSTAMP_TX_ON);
2416 info->rx_filters =
2417 (1 << HWTSTAMP_FILTER_NONE) |
2418 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2419 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2420 return 0;
2421}
2422#else
2423static int keystone_get_ts_info2(struct net_device *ndev,
2424 struct ethtool_ts_info *info)
2425{
2426 info->so_timestamping =
2427 SOF_TIMESTAMPING_TX_SOFTWARE |
2428 SOF_TIMESTAMPING_RX_SOFTWARE |
2429 SOF_TIMESTAMPING_SOFTWARE;
2430 info->phc_index = -1;
2431 info->tx_types = 0;
2432 info->rx_filters = 0;
2433 return 0;
2434}
2435#endif
2436
2437static const struct ethtool_ops keystone_ethtool_ops = {
2438 .get_drvinfo = keystone_get_drvinfo2,
2439 .get_link = ethtool_op_get_link,
2440 .get_msglevel = keystone_get_msglevel2,
2441 .set_msglevel = keystone_set_msglevel2,
2442 .get_strings = keystone_get_stat_strings2,
2443 .get_sset_count = keystone_get_sset_count2,
2444 .get_ethtool_stats = keystone_get_ethtool_stats2,
2445 .get_settings = keystone_get_settings2,
2446 .set_settings = keystone_set_settings2,
2447 .get_ts_info = keystone_get_ts_info2,
2448};
2449
2450#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
2451 ((mac)[2] << 16) | ((mac)[3] << 24))
2452#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
2453
2454static void cpsw2_set_slave_mac(struct cpsw2_slave *slave,
2455 struct cpsw2_intf *cpsw_intf)
2456{
2457 struct net_device *ndev = cpsw_intf->ndev;
2458
2459 writel(mac_hi(ndev->dev_addr), &slave->regs->sa_hi);
2460 writel(mac_lo(ndev->dev_addr), &slave->regs->sa_lo);
2461}
2462
2463static inline int cpsw2_get_slave_port(struct cpsw2_priv *priv, u32 slave_num)
2464{
2465 if (priv->host_port == 0)
2466 return slave_num + 1;
2467 else
2468 return slave_num;
2469}
2470
2471static void _cpsw2_adjust_link(struct cpsw2_slave *slave, bool *link)
2472{
2473 struct phy_device *phy = slave->phy;
2474 u32 mac_control = 0;
2475 u32 slave_port;
2476
2477 if (!phy)
2478 return;
2479
2480 slave_port = slave->port_num;
2481
2482 if (phy->link) {
2483 mac_control = slave->mac_control;
2484 mac_control |= MACSL_ENABLE | MACSL_RX_ENABLE_EXT_CTL |
2485 MACSL_RX_ENABLE_CSF;
2486 /* enable forwarding */
2487 cpsw_ale_control_set(slave->ale, slave_port,
2488 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2489
2490 if (phy->duplex)
2491 mac_control |= BIT(0); /* FULLDUPLEXEN */
2492 else
2493 mac_control &= ~0x1;
2494
2495 *link = true;
2496 } else {
2497 mac_control = 0;
2498 /* disable forwarding */
2499 cpsw_ale_control_set(slave->ale, slave_port,
2500 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
2501 }
2502
2503 if (mac_control != slave->mac_control) {
2504 phy_print_status(phy);
2505 writel(mac_control, &slave->regs->mac_control);
2506 }
2507
2508 slave->mac_control = mac_control;
2509}
2510
2511static void cpsw2_adjust_link(struct net_device *n_dev, void *context)
2512{
2513 struct cpsw2_slave *slave = (struct cpsw2_slave *)context;
2514 struct netcp_priv *netcp = netdev_priv(n_dev);
2515 bool link = false;
2516
2517 _cpsw2_adjust_link(slave, &link);
2518
2519 if (link)
2520 netcp->link_state |= BIT(slave->slave_num);
2521 else
2522 netcp->link_state &= ~BIT(slave->slave_num);
2523}
2524
2525/*
2526 * Reset the the mac sliver
2527 * Soft reset is set and polled until clear, or until a timeout occurs
2528 */
2529static int cpsw2_port_reset(struct cpsw2_slave *slave)
2530{
2531 u32 i, v;
2532
2533 /* Set the soft reset bit */
2534 writel(SOFT_RESET, &slave->regs->soft_reset);
2535
2536 /* Wait for the bit to clear */
2537 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
2538 v = readl(&slave->regs->soft_reset);
2539 if ((v & SOFT_RESET_MASK) !=
2540 SOFT_RESET)
2541 return 0;
2542 }
2543
2544 /* Timeout on the reset */
2545 return GMACSL_RET_WARN_RESET_INCOMPLETE;
2546}
2547
2548/*
2549 * Configure the mac sliver
2550 */
2551static void cpsw2_port_config(struct cpsw2_slave *slave, int max_rx_len)
2552{
2553 if (max_rx_len > MAX_SIZE_STREAM_BUFFER)
2554 max_rx_len = MAX_SIZE_STREAM_BUFFER;
2555
2556 writel(max_rx_len, &slave->regs->rx_maxlen);
2557
2558 writel(MACSL_ENABLE | MACSL_RX_ENABLE_EXT_CTL | MACSL_RX_ENABLE_CSF,
2559 &slave->regs->mac_control);
2560}
2561
2562static void cpsw2_slave_stop(struct cpsw2_slave *slave, struct cpsw2_priv *priv)
2563{
2564 cpsw2_port_reset(slave);
2565
2566 if (!slave->phy)
2567 return;
2568
2569 phy_stop(slave->phy);
2570 phy_disconnect(slave->phy);
2571 slave->phy = NULL;
2572}
2573
2574static void cpsw2_slave_link(struct cpsw2_slave *slave,
2575 struct cpsw2_intf *cpsw_intf)
2576{
2577 struct netcp_priv *netcp = netdev_priv(cpsw_intf->ndev);
2578
2579 if (slave->link_interface == SGMII_LINK_MAC_PHY) {
2580 if (netcp->link_state)
2581 cpsw_intf->sgmii_link |= BIT(slave->slave_num);
2582 else
2583 cpsw_intf->sgmii_link &= ~BIT(slave->slave_num);
2584 }
2585}
2586
2587static void cpsw2_slave_open(struct cpsw2_slave *slave,
2588 struct cpsw2_intf *cpsw_intf)
2589{
2590 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2591 u32 slave_port;
2592
2593 keystone_sgmii_reset(SGMII2_BASE(slave->slave_num), slave->slave_num);
2594
2595 keystone_sgmii_config(SGMII2_BASE(slave->slave_num), slave->slave_num,
2596 slave->link_interface);
2597
2598 cpsw2_port_reset(slave);
2599
2600 cpsw2_port_config(slave, cpsw_dev->rx_packet_max);
2601
2602 cpsw2_set_slave_mac(slave, cpsw_intf);
2603
2604 slave->mac_control = MACSL_ENABLE | MACSL_RX_ENABLE_EXT_CTL |
2605 MACSL_RX_ENABLE_CSF;
2606
2607 /* this slave port here is 1 based */
2608 slave_port = cpsw2_get_slave_port(cpsw_dev, slave->slave_num);
2609
2610 /* hence port num here is also 1 based */
2611 slave->port_num = slave_port;
2612 slave->ale = cpsw_dev->ale;
2613
2614 /* enable forwarding */
2615 cpsw_ale_control_set(cpsw_dev->ale, slave_port,
2616 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2617
2618 cpsw_ale_add_mcast(cpsw_dev->ale, cpsw_intf->ndev->broadcast,
2619 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
2620
2621 if (slave->link_interface == SGMII_LINK_MAC_PHY) {
2622 slave->phy = of_phy_connect(cpsw_intf->ndev,
2623 cpsw_intf->phy_node,
2624 &cpsw2_adjust_link, 0,
2625 PHY_INTERFACE_MODE_SGMII,
2626 slave);
2627 if (IS_ERR_OR_NULL(slave->phy)) {
2628 dev_err(cpsw_dev->dev, "phy not found on slave %d\n",
2629 slave->slave_num);
2630 slave->phy = NULL;
2631 } else {
2632 dev_info(cpsw_dev->dev, "phy found: id is: 0x%s\n",
2633 dev_name(&slave->phy->dev));
2634 cpsw_intf->ndev->phydev = slave->phy;
2635 slave->phy_port_t = PORT_MII;
2636 phy_start(slave->phy);
2637 }
2638 }
2639}
2640
2641static void cpsw2_init_host_port(struct cpsw2_priv *priv,
2642 struct cpsw2_intf *cpsw_intf)
2643{
2644 int bypass_en = 1;
2645
2646 /* Max length register */
2647 writel(MAX_SIZE_STREAM_BUFFER,
2648 &priv->host_port_regs->rx_maxlen);
2649
2650 if (priv->ale_refcnt == 1)
2651 cpsw_ale_start(priv->ale);
2652
2653 if (!priv->multi_if)
2654 bypass_en = 0;
2655
2656 cpsw_ale_control_set(priv->ale, 0, ALE_BYPASS, bypass_en);
2657
2658 cpsw_ale_control_set(priv->ale, 0, ALE_NO_PORT_VLAN, 1);
2659
2660 cpsw_ale_control_set(priv->ale, priv->host_port,
2661 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
2662
2663 cpsw_ale_control_set(priv->ale, 0,
2664 ALE_PORT_UNKNOWN_VLAN_MEMBER_1R4,
2665 CPSW2_MASK_ALL_PORTS(priv->num_slaves + 1));
2666
2667 cpsw_ale_control_set(priv->ale, 0,
2668 ALE_PORT_UNKNOWN_MCAST_FLOOD_1R4,
2669 CPSW2_MASK_PHYS_PORTS(priv->num_slaves + 1));
2670
2671 cpsw_ale_control_set(priv->ale, 0,
2672 ALE_PORT_UNKNOWN_REG_MCAST_FLOOD_1R4,
2673 CPSW2_MASK_ALL_PORTS(priv->num_slaves + 1));
2674
2675 cpsw_ale_control_set(priv->ale, 0,
2676 ALE_PORT_UNTAGGED_EGRESS_1R4,
2677 CPSW2_MASK_ALL_PORTS(priv->num_slaves + 1));
2678}
2679
2680static void cpsw2_slave_init(struct cpsw2_slave *slave, struct cpsw2_priv *priv)
2681{
2682 void __iomem *regs = priv->ss_regs;
2683 int slave_num = slave->slave_num;
2684
2685 slave->regs = regs + priv->slave_reg_ofs +
2686 (CPSW2_SLAVE_REGS_SIZE * slave_num);
2687}
2688
2689static void cpsw2_add_mcast_addr(struct cpsw2_intf *cpsw_intf, u8 *addr)
2690{
2691 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2692 u16 vlan_id;
2693
2694 cpsw_ale_add_mcast(cpsw_dev->ale, addr,
2695 CPSW2_MASK_ALL_PORTS(cpsw_dev->num_slaves + 1), 0, 0,
2696 ALE_MCAST_FWD_2);
2697 for_each_set_bit(vlan_id, cpsw_intf->active_vlans, VLAN_N_VID) {
2698 cpsw_ale_add_mcast(cpsw_dev->ale, addr,
2699 CPSW2_MASK_ALL_PORTS(cpsw_dev->num_slaves + 1),
2700 ALE_VLAN, vlan_id, ALE_MCAST_FWD_2);
2701 }
2702}
2703
2704static void cpsw2_add_ucast_addr(struct cpsw2_intf *cpsw_intf, u8 *addr)
2705{
2706 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2707 u16 vlan_id;
2708
2709 cpsw_ale_add_ucast(cpsw_dev->ale, addr, cpsw_dev->host_port, 0, 0);
2710
2711 for_each_set_bit(vlan_id, cpsw_intf->active_vlans, VLAN_N_VID)
2712 cpsw_ale_add_ucast(cpsw_dev->ale, addr, cpsw_dev->host_port,
2713 ALE_VLAN, vlan_id);
2714}
2715
2716static void cpsw2_del_mcast_addr(struct cpsw2_intf *cpsw_intf, u8 *addr)
2717{
2718 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2719 u16 vlan_id;
2720
2721 cpsw_ale_del_mcast(cpsw_dev->ale, addr, 0, 0, 0);
2722
2723 for_each_set_bit(vlan_id, cpsw_intf->active_vlans, VLAN_N_VID) {
2724 cpsw_ale_del_mcast(cpsw_dev->ale, addr, 0, ALE_VLAN, vlan_id);
2725 }
2726}
2727
2728static void cpsw2_del_ucast_addr(struct cpsw2_intf *cpsw_intf, u8 *addr)
2729{
2730 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2731 u16 vlan_id;
2732
2733 cpsw_ale_del_ucast(cpsw_dev->ale, addr, cpsw_dev->host_port, 0, 0);
2734
2735 for_each_set_bit(vlan_id, cpsw_intf->active_vlans, VLAN_N_VID) {
2736 cpsw_ale_del_ucast(cpsw_dev->ale, addr, cpsw_dev->host_port,
2737 ALE_VLAN, vlan_id);
2738 }
2739}
2740
2741static int cpsw2_add_addr(void *intf_priv, struct netcp_addr *naddr)
2742{
2743 struct cpsw2_intf *cpsw_intf = intf_priv;
2744 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2745
2746 dev_dbg(cpsw_dev->dev, "ethss adding address %pM, type %d\n",
2747 naddr->addr, naddr->type);
2748
2749 switch (naddr->type) {
2750 case ADDR_MCAST:
2751 case ADDR_BCAST:
2752 cpsw2_add_mcast_addr(cpsw_intf, naddr->addr);
2753 break;
2754 case ADDR_UCAST:
2755 case ADDR_DEV:
2756 cpsw2_add_ucast_addr(cpsw_intf, naddr->addr);
2757 break;
2758 case ADDR_ANY:
2759 /* nothing to do for promiscuous */
2760 default:
2761 break;
2762 }
2763
2764 return 0;
2765}
2766
2767static int cpsw2_del_addr(void *intf_priv, struct netcp_addr *naddr)
2768{
2769 struct cpsw2_intf *cpsw_intf = intf_priv;
2770 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2771
2772 dev_dbg(cpsw_dev->dev, "ethss deleting address %pM, type %d\n",
2773 naddr->addr, naddr->type);
2774
2775 switch (naddr->type) {
2776 case ADDR_MCAST:
2777 case ADDR_BCAST:
2778 cpsw2_del_mcast_addr(cpsw_intf, naddr->addr);
2779 break;
2780 case ADDR_UCAST:
2781 case ADDR_DEV:
2782 cpsw2_del_ucast_addr(cpsw_intf, naddr->addr);
2783 break;
2784 case ADDR_ANY:
2785 /* nothing to do for promiscuous */
2786 default:
2787 break;
2788 }
2789
2790 return 0;
2791}
2792
2793static int cpsw2_add_vid(void *intf_priv, int vid)
2794{
2795 struct cpsw2_intf *cpsw_intf = intf_priv;
2796 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2797
2798 set_bit(vid, cpsw_intf->active_vlans);
2799
2800 cpsw_ale_add_vlan(cpsw_dev->ale, vid,
2801 CPSW2_MASK_ALL_PORTS(cpsw_dev->num_slaves + 1),
2802 CPSW2_MASK_NO_PORTS,
2803 CPSW2_MASK_ALL_PORTS(cpsw_dev->num_slaves + 1),
2804 CPSW2_MASK_PHYS_PORTS(cpsw_dev->num_slaves + 1));
2805
2806 return 0;
2807}
2808
2809static int cpsw2_del_vid(void *intf_priv, int vid)
2810{
2811 struct cpsw2_intf *cpsw_intf = intf_priv;
2812 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
2813
2814 cpsw_ale_del_vlan(cpsw_dev->ale, vid, 0);
2815
2816 clear_bit(vid, cpsw_intf->active_vlans);
2817
2818 return 0;
2819}
2820
2821#ifdef CONFIG_TI_CPTS
2822#define KEYSTONE_PTP_FILTER2 \
2823{ \
2824 {OP_LDH, 0, 0, OFF_ETYPE }, /* */ \
2825/*ip4*/ {OP_JEQ, 0, 12, ETH_P_IP }, /* f goto ip6 */ \
2826 {OP_LDB, 0, 0, OFF_PROTO4 }, /* */ \
2827 {OP_JEQ, 0, 9, IPPROTO_UDP }, /* */ \
2828 {OP_LDH, 0, 0, OFF_FRAG }, /* */ \
2829 {OP_JSET, 7, 0, 0x1fff }, /* */ \
2830 {OP_LDX, 0, 0, OFF_IHL }, /* */ \
2831 {OP_LDHI, 0, 0, RELOFF_DST4 }, /* */ \
2832 {OP_JEQ, 0, 4, PTP_EV_PORT }, /* */ \
2833 {OP_LDHI, 0, 0, ETH_HLEN + UDP_HLEN }, /* */ \
2834 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2835 {OP_OR, 0, 0, PTP_CLASS_IPV4 }, /* */ \
2836 {OP_RETA, 0, 0, 0 }, /* */ \
2837 {OP_RETK, 0, 0, PTP_CLASS_NONE }, /* */ \
2838/*ip6*/ {OP_JEQ, 0, 9, ETH_P_IPV6 }, /* f goto v */ \
2839 {OP_LDB, 0, 0, ETH_HLEN + OFF_NEXT }, /* */ \
2840 {OP_JEQ, 0, 6, IPPROTO_UDP }, /* */ \
2841 {OP_LDH, 0, 0, OFF_DST6 }, /* */ \
2842 {OP_JEQ, 0, 4, PTP_EV_PORT }, /* */ \
2843 {OP_LDH, 0, 0, OFF_PTP6 }, /* */ \
2844 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2845 {OP_OR, 0, 0, PTP_CLASS_IPV6 }, /* */ \
2846 {OP_RETA, 0, 0, 0 }, /* */ \
2847 {OP_RETK, 0, 0, PTP_CLASS_NONE }, /* */ \
2848/* v */ {OP_JEQ, 0, 32, ETH_P_8021Q }, /* f goto ptp */ \
2849 {OP_LDH, 0, 0, OFF_ETYPE + 4 }, /* */ \
2850/*vip4*/{OP_JEQ, 0, 12, ETH_P_IP }, /* f goto vip6 */ \
2851 {OP_LDB, 0, 0, OFF_PROTO4 + 4 }, /* */ \
2852 {OP_JEQ, 0, 9, IPPROTO_UDP }, /* */ \
2853 {OP_LDH, 0, 0, OFF_FRAG + 4 }, /* */ \
2854 {OP_JSET, 7, 0, 0x1fff }, /* */ \
2855 {OP_LDX, 0, 0, OFF_IHL + 4 }, /* */ \
2856 {OP_LDHI, 0, 0, RELOFF_DST4 + 4 }, /* */ \
2857 {OP_JEQ, 0, 4, PTP_EV_PORT }, /* */ \
2858 {OP_LDHI, 0, 0, ETH_HLEN + UDP_HLEN + 4 }, /* */ \
2859 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2860 {OP_OR, 0, 0, PTP_CLASS_VLAN_IPV4 }, /* */ \
2861 {OP_RETA, 0, 0, 0 }, /* */ \
2862 {OP_RETK, 0, 0, PTP_CLASS_NONE }, /* */ \
2863/*vip6*/{OP_JEQ, 0, 9, ETH_P_IPV6 }, /* f goto vptp */ \
2864 {OP_LDB, 0, 0, ETH_HLEN + OFF_NEXT + 4 }, /* */ \
2865 {OP_JEQ, 0, 6, IPPROTO_UDP }, /* */ \
2866 {OP_LDH, 0, 0, OFF_DST6 + 4 }, /* */ \
2867 {OP_JEQ, 0, 4, PTP_EV_PORT }, /* */ \
2868 {OP_LDH, 0, 0, OFF_PTP6 + 4 }, /* */ \
2869 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2870 {OP_OR, 0, 0, PTP_CLASS_VLAN_IPV6 }, /* */ \
2871 {OP_RETA, 0, 0, 0 }, /* */ \
2872 {OP_RETK, 0, 0, PTP_CLASS_NONE }, /* */ \
2873/*vptp*/{OP_JEQ, 0, 15, ETH_P_1588 }, /* */ \
2874 {OP_LDB, 0, 0, ETH_HLEN + VLAN_HLEN }, /* */ \
2875 {OP_AND, 0, 0, PTP_GEN_BIT }, /* */ \
2876 {OP_JEQ, 0, 12, 0 }, /* */ \
2877 {OP_LDH, 0, 0, ETH_HLEN + VLAN_HLEN }, /* */ \
2878 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2879 {OP_OR, 0, 0, PTP_CLASS_VLAN }, /* */ \
2880 {OP_RETA, 0, 0, 0 }, /* */ \
2881/*ptp*/ {OP_JEQ, 0, 7, ETH_P_1588 }, /* */ \
2882 {OP_LDB, 0, 0, ETH_HLEN }, /* */ \
2883 {OP_AND, 0, 0, PTP_GEN_BIT }, /* */ \
2884 {OP_JEQ, 0, 4, 0 }, /* */ \
2885 {OP_LDH, 0, 0, ETH_HLEN }, /* */ \
2886 {OP_AND, 0, 0, PTP_CLASS_VMASK }, /* */ \
2887 {OP_OR, 0, 0, PTP_CLASS_L2 }, /* */ \
2888 {OP_RETA, 0, 0, 0 }, /* */ \
2889 {OP_RETK, 0, 0, PTP_CLASS_NONE }, \
2890}
2891
2892static struct sock_filter phy_ptp_filter[] = {
2893 PTP_FILTER
2894};
2895
2896static struct sock_filter cpsw_ptp_filter[] = KEYSTONE_PTP_FILTER2;
2897
2898static void cpsw2_hwtstamp(struct cpsw2_intf *cpsw_intf)
2899{
2900 struct cpsw2_priv *priv = cpsw_intf->cpsw_priv;
2901 struct cpsw2_slave *slave = cpsw_intf->slaves;
2902 u32 ts_en, seq_id, ctl, i;
2903
2904 if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) {
2905 writel(0, &slave->regs->ts_ctl);
2906 return;
2907 }
2908
2909 seq_id = (30 << CPSW2_TS_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2910 ts_en = EVENT_MSG_BITS << CPSW2_TS_MSG_TYPE_EN_SHIFT;
2911 ctl = ETH_P_1588 | CPSW2_TS_TTL_NONZERO |
2912 (slave->ts_ctl.dst_port_map << CPSW2_TS_CTL_DST_PORT_SHIFT) |
2913 (slave->ts_ctl.uni ? CPSW2_TS_UNI_EN :
2914 slave->ts_ctl.maddr_map << CPSW2_TS_CTL_MADDR_SHIFT);
2915
2916 if (priv->cpts.tx_enable)
2917 ts_en |= (CPSW2_TS_TX_ANX_ALL_EN | CPSW2_TS_TX_VLAN_LT1_EN);
2918
2919 if (priv->cpts.rx_enable)
2920 ts_en |= (CPSW2_TS_RX_ANX_ALL_EN | CPSW2_TS_RX_VLAN_LT1_EN);
2921
2922 for (i = 0; i < cpsw_intf->num_slaves; i++, slave++) {
2923 writel(ts_en, &slave->regs->ts_ctl);
2924 writel(seq_id, &slave->regs->ts_seq_ltype);
2925 writel(ctl, &slave->regs->ts_ctl_ltype2);
2926 }
2927}
2928
2929static int cpsw2_hwtstamp_ioctl(struct cpsw2_intf *cpsw_intf, struct ifreq *ifr)
2930{
2931 struct cpsw2_priv *priv = cpsw_intf->cpsw_priv;
2932 struct cpts *cpts = &priv->cpts;
2933 struct hwtstamp_config cfg;
2934
2935 if (!cpts->reg)
2936 return -EOPNOTSUPP;
2937
2938 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2939 return -EFAULT;
2940
2941 /* reserved for future extensions */
2942 if (cfg.flags)
2943 return -EINVAL;
2944
2945 switch (cfg.tx_type) {
2946 case HWTSTAMP_TX_OFF:
2947 cpts->tx_enable = 0;
2948 break;
2949 case HWTSTAMP_TX_ON:
2950 cpts->tx_enable = 1;
2951 break;
2952 default:
2953 return -ERANGE;
2954 }
2955
2956 switch (cfg.rx_filter) {
2957 case HWTSTAMP_FILTER_NONE:
2958 cpts->rx_enable = 0;
2959 break;
2960 case HWTSTAMP_FILTER_ALL:
2961 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2962 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2963 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2964 cpts->rx_enable = 1;
2965 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2966 break;
2967 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2968 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2969 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2970 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2971 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2972 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2973 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2974 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2975 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2976 cpts->rx_enable = 1;
2977 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2978 break;
2979 default:
2980 return -ERANGE;
2981 }
2982
2983 cpsw2_hwtstamp(cpsw_intf);
2984
2985 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2986}
2987#else
2988static inline int cpsw2_hwtstamp_ioctl(struct cpsw2_intf *cpsw_intf,
2989 struct ifreq *ifr)
2990{
2991 return -EOPNOTSUPP;
2992}
2993#endif /*CONFIG_TI_CPTS*/
2994
2995static int cpsw2_ioctl(void *intf_priv, struct ifreq *req, int cmd)
2996{
2997 struct cpsw2_intf *cpsw_intf = intf_priv;
2998 struct cpsw2_slave *slave = cpsw_intf->slaves;
2999 struct phy_device *phy = slave->phy;
3000 int ret = -EOPNOTSUPP;
3001
3002 if (cpsw_intf->cpsw_priv->force_no_hwtstamp)
3003 return -EOPNOTSUPP;
3004
3005 if (phy)
3006 ret = phy_mii_ioctl(phy, req, cmd);
3007
3008 if ((cmd == SIOCSHWTSTAMP) && (ret == -EOPNOTSUPP))
3009 ret = cpsw2_hwtstamp_ioctl(cpsw_intf, req);
3010
3011 return ret;
3012}
3013
3014static void cpsw2_timer(unsigned long arg)
3015{
3016 struct cpsw2_intf *cpsw_intf = (struct cpsw2_intf *)arg;
3017 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3018 u32 sp = cpsw_intf->slave_port;
3019 u32 ns = cpsw_intf->num_slaves;
3020 u32 sgmii_link;
3021
3022 if (cpsw_dev->multi_if)
3023 sgmii_link = keystone_sgmii_get_port_link(SGMII2_BASE(sp), sp);
3024 else {
3025 /* Single interface mode. Link is up if any one slave
3026 * port is up. It assumes slave port always starts from
3027 * 0 and is consecutive.
3028 */
3029
3030 /* slave port (port > 2) status */
3031 sgmii_link = keystone_sgmii_link_status(SGMII2_BASE(2),
3032 max_t(u32, ns, 2) - 2);
3033
3034 sgmii_link <<= 2;
3035
3036 /* slave port 0, 1 status */
3037 sgmii_link |= keystone_sgmii_link_status(SGMII2_BASE(0),
3038 min_t(u32, ns, 2));
3039 }
3040 cpsw_intf->sgmii_link = sgmii_link;
3041
3042 for_each_slave(cpsw_intf, cpsw2_slave_link, cpsw_intf);
3043
3044 /* FIXME: Don't aggregate link statuses in multi-interface case */
3045 if (cpsw_intf->sgmii_link) {
3046 /* link ON */
3047 if (!netif_carrier_ok(cpsw_intf->ndev))
3048 netif_carrier_on(cpsw_intf->ndev);
3049 } else {
3050 /* link OFF */
3051 if (netif_carrier_ok(cpsw_intf->ndev))
3052 netif_carrier_off(cpsw_intf->ndev);
3053 }
3054
3055 spin_lock_bh(&cpsw_dev->hw_stats_lock);
3056 cpsw2_update_stats(cpsw_dev, NULL);
3057 spin_unlock_bh(&cpsw_dev->hw_stats_lock);
3058
3059 cpsw_intf->timer.expires = jiffies + (HZ/10);
3060 add_timer(&cpsw_intf->timer);
3061
3062 return;
3063}
3064
3065#ifdef CONFIG_TI_CPTS
3066#define PHY_TXTSTAMP(p) \
3067 (p->skb->dev && \
3068 p->skb->dev->phydev && \
3069 p->skb->dev->phydev->drv && \
3070 p->skb->dev->phydev->drv->txtstamp)
3071
3072#define PHY_RXTSTAMP(p) \
3073 (p->skb->dev && \
3074 p->skb->dev->phydev && \
3075 p->skb->dev->phydev->drv && \
3076 p->skb->dev->phydev->drv->rxtstamp)
3077
3078static bool phy_ptp_tstamp(const struct netcp_packet *p_info, bool is_tx)
3079{
3080 struct sk_buff *skb = p_info->skb;
3081 unsigned type = PTP_CLASS_NONE;
3082
3083 if (is_tx && likely(PHY_TXTSTAMP(p_info)))
3084 type = sk_run_filter(skb, phy_ptp_filter);
3085 else if (!is_tx && likely(PHY_RXTSTAMP(p_info)))
3086 type = sk_run_filter(skb, phy_ptp_filter);
3087 else
3088 return false;
3089
3090 switch (type) {
3091 case PTP_CLASS_V1_IPV4:
3092 case PTP_CLASS_V1_IPV6:
3093 case PTP_CLASS_V2_IPV4:
3094 case PTP_CLASS_V2_IPV6:
3095 case PTP_CLASS_V2_L2:
3096 case PTP_CLASS_V2_VLAN:
3097 return true;
3098 }
3099
3100 return false;
3101}
3102
3103static int cpsw2_txtstamp_complete(void *context, struct sk_buff *skb)
3104{
3105 struct cpsw2_intf *cpsw_intf = context;
3106 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3107
3108 return cpts_tx_timestamp(&cpsw_dev->cpts, skb);
3109}
3110
3111static bool cpsw2_cpts_txtstamp(struct cpsw2_intf *cpsw_intf,
3112 const struct netcp_packet *p_info)
3113{
3114 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3115 struct sk_buff *skb = p_info->skb;
3116 unsigned type = PTP_CLASS_NONE;
3117
3118 if (!cpsw_dev->cpts.tx_enable)
3119 return false;
3120
3121 type = sk_run_filter(skb, cpsw_dev->cpts.filter);
3122 switch (type) {
3123 case PTP_CLASS_V1_IPV4:
3124 case PTP_CLASS_V1_IPV6:
3125 case PTP_CLASS_V2_IPV4:
3126 case PTP_CLASS_V2_IPV6:
3127 case PTP_CLASS_V2_L2:
3128 case PTP_CLASS_V2_VLAN:
3129 case PTP_CLASS_V1_VLAN_IPV4:
3130 case PTP_CLASS_V2_VLAN_IPV4:
3131 case PTP_CLASS_V1_VLAN_IPV6:
3132 case PTP_CLASS_V2_VLAN_IPV6:
3133 return true;
3134 }
3135
3136 return false;
3137}
3138
3139static int cpsw2_mark_pkt_txtstamp(struct cpsw2_intf *cpsw_intf,
3140 struct netcp_packet *p_info)
3141{
3142 if (!(skb_shinfo(p_info->skb)->tx_flags & SKBTX_HW_TSTAMP))
3143 return 0;
3144
3145 if (phy_ptp_tstamp(p_info, true)) {
3146 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
3147 return 0;
3148 }
3149
3150 if (cpsw2_cpts_txtstamp(cpsw_intf, p_info)) {
3151 p_info->txtstamp_complete = cpsw2_txtstamp_complete;
3152 p_info->ts_context = (void *)cpsw_intf;
3153 skb_shinfo(p_info->skb)->tx_flags |= SKBTX_IN_PROGRESS;
3154 }
3155
3156 return 0;
3157}
3158
3159static int cpsw2_rxtstamp_complete(struct cpsw2_intf *cpsw_intf,
3160 struct netcp_packet *p_info)
3161{
3162 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3163
3164 if (p_info->rxtstamp_complete)
3165 return 0;
3166
3167 if (phy_ptp_tstamp(p_info, false)) {
3168 p_info->rxtstamp_complete = true;
3169 return 0;
3170 }
3171
3172 if (!cpts_rx_timestamp(&cpsw_dev->cpts, p_info->skb))
3173 p_info->rxtstamp_complete = true;
3174
3175 return 0;
3176}
3177
3178static inline void cpsw2_register_cpts(struct cpsw2_priv *cpsw_dev)
3179{
3180 if (!cpsw_dev->cpts.reg)
3181 return;
3182
3183 if (cpsw_dev->cpts_registered < 0)
3184 /* Should not happen */
3185 return;
3186
3187 if (cpsw_dev->cpts_registered > 0)
3188 goto done;
3189
3190 cpsw_dev->cpts.filter = cpsw_ptp_filter;
3191 cpsw_dev->cpts.filter_size = ARRAY_SIZE(cpsw_ptp_filter);
3192
3193 /* Let cpts calculate the mult and shift */
3194 if (cpts_register(cpsw_dev->dev, &cpsw_dev->cpts,
3195 cpsw_dev->cpts.cc.mult, cpsw_dev->cpts.cc.shift))
3196 dev_err(cpsw_dev->dev, "error registering cpts device\n");
3197
3198done:
3199 ++cpsw_dev->cpts_registered;
3200}
3201
3202static inline void cpsw2_unregister_cpts(struct cpsw2_priv *cpsw_dev)
3203{
3204 if (!cpsw_dev->cpts.reg)
3205 return;
3206
3207 if (cpsw_dev->cpts_registered <= 0)
3208 return;
3209
3210 --cpsw_dev->cpts_registered;
3211
3212 if (cpsw_dev->cpts_registered)
3213 return;
3214
3215 cpsw_dev->cpts.filter = 0;
3216 cpsw_dev->cpts.filter_size = 0;
3217 cpts_unregister(&cpsw_dev->cpts);
3218}
3219#else
3220static inline int cpsw2_mark_pkt_txtstamp(struct cpsw2_intf *cpsw_intf,
3221 struct netcp_packet *p_info)
3222{
3223 return 0;
3224}
3225
3226static inline int cpsw2_rxtstamp_complete(struct cpsw2_intf *cpsw_intf,
3227 struct netcp_packet *p_info)
3228{
3229 return 0;
3230}
3231
3232static inline void cpsw2_register_cpts(struct cpsw2_priv *cpsw_dev)
3233{
3234}
3235
3236static inline void cpsw2_unregister_cpts(struct cpsw2_priv *cpsw_dev)
3237{
3238}
3239#endif /* CONFIG_TI_CPTS */
3240
3241static int cpsw2_serdes_init(struct cpsw2_priv *cpsw_dev)
3242{
3243 int i, total_slaves, slaves;
3244 int ret = 0;
3245
3246 for (i = 0, total_slaves = cpsw_dev->num_slaves;
3247 i < cpsw_dev->num_serdes;
3248 i++, total_slaves -= cpsw_dev->serdes_lanes) {
3249 if (total_slaves <= 0)
3250 break;
3251
3252 if (total_slaves > cpsw_dev->serdes_lanes)
3253 slaves = cpsw_dev->serdes_lanes;
3254 else
3255 slaves = total_slaves;
3256
3257 serdes_reset(cpsw_dev->serdes_regs[i], slaves);
3258 ret = serdes_init(cpsw_dev->serdes_regs[i], &cpsw_dev->serdes,
3259 slaves);
3260 if (ret < 0) {
3261 dev_err(cpsw_dev->dev,
3262 "cpsw serdes initialization failed\n");
3263 break;
3264 }
3265 }
3266 return ret;
3267}
3268
3269static int cpsw2_tx_hook(int order, void *data, struct netcp_packet *p_info)
3270{
3271 struct cpsw2_intf *cpsw_intf = data;
3272
3273 p_info->tx_pipe = &cpsw_intf->tx_pipe;
3274
3275 return cpsw2_mark_pkt_txtstamp(cpsw_intf, p_info);
3276}
3277
3278static int cpsw2_rx_hook(int order, void *data, struct netcp_packet *p_info)
3279{
3280 struct cpsw2_intf *cpsw_intf = data;
3281
3282 return cpsw2_rxtstamp_complete(cpsw_intf, p_info);
3283}
3284
3285#define CPSW2_TXHOOK_ORDER 0
3286#define CPSW2_RXHOOK_ORDER 0
3287
3288static int cpsw2_open(void *intf_priv, struct net_device *ndev)
3289{
3290 struct cpsw2_intf *cpsw_intf = intf_priv;
3291 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3292 struct netcp_priv *netcp = netdev_priv(ndev);
3293 struct cpsw_ale_params ale_params;
3294 int ret = 0;
3295 u32 reg;
3296
3297 cpsw_dev->cpgmac = clk_get(cpsw_dev->dev, "clk_cpgmac");
3298 if (IS_ERR(cpsw_dev->cpgmac)) {
3299 ret = PTR_ERR(cpsw_dev->cpgmac);
3300 cpsw_dev->cpgmac = NULL;
3301 dev_err(cpsw_dev->dev, "unable to get Keystone CPGMAC"
3302 " clock: %d\n", ret);
3303 return ret;
3304 }
3305
3306 ret = clk_prepare_enable(cpsw_dev->cpgmac);
3307 if (ret)
3308 goto clk_fail;
3309
3310 reg = readl(&cpsw_dev->regs->id_ver);
3311
3312 dev_info(cpsw_dev->dev, "initializing cpsw version %d.%d (%d) "
3313 "SGMII identification value 0x%x\n",
3314 CPSW2_MAJOR_VERSION(reg), CPSW2_MINOR_VERSION(reg),
3315 CPSW2_RTL_VERSION(reg), CPSW2_SGMII_IDENT(reg));
3316
3317 ret = netcp_txpipe_open(&cpsw_intf->tx_pipe);
3318 if (ret)
3319 goto txpipe_fail;
3320
3321 dev_dbg(cpsw_dev->dev, "opened TX channel %s: %p with psflags %d\n",
3322 cpsw_intf->tx_pipe.dma_chan_name,
3323 cpsw_intf->tx_pipe.dma_channel,
3324 cpsw_intf->tx_pipe.dma_psflags);
3325
3326 cpsw_dev->ale_refcnt++;
3327 if (cpsw_dev->ale_refcnt == 1) {
3328 memset(&ale_params, 0, sizeof(ale_params));
3329
3330 ale_params.dev = cpsw_dev->dev;
3331 ale_params.ale_regs = (void *)\
3332 ((u32)cpsw_dev->ale_reg);
3333 ale_params.ale_ageout = cpsw_dev->ale_ageout;
3334 ale_params.ale_entries = cpsw_dev->ale_entries;
3335 ale_params.ale_ports = cpsw_dev->ale_ports;
3336
3337 cpsw_dev->ale = cpsw_ale_create(&ale_params);
3338 if (!cpsw_dev->ale) {
3339 dev_err(cpsw_dev->dev,
3340 "error initializing ale engine\n");
3341 ret = -ENODEV;
3342 goto ale_fail;
3343 } else
3344 dev_info(cpsw_dev->dev, "Created a cpsw ale engine\n");
3345 }
3346
3347 for_each_slave(cpsw_intf, cpsw2_slave_init, cpsw_dev);
3348
3349 for_each_slave(cpsw_intf, cpsw2_slave_stop, cpsw_dev);
3350
3351 /* Serdes init */
3352 if (cpsw_dev->init_serdes_at_probe == 0)
3353 cpsw2_serdes_init(cpsw_dev);
3354
3355 /* initialize host and slave ports */
3356 cpsw2_init_host_port(cpsw_dev, cpsw_intf);
3357
3358 /* disable priority elevation and enable statistics on all ports */
3359 writel(0, &cpsw_dev->regs->ptype);
3360
3361 /* Control register */
3362 writel(CPSW2_CTL_P0_ENABLE, &cpsw_dev->regs->control);
3363
3364 /* All statistics enabled by default */
3365 writel(CPSW2_REG_VAL_STAT_ENABLE_ALL(cpsw_dev->num_slaves + 1),
3366 &cpsw_dev->regs->stat_port_en);
3367
3368 for_each_slave(cpsw_intf, cpsw2_slave_open, cpsw_intf);
3369
3370 init_timer(&cpsw_intf->timer);
3371 cpsw_intf->timer.data = (unsigned long)cpsw_intf;
3372 cpsw_intf->timer.function = cpsw2_timer;
3373 cpsw_intf->timer.expires = jiffies + CPSW2_TIMER_INTERVAL;
3374 add_timer(&cpsw_intf->timer);
3375 dev_dbg(cpsw_dev->dev, "%s(): cpsw2_timer = %p\n", __func__,
3376 cpsw2_timer);
3377
3378 netcp_register_txhook(netcp, CPSW2_TXHOOK_ORDER,
3379 cpsw2_tx_hook, cpsw_intf);
3380
3381 if (!cpsw_dev->force_no_hwtstamp)
3382 netcp_register_rxhook(netcp, CPSW2_RXHOOK_ORDER,
3383 cpsw2_rx_hook, cpsw_intf);
3384
3385 /* Configure the streaming switch */
3386#define PSTREAM_ROUTE_GLOBAL_DMA 0
3387 netcp_set_streaming_switch2(cpsw_dev->netcp_device, netcp->cpsw_port,
3388 PSTREAM_ROUTE_GLOBAL_DMA);
3389
3390 cpsw2_register_cpts(cpsw_dev);
3391 return 0;
3392
3393ale_fail:
3394 netcp_txpipe_close(&cpsw_intf->tx_pipe);
3395txpipe_fail:
3396 clk_disable_unprepare(cpsw_dev->cpgmac);
3397clk_fail:
3398 clk_put(cpsw_dev->cpgmac);
3399 cpsw_dev->cpgmac = NULL;
3400 return ret;
3401}
3402
3403static int cpsw2_close(void *intf_priv, struct net_device *ndev)
3404{
3405 struct cpsw2_intf *cpsw_intf = intf_priv;
3406 struct cpsw2_priv *cpsw_dev = cpsw_intf->cpsw_priv;
3407 struct netcp_priv *netcp = netdev_priv(ndev);
3408
3409 del_timer_sync(&cpsw_intf->timer);
3410
3411 cpsw_dev->ale_refcnt--;
3412 if (!cpsw_dev->ale_refcnt)
3413 cpsw_ale_stop(cpsw_dev->ale);
3414
3415 for_each_slave(cpsw_intf, cpsw2_slave_stop, cpsw_dev);
3416
3417 if (!cpsw_dev->force_no_hwtstamp)
3418 netcp_unregister_rxhook(netcp, CPSW2_RXHOOK_ORDER,
3419 cpsw2_rx_hook, cpsw_intf);
3420
3421 netcp_unregister_txhook(netcp, CPSW2_TXHOOK_ORDER, cpsw2_tx_hook,
3422 cpsw_intf);
3423 netcp_txpipe_close(&cpsw_intf->tx_pipe);
3424
3425 clk_disable_unprepare(cpsw_dev->cpgmac);
3426 clk_put(cpsw_dev->cpgmac);
3427
3428 cpsw2_unregister_cpts(cpsw_dev);
3429 return 0;
3430}
3431
3432static int cpsw2_remove(struct netcp_device *netcp_device, void *inst_priv)
3433{
3434 struct cpsw2_priv *cpsw_dev = inst_priv;
3435 struct cpsw2_intf *cpsw_intf, *tmp;
3436 int i;
3437
3438 of_node_put(cpsw_dev->interfaces);
3439
3440 cpsw_ale_destroy(cpsw_dev->ale);
3441
3442 list_for_each_entry_safe(cpsw_intf, tmp, &cpsw_dev->cpsw_intf_head,
3443 cpsw_intf_list) {
3444 netcp_delete_interface(netcp_device, cpsw_intf->ndev);
3445 }
3446 BUG_ON(!list_empty(&cpsw_dev->cpsw_intf_head));
3447
3448 iounmap(cpsw_dev->ss_regs);
3449 for (i = 0; i < cpsw_dev->num_serdes; i++)
3450 if (cpsw_dev->serdes_regs[i])
3451 iounmap(cpsw_dev->serdes_regs[i]);
3452 memset(cpsw_dev, 0x00, sizeof(*cpsw_dev)); /* FIXME: Poison */
3453 kfree(cpsw_dev);
3454 return 0;
3455}
3456
3457static int init_slave(struct cpsw2_priv *cpsw_dev,
3458 struct device_node *node, int slave_num)
3459{
3460 int ret = 0;
3461
3462 ret = of_property_read_u32(node, "link-interface",
3463 &cpsw_dev->link[slave_num]);
3464 if (ret < 0) {
3465 dev_err(cpsw_dev->dev,
3466 "missing link-interface value"
3467 "defaulting to mac-phy link\n");
3468 cpsw_dev->link[slave_num] = 1;
3469 }
3470
3471 cpsw_dev->phy_node[slave_num] = of_parse_phandle(node, "phy-handle", 0);
3472
3473 return 0;
3474}
3475
3476static int cpsw2_create_cpts_sysfs(struct cpsw2_priv *cpsw_dev)
3477{
3478 struct kobject *pts_kobj;
3479 char *port_name[] = {"1", "2", "3", "4", "5", "6", "7", "8", NULL};
3480 int i, ret;
3481
3482 pts_kobj = kobject_create_and_add("port_ts",
3483 kobject_get(&cpsw_dev->kobj));
3484 if (!pts_kobj) {
3485 dev_err(cpsw_dev->dev,
3486 "failed to create sysfs port_ts entry\n");
3487 kobject_put(&cpsw_dev->kobj);
3488 return -ENOMEM;
3489 }
3490
3491 for (i = 0; (i < cpsw_dev->num_slaves) && port_name[i]; i++) {
3492 ret = kobject_init_and_add(&cpsw_dev->port_ts_kobj[i],
3493 &cpsw_pts_n_ktype, kobject_get(pts_kobj), port_name[i]);
3494
3495 if (ret) {
3496 dev_err(cpsw_dev->dev,
3497 "failed to create sysfs port_ts/%s entry\n",
3498 port_name[i]);
3499 kobject_put(&cpsw_dev->port_ts_kobj[i]);
3500 kobject_put(pts_kobj);
3501 return ret;
3502 }
3503 }
3504
3505 return 0;
3506}
3507
3508static int cpsw2_create_sysfs_entries(struct cpsw2_priv *cpsw_dev)
3509{
3510 struct device *dev = cpsw_dev->dev;
3511 int ret;
3512
3513 ret = kobject_init_and_add(&cpsw_dev->kobj, &cpsw_ktype,
3514 kobject_get(&dev->kobj), "cpsw");
3515
3516 if (ret) {
3517 dev_err(dev, "failed to create cpsw sysfs entry\n");
3518 kobject_put(&cpsw_dev->kobj);
3519 kobject_put(&dev->kobj);
3520 return ret;
3521 }
3522
3523 ret = kobject_init_and_add(&cpsw_dev->tx_pri_kobj,
3524 &cpsw_tx_pri_ktype,
3525 kobject_get(&cpsw_dev->kobj), "port_tx_pri_map");
3526
3527 if (ret) {
3528 dev_err(dev, "failed to create sysfs port_tx_pri_map entry\n");
3529 kobject_put(&cpsw_dev->tx_pri_kobj);
3530 kobject_put(&cpsw_dev->kobj);
3531 return ret;
3532 }
3533
3534 ret = kobject_init_and_add(&cpsw_dev->pvlan_kobj,
3535 &cpsw_pvlan_ktype,
3536 kobject_get(&cpsw_dev->kobj), "port_vlan");
3537
3538 if (ret) {
3539 dev_err(dev, "failed to create sysfs port_vlan entry\n");
3540 kobject_put(&cpsw_dev->pvlan_kobj);
3541 kobject_put(&cpsw_dev->kobj);
3542 return ret;
3543 }
3544
3545 ret = cpsw2_create_cpts_sysfs(cpsw_dev);
3546 if (ret)
3547 return ret;
3548
3549 ret = kobject_init_and_add(&cpsw_dev->stats_kobj,
3550 &cpsw_stats_ktype,
3551 kobject_get(&cpsw_dev->kobj), "stats");
3552
3553 if (ret) {
3554 dev_err(dev, "failed to create sysfs stats entry\n");
3555 kobject_put(&cpsw_dev->stats_kobj);
3556 kobject_put(&cpsw_dev->kobj);
3557 return ret;
3558 }
3559
3560 return 0;
3561}
3562
3563static int cpsw2_probe(struct netcp_device *netcp_device,
3564 struct device *dev,
3565 struct device_node *node,
3566 void **inst_priv)
3567{
3568 struct cpsw2_priv *cpsw_dev;
3569 struct device_node *slaves, *slave, *interfaces;
3570 void __iomem *regs;
3571 struct net_device *ndev;
3572 int slave_num = 0;
3573 int i, ret = 0;
3574 u32 temp[CPSW2_SERDES_MAX_NUM * 2];
3575
3576 if (!node) {
3577 dev_err(dev, "device tree info unavailable\n");
3578 return -ENODEV;
3579 }
3580
3581 if (ptp_filter_init(phy_ptp_filter, ARRAY_SIZE(phy_ptp_filter))) {
3582 dev_err(dev, "bad ptp filter\n");
3583 return -EINVAL;
3584 }
3585
3586 cpsw_dev = devm_kzalloc(dev, sizeof(struct cpsw2_priv), GFP_KERNEL);
3587 if (!cpsw_dev) {
3588 dev_err(dev, "cpsw_dev memory allocation failed\n");
3589 return -ENOMEM;
3590 }
3591 *inst_priv = cpsw_dev;
3592 dev_dbg(dev, "%s(): cpsw_priv = %p\n", __func__, cpsw_dev);
3593
3594 cpsw_dev->dev = dev;
3595 cpsw_dev->netcp_device = netcp_device;
3596
3597 ret = of_property_read_u32(node, "num-serdes",
3598 &cpsw_dev->num_serdes);
3599 if (ret < 0) {
3600 dev_err(dev, "missing num-serdes parameter\n");
3601 cpsw_dev->num_serdes = CPSW2_SERDES_MAX_NUM;
3602 }
3603 if (cpsw_dev->num_serdes > CPSW2_SERDES_MAX_NUM) {
3604 dev_err(dev, "invalid num_serdes, should not be bigger than"
3605 " CPSW2_SERDES_MAX_NUM, reset the value to"
3606 " CPSW2_SERDES_MAX_NUM\n");
3607 cpsw_dev->num_serdes = CPSW2_SERDES_MAX_NUM;
3608 }
3609 dev_dbg(dev, "num-serdes %u\n", cpsw_dev->num_serdes);
3610
3611 ret = of_property_read_u32(node, "serdes-lanes",
3612 &cpsw_dev->serdes_lanes);
3613 if (ret < 0) {
3614 dev_err(dev, "missing serdes-lanes parameter\n");
3615 cpsw_dev->serdes_lanes = CPSW2_LANE_NUM_PER_SERDES;
3616 }
3617 dev_dbg(dev, "serdes-lanes %u\n", cpsw_dev->serdes_lanes);
3618
3619 if (of_property_read_u32_array(node, "serdes_reg", (u32 *)&(temp[0]),
3620 cpsw_dev->num_serdes * 2)) {
3621 dev_err(dev, "No serdes regs defined\n");
3622 ret = -ENODEV;
3623 goto exit;
3624 }
3625
3626 for (i = 0; i < cpsw_dev->num_serdes; i++) {
3627 cpsw_dev->serdes_regs[i] = ioremap(temp[i*2], temp[i*2+1]);
3628 if (!cpsw_dev->serdes_regs[i]) {
3629 dev_err(dev, "can't map serdes regs\n");
3630 ret = -ENOMEM;
3631 goto exit;
3632 }
3633 }
3634
3635 ret = of_property_read_u32(node, "serdes-ref-clk",
3636 &cpsw_dev->serdes.clk);
3637 if (ret < 0) {
3638 dev_err(dev, "missing serdes-ref-clk parameter\n");
3639 cpsw_dev->serdes.clk = SERDES_CLOCK_156P25M;
3640 }
3641 dev_dbg(dev, "serdes-ref-clk %u\n", cpsw_dev->serdes.clk);
3642
3643 ret = of_property_read_u32(node, "serdes-baud-rate",
3644 &cpsw_dev->serdes.rate);
3645 if (ret < 0) {
3646 dev_err(dev, "missing serdes-baud-rate parameter\n");
3647 cpsw_dev->serdes.rate = SERDES_RATE_5G;
3648 }
3649 dev_dbg(dev, "serdes-baud-rate %u\n", cpsw_dev->serdes.rate);
3650
3651 ret = of_property_read_u32(node, "serdes-rate-mode",
3652 &cpsw_dev->serdes.rate_mode);
3653 if (ret < 0) {
3654 dev_err(dev, "missing serdes-rate-mode parameter\n");
3655 cpsw_dev->serdes.rate_mode = SERDES_QUARTER_RATE;
3656 }
3657 dev_dbg(dev, "serdes-rate-mode %u\n", cpsw_dev->serdes.rate_mode);
3658
3659 ret = of_property_read_u32(node, "serdes-phy-intf",
3660 &cpsw_dev->serdes.intf);
3661