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author | Reece R. Pollack | 2014-12-18 14:24:44 -0600 |
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committer | Reece R. Pollack | 2014-12-18 14:24:44 -0600 |
commit | 47e64f77838bf773b4ed69e01cd4fcc35ec64ced (patch) | |
tree | cbecb5e7db2d67bab8ed4cdef545794138484eb3 /drivers | |
parent | 474793dd5f9ff9cdc9c740a50d09828d89093cc4 (diff) | |
parent | 80c06551db21ce96c1aac33990bcd63c9949c433 (diff) | |
download | linux-47e64f77838bf773b4ed69e01cd4fcc35ec64ced.tar.gz linux-47e64f77838bf773b4ed69e01cd4fcc35ec64ced.tar.xz linux-47e64f77838bf773b4ed69e01cd4fcc35ec64ced.zip |
Merge branch 'master/rebuild/24-drivers-net' into master/master
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/ethernet/ti/keystone_pa2.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/ethernet/ti/keystone_pa2.c b/drivers/net/ethernet/ti/keystone_pa2.c index aa92fc2f055..1fa2e4e3bfd 100644 --- a/drivers/net/ethernet/ti/keystone_pa2.c +++ b/drivers/net/ethernet/ti/keystone_pa2.c | |||
@@ -291,7 +291,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
291 | (Global address of Post cluster) */ | 291 | (Global address of Post cluster) */ |
292 | 0x00000000, /* C26: Reserved*/ | 292 | 0x00000000, /* C26: Reserved*/ |
293 | 0x00000000, /* C27: Reserved*/ | 293 | 0x00000000, /* C27: Reserved*/ |
294 | 0x00000000, /* C28: Reserved*/ | 294 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
295 | 0x00000000, /* C29: Reserved*/ | 295 | 0x00000000, /* C29: Reserved*/ |
296 | 0x00000000, /* C30: Reserved*/ | 296 | 0x00000000, /* C30: Reserved*/ |
297 | 0x00000000 /* C31: Reserved*/ | 297 | 0x00000000 /* C31: Reserved*/ |
@@ -327,7 +327,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
327 | (Global address of Post cluster) */ | 327 | (Global address of Post cluster) */ |
328 | 0x00000000, /* C26: Reserved*/ | 328 | 0x00000000, /* C26: Reserved*/ |
329 | 0x00000000, /* C27: Reserved*/ | 329 | 0x00000000, /* C27: Reserved*/ |
330 | 0x00000000, /* C28: Reserved*/ | 330 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
331 | 0x00000000, /* C29: Reserved*/ | 331 | 0x00000000, /* C29: Reserved*/ |
332 | 0x00000000, /* C30: Reserved*/ | 332 | 0x00000000, /* C30: Reserved*/ |
333 | 0x00000000 /* C31: Reserved*/ | 333 | 0x00000000 /* C31: Reserved*/ |
@@ -363,7 +363,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
363 | (Global address of Post cluster) */ | 363 | (Global address of Post cluster) */ |
364 | 0x00000000, /* C26: Reserved*/ | 364 | 0x00000000, /* C26: Reserved*/ |
365 | 0x00000000, /* C27: Reserved*/ | 365 | 0x00000000, /* C27: Reserved*/ |
366 | 0x00000000, /* C28: Reserved*/ | 366 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
367 | 0x00000000, /* C29: Reserved*/ | 367 | 0x00000000, /* C29: Reserved*/ |
368 | 0x00000000, /* C30: Reserved*/ | 368 | 0x00000000, /* C30: Reserved*/ |
369 | 0x00000000 /* C31: Reserved*/ | 369 | 0x00000000 /* C31: Reserved*/ |
@@ -399,7 +399,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
399 | (Global address of Post cluster) */ | 399 | (Global address of Post cluster) */ |
400 | 0x00000000, /* C26: Reserved*/ | 400 | 0x00000000, /* C26: Reserved*/ |
401 | 0x00000000, /* C27: Reserved*/ | 401 | 0x00000000, /* C27: Reserved*/ |
402 | 0x00000000, /* C28: Reserved*/ | 402 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
403 | 0x00000000, /* C29: Reserved*/ | 403 | 0x00000000, /* C29: Reserved*/ |
404 | 0x00000000, /* C30: Reserved*/ | 404 | 0x00000000, /* C30: Reserved*/ |
405 | 0x00000000 /* C31: Reserved*/ | 405 | 0x00000000 /* C31: Reserved*/ |
@@ -435,7 +435,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
435 | (Global address of Post cluster) */ | 435 | (Global address of Post cluster) */ |
436 | 0x00000000, /* C26: Reserved*/ | 436 | 0x00000000, /* C26: Reserved*/ |
437 | 0x00000000, /* C27: Reserved*/ | 437 | 0x00000000, /* C27: Reserved*/ |
438 | 0x00000000, /* C28: Reserved*/ | 438 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
439 | 0x00000000, /* C29: Reserved*/ | 439 | 0x00000000, /* C29: Reserved*/ |
440 | 0x00000000, /* C30: Reserved*/ | 440 | 0x00000000, /* C30: Reserved*/ |
441 | 0x00000000 /* C31: Reserved*/ | 441 | 0x00000000 /* C31: Reserved*/ |
@@ -471,7 +471,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
471 | (Global address of Post cluster) */ | 471 | (Global address of Post cluster) */ |
472 | 0x00000000, /* C26: Reserved*/ | 472 | 0x00000000, /* C26: Reserved*/ |
473 | 0x00000000, /* C27: Reserved*/ | 473 | 0x00000000, /* C27: Reserved*/ |
474 | 0x00000000, /* C28: Reserved*/ | 474 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
475 | 0x00000000, /* C29: Reserved*/ | 475 | 0x00000000, /* C29: Reserved*/ |
476 | 0x00000000, /* C30: Reserved*/ | 476 | 0x00000000, /* C30: Reserved*/ |
477 | 0x00000000 /* C31: Reserved*/ | 477 | 0x00000000 /* C31: Reserved*/ |
@@ -507,7 +507,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
507 | (Global address of Post Cluster) */ | 507 | (Global address of Post Cluster) */ |
508 | 0x00000000, /* C26: Reserved*/ | 508 | 0x00000000, /* C26: Reserved*/ |
509 | 0x00000000, /* C27: Reserved*/ | 509 | 0x00000000, /* C27: Reserved*/ |
510 | 0x00000000, /* C28: Reserved*/ | 510 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
511 | 0x00000000, /* C29: Reserved*/ | 511 | 0x00000000, /* C29: Reserved*/ |
512 | 0x00000000, /* C30: Reserved*/ | 512 | 0x00000000, /* C30: Reserved*/ |
513 | 0x00000000 /* C31: Reserved*/ | 513 | 0x00000000 /* C31: Reserved*/ |
@@ -543,7 +543,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
543 | (Global address of Post cluster) */ | 543 | (Global address of Post cluster) */ |
544 | 0x00000000, /* C26: Reserved*/ | 544 | 0x00000000, /* C26: Reserved*/ |
545 | 0x00000000, /* C27: Reserved*/ | 545 | 0x00000000, /* C27: Reserved*/ |
546 | 0x00000000, /* C28: Reserved*/ | 546 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
547 | 0x00000000, /* C29: Reserved*/ | 547 | 0x00000000, /* C29: Reserved*/ |
548 | 0x00000000, /* C30: Reserved*/ | 548 | 0x00000000, /* C30: Reserved*/ |
549 | 0x00000000 /* C31: Reserved*/ | 549 | 0x00000000 /* C31: Reserved*/ |
@@ -578,7 +578,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
578 | 0x00000000, /* C25: Reserved */ | 578 | 0x00000000, /* C25: Reserved */ |
579 | 0x00000000, /* C26: Reserved*/ | 579 | 0x00000000, /* C26: Reserved*/ |
580 | 0x00000000, /* C27: Reserved*/ | 580 | 0x00000000, /* C27: Reserved*/ |
581 | 0x00000000, /* C28: Reserved*/ | 581 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
582 | 0x00000000, /* C29: Reserved*/ | 582 | 0x00000000, /* C29: Reserved*/ |
583 | 0x00000000, /* C30: Reserved*/ | 583 | 0x00000000, /* C30: Reserved*/ |
584 | 0x00000000 /* C31: Reserved*/ | 584 | 0x00000000 /* C31: Reserved*/ |
@@ -613,7 +613,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
613 | 0x00000000, /* C25: Reserved */ | 613 | 0x00000000, /* C25: Reserved */ |
614 | 0x00000000, /* C26: Reserved*/ | 614 | 0x00000000, /* C26: Reserved*/ |
615 | 0x00000000, /* C27: Reserved*/ | 615 | 0x00000000, /* C27: Reserved*/ |
616 | 0x00000000, /* C28: Reserved*/ | 616 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
617 | 0x00000000, /* C29: Reserved*/ | 617 | 0x00000000, /* C29: Reserved*/ |
618 | 0x00000000, /* C30: Reserved*/ | 618 | 0x00000000, /* C30: Reserved*/ |
619 | 0x00000000 /* C31: Reserved*/ | 619 | 0x00000000 /* C31: Reserved*/ |
@@ -648,7 +648,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
648 | 0x00000000, /* C25: Reserved*/ | 648 | 0x00000000, /* C25: Reserved*/ |
649 | 0xFF020400, /* C26: Eflow Exception route */ | 649 | 0xFF020400, /* C26: Eflow Exception route */ |
650 | 0x00000000, /* C27: Reserved*/ | 650 | 0x00000000, /* C27: Reserved*/ |
651 | 0x00000000, /* C28: Reserved*/ | 651 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
652 | 0x00000000, /* C29: Reserved*/ | 652 | 0x00000000, /* C29: Reserved*/ |
653 | 0x00000000, /* C30: Reserved*/ | 653 | 0x00000000, /* C30: Reserved*/ |
654 | 0x00000000 /* C31: Reserved*/ | 654 | 0x00000000 /* C31: Reserved*/ |
@@ -683,7 +683,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
683 | 0x00000000, /* C25: Reserved*/ | 683 | 0x00000000, /* C25: Reserved*/ |
684 | 0xFF020400, /* C26: Eflow Exception route */ | 684 | 0xFF020400, /* C26: Eflow Exception route */ |
685 | 0xFFF80800, /* C27: Command Buffer */ | 685 | 0xFFF80800, /* C27: Command Buffer */ |
686 | 0x00000000, /* C28: Reserved*/ | 686 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
687 | 0x00000000, /* C29: Reserved*/ | 687 | 0x00000000, /* C29: Reserved*/ |
688 | 0x00000000, /* C30: Reserved*/ | 688 | 0x00000000, /* C30: Reserved*/ |
689 | 0x00000000 /* C31: Reserved*/ | 689 | 0x00000000 /* C31: Reserved*/ |
@@ -718,7 +718,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
718 | 0x00000000, /* C25: Reserved*/ | 718 | 0x00000000, /* C25: Reserved*/ |
719 | 0xFF020400, /* C26: Eflow Exception route */ | 719 | 0xFF020400, /* C26: Eflow Exception route */ |
720 | 0xFFF80900, /* C27: Command Buffer */ | 720 | 0xFFF80900, /* C27: Command Buffer */ |
721 | 0x00000000, /* C28: Reserved*/ | 721 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
722 | 0x00000000, /* C29: Reserved*/ | 722 | 0x00000000, /* C29: Reserved*/ |
723 | 0x00000000, /* C30: Reserved*/ | 723 | 0x00000000, /* C30: Reserved*/ |
724 | 0x00000000 /* C31: Reserved*/ | 724 | 0x00000000 /* C31: Reserved*/ |
@@ -753,7 +753,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
753 | 0x00000000, /* C25: Reserved*/ | 753 | 0x00000000, /* C25: Reserved*/ |
754 | 0xFF020400, /* C26: Eflow Exception route */ | 754 | 0xFF020400, /* C26: Eflow Exception route */ |
755 | 0xFFF80800, /* C27: Command Buffer */ | 755 | 0xFFF80800, /* C27: Command Buffer */ |
756 | 0x00000000, /* C28: Reserved*/ | 756 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
757 | 0x00000000, /* C29: Reserved*/ | 757 | 0x00000000, /* C29: Reserved*/ |
758 | 0x00000000, /* C30: Reserved*/ | 758 | 0x00000000, /* C30: Reserved*/ |
759 | 0x00000000 /* C31: Reserved*/ | 759 | 0x00000000 /* C31: Reserved*/ |
@@ -788,7 +788,7 @@ static const u32 pa2_pdsp_const_reg_map[PA2_NUM_PDSPS][PA2_PDSP_CONST_NUM_REG] \ | |||
788 | 0x00000000, /* C25: Reserved*/ | 788 | 0x00000000, /* C25: Reserved*/ |
789 | 0xFF020400, /* C26: Eflow Exception route */ | 789 | 0xFF020400, /* C26: Eflow Exception route */ |
790 | 0xFFF80800, /* C27: Command Buffer */ | 790 | 0xFFF80800, /* C27: Command Buffer */ |
791 | 0x00000000, /* C28: Reserved*/ | 791 | 0xFF020500, /* C28: Port (Interface-based) configurations */ |
792 | 0x00000000, /* C29: Reserved*/ | 792 | 0x00000000, /* C29: Reserved*/ |
793 | 0x00000000, /* C30: Reserved*/ | 793 | 0x00000000, /* C30: Reserved*/ |
794 | 0x00000000 /* C31: Reserved*/ | 794 | 0x00000000 /* C31: Reserved*/ |