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1 | * Texas Instruments Davinci NAND | ||
2 | |||
3 | This file provides information, what the device node for the | ||
4 | davinci nand interface contain. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "ti,davinci-nand"; | ||
8 | - reg : contain 2 offset/length values: | ||
9 | - offset and length for the access window | ||
10 | - offset and length for accessing the aemif control registers | ||
11 | - ti,davinci-chipselect: Indicates on the davinci_nand driver which | ||
12 | chipselect is used for accessing the nand. | ||
13 | |||
14 | Recommended properties : | ||
15 | - ti,davinci-mask-ale: mask for ale | ||
16 | - ti,davinci-mask-cle: mask for cle | ||
17 | - ti,davinci-mask-chipsel: mask for chipselect | ||
18 | - ti,davinci-ecc-mode: ECC mode valid values for davinci driver: | ||
19 | - "none" | ||
20 | - "soft" | ||
21 | - "hw" | ||
22 | - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. | ||
23 | - ti,davinci-nand-buswidth: buswidth 8 or 16 | ||
24 | - ti,davinci-nand-use-bbt: use flash based bad block table support. | ||
25 | - ti,davinci-no-subpage-write: disable subpage write for the device. | ||
26 | |||
27 | <<<<<<< HEAD | ||
28 | nand device bindings may contain additional sub-nodes describing | ||
29 | partitions of the address space. See partition.txt for more detail. | ||
30 | |||
31 | Example(da850 EVM ): | ||
32 | nand_cs3@62000000 { | ||
33 | compatible = "ti,davinci-nand"; | ||
34 | reg = <0x62000000 0x807ff | ||
35 | 0x68000000 0x8000>; | ||
36 | ti,davinci-chipselect = <1>; | ||
37 | ti,davinci-mask-ale = <0>; | ||
38 | ti,davinci-mask-cle = <0>; | ||
39 | ti,davinci-mask-chipsel = <0>; | ||
40 | ti,davinci-ecc-mode = "hw"; | ||
41 | ti,davinci-ecc-bits = <4>; | ||
42 | ti,davinci-nand-use-bbt; | ||
43 | |||
44 | partition@180000 { | ||
45 | label = "ubifs"; | ||
46 | reg = <0x180000 0x7e80000>; | ||
47 | }; | ||
48 | }; | ||
49 | |||
50 | Example (enbw_cmc board): | ||
51 | aemif@60000000 { | ||
52 | compatible = "ti,davinci-aemif"; | ||
53 | #address-cells = <2>; | ||
54 | #size-cells = <1>; | ||
55 | reg = <0x68000000 0x80000>; | ||
56 | ranges = <2 0 0x60000000 0x02000000 | ||
57 | 3 0 0x62000000 0x02000000 | ||
58 | 4 0 0x64000000 0x02000000 | ||
59 | 5 0 0x66000000 0x02000000 | ||
60 | 6 0 0x68000000 0x02000000>; | ||
61 | nand@3,0 { | ||
62 | compatible = "ti,davinci-nand"; | ||
63 | reg = <3 0x0 0x807ff | ||
64 | 6 0x0 0x8000>; | ||
65 | #address-cells = <1>; | ||
66 | #size-cells = <1>; | ||
67 | ti,davinci-chipselect = <1>; | ||
68 | ti,davinci-mask-ale = <0>; | ||
69 | ti,davinci-mask-cle = <0>; | ||
70 | ti,davinci-mask-chipsel = <0>; | ||
71 | ti,davinci-ecc-mode = "hw"; | ||
72 | ti,davinci-ecc-bits = <4>; | ||
73 | ti,davinci-nand-use-bbt; | ||
74 | }; | ||
75 | }; | ||