aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-davinci/dm355.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-davinci/dm355.c')
-rw-r--r--arch/arm/mach-davinci/dm355.c583
1 files changed, 302 insertions, 281 deletions
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a11034a358f..34648550258 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -13,8 +13,13 @@
13#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16
17#include <linux/spi/spi.h> 16#include <linux/spi/spi.h>
17#include <linux/clkdev.h>
18#include <linux/clk-provider.h>
19#include <linux/platform_data/clk-davinci-pll.h>
20#include <linux/platform_data/clk-davinci-psc.h>
21#include <linux/platform_data/davinci-clock.h>
22#include <mach/pll.h>
18 23
19#include <asm/mach/map.h> 24#include <asm/mach/map.h>
20 25
@@ -30,10 +35,14 @@
30#include <mach/gpio-davinci.h> 35#include <mach/gpio-davinci.h>
31 36
32#include "davinci.h" 37#include "davinci.h"
33#include "clock.h"
34#include "mux.h" 38#include "mux.h"
35#include "asp.h" 39#include "asp.h"
36 40
41#define PLLM 0x110
42#define PREDIV 0x114
43#define POSTDIV 0x128
44#define PLLM_PLLM_MASK 0xff
45
37#define DM355_UART2_BASE (IO_PHYS + 0x206000) 46#define DM355_UART2_BASE (IO_PHYS + 0x206000)
38#define DM355_OSD_BASE (IO_PHYS + 0x70200) 47#define DM355_OSD_BASE (IO_PHYS + 0x70200)
39#define DM355_VENC_BASE (IO_PHYS + 0x70400) 48#define DM355_VENC_BASE (IO_PHYS + 0x70400)
@@ -43,343 +52,330 @@
43 */ 52 */
44#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ 53#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
45 54
46static struct pll_data pll1_data = { 55static struct clk_davinci_pll_data pll1_data = {
47 .num = 1, 56 .phy_pllm = DAVINCI_PLL1_BASE + PLLM,
48 .phys_base = DAVINCI_PLL1_BASE, 57 .phy_prediv = DAVINCI_PLL1_BASE + PREDIV,
49 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 58 .phy_postdiv = DAVINCI_PLL1_BASE + POSTDIV,
59 .pllm_mask = PLLM_PLLM_MASK,
60 .prediv_mask = PLLDIV_RATIO_MASK,
61 .postdiv_mask = PLLDIV_RATIO_MASK,
62 .num = 1,
63 .pll_flags = CLK_DAVINCI_PLL_HAS_PREDIV |
64 CLK_DAVINCI_PLL_HAS_POSTDIV,
65 .fixed_prediv = 8,
50}; 66};
51 67
52static struct pll_data pll2_data = { 68static struct clk_fixed_rate_data clkin_data = {
53 .num = 2,
54 .phys_base = DAVINCI_PLL2_BASE,
55 .flags = PLL_HAS_PREDIV,
56};
57
58static struct clk ref_clk = {
59 .name = "ref_clk",
60 /* FIXME -- crystal rate is board-specific */ 69 /* FIXME -- crystal rate is board-specific */
61 .rate = DM355_REF_FREQ, 70 .rate = DM355_REF_FREQ,
62}; 71 .flags = CLK_IS_ROOT,
63
64static struct clk pll1_clk = {
65 .name = "pll1",
66 .parent = &ref_clk,
67 .flags = CLK_PLL,
68 .pll_data = &pll1_data,
69};
70
71static struct clk pll1_aux_clk = {
72 .name = "pll1_aux_clk",
73 .parent = &pll1_clk,
74 .flags = CLK_PLL | PRE_PLL,
75};
76
77static struct clk pll1_sysclk1 = {
78 .name = "pll1_sysclk1",
79 .parent = &pll1_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82}; 72};
83 73
84static struct clk pll1_sysclk2 = { 74static struct davinci_clk ref_clk_clkin = {
85 .name = "pll1_sysclk2", 75 .name = "clkin",
86 .parent = &pll1_clk, 76 .type = DAVINCI_FIXED_RATE_CLK,
87 .flags = CLK_PLL, 77 .clk_data = {
88 .div_reg = PLLDIV2, 78 .data = &clkin_data,
89}; 79 },
90
91static struct clk pll1_sysclk3 = {
92 .name = "pll1_sysclk3",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
96};
97
98static struct clk pll1_sysclk4 = {
99 .name = "pll1_sysclk4",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV4,
103};
104
105static struct clk pll1_sysclkbp = {
106 .name = "pll1_sysclkbp",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL | PRE_PLL,
109 .div_reg = BPDIV
110};
111
112static struct clk vpss_dac_clk = {
113 .name = "vpss_dac",
114 .parent = &pll1_sysclk3,
115 .lpsc = DM355_LPSC_VPSS_DAC,
116};
117
118static struct clk vpss_master_clk = {
119 .name = "vpss_master",
120 .parent = &pll1_sysclk4,
121 .lpsc = DAVINCI_LPSC_VPSSMSTR,
122 .flags = CLK_PSC,
123};
124
125static struct clk vpss_slave_clk = {
126 .name = "vpss_slave",
127 .parent = &pll1_sysclk4,
128 .lpsc = DAVINCI_LPSC_VPSSSLV,
129};
130
131static struct clk clkout1_clk = {
132 .name = "clkout1",
133 .parent = &pll1_aux_clk,
134 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135};
136
137static struct clk clkout2_clk = {
138 .name = "clkout2",
139 .parent = &pll1_sysclkbp,
140};
141
142static struct clk pll2_clk = {
143 .name = "pll2",
144 .parent = &ref_clk,
145 .flags = CLK_PLL,
146 .pll_data = &pll2_data,
147};
148
149static struct clk pll2_sysclk1 = {
150 .name = "pll2_sysclk1",
151 .parent = &pll2_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV1,
154};
155
156static struct clk pll2_sysclkbp = {
157 .name = "pll2_sysclkbp",
158 .parent = &pll2_clk,
159 .flags = CLK_PLL | PRE_PLL,
160 .div_reg = BPDIV
161};
162
163static struct clk clkout3_clk = {
164 .name = "clkout3",
165 .parent = &pll2_sysclkbp,
166 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167}; 80};
168 81
169static struct clk arm_clk = { 82static struct clk_fixed_rate_data oscin_data = {
170 .name = "arm_clk", 83 /* FIXME -- crystal rate is board-specific */
171 .parent = &pll1_sysclk1, 84 .rate = DM355_REF_FREQ,
172 .lpsc = DAVINCI_LPSC_ARM, 85 .flags = CLK_IS_ROOT,
173 .flags = ALWAYS_ENABLED,
174}; 86};
175 87
176/* 88static struct davinci_clk ref_clk_oscin = {
177 * NOT LISTED below, and not touched by Linux 89 .name = "oscin",
178 * - in SyncReset state by default 90 .type = DAVINCI_FIXED_RATE_CLK,
179 * .lpsc = DAVINCI_LPSC_TPCC, 91 .clk_data = {
180 * .lpsc = DAVINCI_LPSC_TPTC0, 92 .data = &oscin_data,
181 * .lpsc = DAVINCI_LPSC_TPTC1, 93 },
182 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183 * .lpsc = DAVINCI_LPSC_MEMSTICK,
184 * - in Enabled state by default
185 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
192 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
193 */
194
195static struct clk mjcp_clk = {
196 .name = "mjcp",
197 .parent = &pll1_sysclk1,
198 .lpsc = DAVINCI_LPSC_IMCOP,
199}; 94};
200 95
201static struct clk uart0_clk = { 96static const char *ref_clk_mux_parents[] = {"clkin", "oscin"};
202 .name = "uart0",
203 .parent = &pll1_aux_clk,
204 .lpsc = DAVINCI_LPSC_UART0,
205};
206 97
207static struct clk uart1_clk = { 98static struct clk_mux_data ref_clk_mux_data = {
208 .name = "uart1", 99 .shift = PLLCTL_CLKMODE_SHIFT,
209 .parent = &pll1_aux_clk, 100 .width = PLLCTL_CLKMODE_WIDTH,
210 .lpsc = DAVINCI_LPSC_UART1, 101 .num_parents = ARRAY_SIZE(ref_clk_mux_parents),
102 .parents = ref_clk_mux_parents,
103 .phys_base = DAVINCI_PLL1_BASE + PLLCTL,
211}; 104};
212 105
213static struct clk uart2_clk = { 106static struct davinci_clk ref_clk_mux = {
214 .name = "uart2", 107 .name = "ref_clk_mux",
215 .parent = &pll1_sysclk2, 108 .parent = &ref_clk_clkin,
216 .lpsc = DAVINCI_LPSC_UART2, 109 .type = DAVINCI_MUX_CLK,
110 .clk_data = {
111 .data = &ref_clk_mux_data,
112 }
217}; 113};
218 114
219static struct clk i2c_clk = { 115static struct davinci_clk pll1_clk = {
220 .name = "i2c", 116 .name = "pll1",
221 .parent = &pll1_aux_clk, 117 .parent = &ref_clk_mux,
222 .lpsc = DAVINCI_LPSC_I2C, 118 .type = DAVINCI_MAIN_PLL_CLK,
119 .clk_data = {
120 .data = &pll1_data,
121 },
223}; 122};
224 123
225static struct clk asp0_clk = { 124static const char *pll1_plldiv_clk_mux_parents[] = {
226 .name = "asp0", 125 "ref_clk_mux", "pll1"};
227 .parent = &pll1_sysclk2,
228 .lpsc = DAVINCI_LPSC_McBSP,
229};
230 126
231static struct clk asp1_clk = { 127static struct clk_mux_data pll1_plldiv_clk_mux_data = {
232 .name = "asp1", 128 .shift = PLLCTL_PLLEN_SHIFT,
233 .parent = &pll1_sysclk2, 129 .width = PLLCTL_PLLEN_WIDTH,
234 .lpsc = DM355_LPSC_McBSP1, 130 .num_parents = ARRAY_SIZE(pll1_plldiv_clk_mux_parents),
131 .parents = pll1_plldiv_clk_mux_parents,
132 .phys_base = DAVINCI_PLL1_BASE + PLLCTL,
235}; 133};
236 134
237static struct clk mmcsd0_clk = { 135static struct davinci_clk pll1_plldiv_clk_mux = {
238 .name = "mmcsd0", 136 .name = "pll1_plldiv_clk_mux",
239 .parent = &pll1_sysclk2, 137 .parent = &pll1_clk,
240 .lpsc = DAVINCI_LPSC_MMC_SD, 138 .type = DAVINCI_MUX_CLK,
139 .clk_data = {
140 .data = &pll1_plldiv_clk_mux_data,
141 },
241}; 142};
242 143
243static struct clk mmcsd1_clk = { 144#define define_pll1_div_clk(__pll, __div, __name) \
244 .name = "mmcsd1", 145 static struct clk_divider_data pll1_div_data##__div = { \
245 .parent = &pll1_sysclk2, 146 .div_reg = DAVINCI_PLL1_BASE + PLLDIV##__div, \
246 .lpsc = DM355_LPSC_MMC_SD1, 147 .width = 5, \
247}; 148 }; \
149 \
150 static struct davinci_clk __name = { \
151 .name = #__name, \
152 .parent = &__pll, \
153 .type = DAVINCI_PRG_DIV_CLK, \
154 .clk_data = { \
155 .data = &pll1_div_data##__div, \
156 }, \
157 }
248 158
249static struct clk spi0_clk = { 159define_pll1_div_clk(pll1_plldiv_clk_mux, 1, pll1_sysclk1);
250 .name = "spi0", 160define_pll1_div_clk(pll1_plldiv_clk_mux, 2, pll1_sysclk2);
251 .parent = &pll1_sysclk2, 161define_pll1_div_clk(pll1_plldiv_clk_mux, 3, pll1_sysclk3);
252 .lpsc = DAVINCI_LPSC_SPI, 162define_pll1_div_clk(pll1_plldiv_clk_mux, 4, pll1_sysclk4);
253};
254 163
255static struct clk spi1_clk = { 164static struct clk_fixed_factor_data fixed_clk_data = {
256 .name = "spi1", 165 .mult = 1,
257 .parent = &pll1_sysclk2, 166 .div = 1,
258 .lpsc = DM355_LPSC_SPI1,
259}; 167};
260 168
261static struct clk spi2_clk = { 169static struct davinci_clk pll1_aux_clk = {
262 .name = "spi2", 170 .name = "pll1_aux_clk",
263 .parent = &pll1_sysclk2, 171 .parent = &ref_clk_mux,
264 .lpsc = DM355_LPSC_SPI2, 172 .type = DAVINCI_FIXED_FACTOR_CLK,
173 .clk_data = {
174 .fixed_factor = &fixed_clk_data,
175 },
265}; 176};
266 177
267static struct clk gpio_clk = { 178static struct clk_divider_data pll1_sysclkbp_data = {
268 .name = "gpio", 179 .div_reg = BPDIV,
269 .parent = &pll1_sysclk2,
270 .lpsc = DAVINCI_LPSC_GPIO,
271}; 180};
272 181
273static struct clk aemif_clk = { 182static struct davinci_clk pll1_sysclkbp = {
274 .name = "aemif", 183 .name = "pll1_sysclkbp",
275 .parent = &pll1_sysclk2, 184 .parent = &ref_clk_mux,
276 .lpsc = DAVINCI_LPSC_AEMIF, 185 .type = DAVINCI_PRG_DIV_CLK,
186 .clk_data = {
187 .data = &pll1_sysclkbp_data,
188 },
277}; 189};
278 190
279static struct clk pwm0_clk = { 191#define __lpsc_clk(cname, _parent, mod, flgs, _flgs, dom) \
280 .name = "pwm0", 192 static struct clk_davinci_psc_data clk_psc_data##cname = { \
281 .parent = &pll1_aux_clk, 193 .domain = DAVINCI_GPSC_##dom, \
282 .lpsc = DAVINCI_LPSC_PWM0, 194 .lpsc = DAVINCI_LPSC_##mod, \
283}; 195 .flags = flgs, \
196 }; \
197 \
198 static struct davinci_clk clk_##cname = { \
199 .name = #cname, \
200 .parent = &_parent, \
201 .flags = _flgs, \
202 .type = DAVINCI_PSC_CLK, \
203 .clk_data = { \
204 .data = &clk_psc_data##cname \
205 }, \
206 }
284 207
285static struct clk pwm1_clk = { 208#define lpsc_clk_enabled(cname, parent, mod) \
286 .name = "pwm1", 209 __lpsc_clk(cname, parent, mod, 0, ALWAYS_ENABLED, ARMDOMAIN)
287 .parent = &pll1_aux_clk, 210
288 .lpsc = DAVINCI_LPSC_PWM1, 211#define lpsc_clk(cname, flgs, parent, mod, dom) \
289}; 212 __lpsc_clk(cname, parent, mod, flgs, 0, dom)
213
214#define __dm355_lpsc_clk(cname, _parent, mod, flgs, _flgs, dom) \
215 static struct clk_davinci_psc_data clk_psc_data##cname = { \
216 .domain = DAVINCI_GPSC_##dom, \
217 .lpsc = DM355_LPSC_##mod, \
218 .flags = flgs, \
219 }; \
220 \
221 static struct davinci_clk clk_##cname = { \
222 .name = #cname, \
223 .parent = &_parent, \
224 .flags = _flgs, \
225 .type = DAVINCI_PSC_CLK, \
226 .clk_data = { \
227 .data = &clk_psc_data##cname \
228 }, \
229 }
290 230
291static struct clk pwm2_clk = { 231#define dm355_lpsc_clk(cname, flgs, parent, mod, dom) \
292 .name = "pwm2", 232 __dm355_lpsc_clk(cname, parent, mod, flgs, 0, dom)
293 .parent = &pll1_aux_clk, 233
294 .lpsc = DAVINCI_LPSC_PWM2, 234dm355_lpsc_clk(vpss_dac, 0, pll1_sysclk3, VPSS_DAC, ARMDOMAIN);
235lpsc_clk(vpss_master, 0, pll1_sysclk4, VPSSMSTR, ARMDOMAIN);
236lpsc_clk(vpss_slave, 0, pll1_sysclk4, VPSSSLV, ARMDOMAIN);
237lpsc_clk_enabled(arm, pll1_sysclk1, ARM);
238lpsc_clk(mjcp, 0, pll1_sysclk1, IMCOP, ARMDOMAIN);
239lpsc_clk(uart0, 0, ref_clk_mux, UART0, ARMDOMAIN);
240lpsc_clk(uart1, 0, ref_clk_mux, UART1, ARMDOMAIN);
241lpsc_clk(uart2, 0, pll1_sysclk2, UART2, ARMDOMAIN);
242lpsc_clk(i2c, 0, ref_clk_mux, I2C, ARMDOMAIN);
243lpsc_clk(asp0, 0, pll1_sysclk2, McBSP, ARMDOMAIN);
244dm355_lpsc_clk(asp1, 0, pll1_sysclk2, McBSP1, ARMDOMAIN);
245lpsc_clk(mmcsd0, 0, pll1_sysclk2, MMC_SD, ARMDOMAIN);
246dm355_lpsc_clk(mmcsd1, 0, pll1_sysclk2, MMC_SD1, ARMDOMAIN);
247lpsc_clk(spi0, 0, pll1_sysclk2, SPI, ARMDOMAIN);
248dm355_lpsc_clk(spi1, 0, pll1_sysclk2, SPI1, ARMDOMAIN);
249dm355_lpsc_clk(spi2, 0, pll1_sysclk2, SPI2, ARMDOMAIN);
250lpsc_clk(gpio, 0, pll1_sysclk2, GPIO, ARMDOMAIN);
251lpsc_clk(aemif, 0, pll1_sysclk2, AEMIF, ARMDOMAIN);
252lpsc_clk(pwm0, 0, ref_clk_mux, PWM0, ARMDOMAIN);
253lpsc_clk(pwm1, 0, ref_clk_mux, PWM1, ARMDOMAIN);
254lpsc_clk(pwm2, 0, ref_clk_mux, PWM2, ARMDOMAIN);
255dm355_lpsc_clk(pwm3, 0, ref_clk_mux, PWM3, ARMDOMAIN);
256lpsc_clk(timer0, 0, ref_clk_mux, TIMER0, ARMDOMAIN);
257lpsc_clk(timer1, 0, ref_clk_mux, TIMER1, ARMDOMAIN);
258/* REVISIT: why can't this be disabled? */
259lpsc_clk(timer2, CLK_IGNORE_UNUSED, ref_clk_mux, TIMER2, ARMDOMAIN);
260dm355_lpsc_clk(timer3, 0, ref_clk_mux, TIMER3, ARMDOMAIN);
261dm355_lpsc_clk(rto, 0, ref_clk_mux, RTO, ARMDOMAIN);
262lpsc_clk(usb, 0, pll1_sysclk2, USB, ARMDOMAIN);
263
264static struct clk_davinci_pll_data pll2_data = {
265 .phy_pllm = DAVINCI_PLL2_BASE + PLLM,
266 .phy_prediv = DAVINCI_PLL2_BASE + PREDIV,
267 .phy_postdiv = DAVINCI_PLL2_BASE + POSTDIV,
268 .pllm_mask = PLLM_PLLM_MASK,
269 .prediv_mask = PLLDIV_RATIO_MASK,
270 .postdiv_mask = PLLDIV_RATIO_MASK,
271 .num = 2,
272 .pll_flags = CLK_DAVINCI_PLL_HAS_PREDIV,
273};
274
275static struct davinci_clk pll2_clk = {
276 .name = "pll2",
277 .parent = &ref_clk_mux,
278 .type = DAVINCI_MAIN_PLL_CLK,
279 .clk_data = {
280 .data = &pll2_data,
281 },
295}; 282};
296 283
297static struct clk pwm3_clk = { 284#define define_pll2_div_clk(__pll, __div, __name) \
298 .name = "pwm3", 285 static struct clk_divider_data pll2_div_data##__div = { \
299 .parent = &pll1_aux_clk, 286 .div_reg = DAVINCI_PLL2_BASE + PLLDIV##__div, \
300 .lpsc = DM355_LPSC_PWM3, 287 .width = 5, \
301}; 288 }; \
289 \
290 static struct davinci_clk __name = { \
291 .name = #__name, \
292 .parent = &__pll, \
293 .type = DAVINCI_PRG_DIV_CLK, \
294 .clk_data = { \
295 .data = &pll2_div_data##__div, \
296 }, \
297 }
302 298
303static struct clk timer0_clk = { 299static const char *pll2_plldiv_clk_mux_parents[] = {
304 .name = "timer0", 300 "ref_clk_mux", "pll2"};
305 .parent = &pll1_aux_clk,
306 .lpsc = DAVINCI_LPSC_TIMER0,
307};
308 301
309static struct clk timer1_clk = { 302static struct clk_mux_data pll2_plldiv_clk_mux_data = {
310 .name = "timer1", 303 .shift = PLLCTL_PLLEN_SHIFT,
311 .parent = &pll1_aux_clk, 304 .width = PLLCTL_PLLEN_WIDTH,
312 .lpsc = DAVINCI_LPSC_TIMER1, 305 .num_parents = ARRAY_SIZE(pll2_plldiv_clk_mux_parents),
306 .parents = pll2_plldiv_clk_mux_parents,
307 .phys_base = DAVINCI_PLL2_BASE + PLLCTL,
313}; 308};
314 309
315static struct clk timer2_clk = { 310static struct davinci_clk pll2_plldiv_clk_mux = {
316 .name = "timer2", 311 .name = "pll2_plldiv_clk_mux",
317 .parent = &pll1_aux_clk, 312 .parent = &pll2_clk,
318 .lpsc = DAVINCI_LPSC_TIMER2, 313 .type = DAVINCI_MUX_CLK,
319 .usecount = 1, /* REVISIT: why can't this be disabled? */ 314 .clk_data = {
315 .data = &pll2_plldiv_clk_mux_data,
316 },
320}; 317};
321 318
322static struct clk timer3_clk = { 319define_pll2_div_clk(pll2_plldiv_clk_mux, 1, pll2_sysclk1);
323 .name = "timer3",
324 .parent = &pll1_aux_clk,
325 .lpsc = DM355_LPSC_TIMER3,
326};
327 320
328static struct clk rto_clk = { 321static struct clk_divider_data pll2_sysclkbp_data = {
329 .name = "rto", 322 .div_reg = DAVINCI_PLL2_BASE + BPDIV,
330 .parent = &pll1_aux_clk, 323 .width = 5,
331 .lpsc = DM355_LPSC_RTO,
332}; 324};
333 325
334static struct clk usb_clk = { 326static struct davinci_clk pll2_sysclkbp = {
335 .name = "usb", 327 .name = "pll2_sysclkbp",
336 .parent = &pll1_sysclk2, 328 .parent = &ref_clk_mux,
337 .lpsc = DAVINCI_LPSC_USB, 329 .type = DAVINCI_PRG_DIV_CLK,
330 .clk_data = {
331 .data = &pll2_sysclkbp_data,
332 },
338}; 333};
339 334
340static struct clk_lookup dm355_clks[] = { 335static struct davinci_clk_lookup dm355_clks[] = {
341 CLK(NULL, "ref", &ref_clk), 336 CLK(NULL, "clkin", &ref_clk_clkin),
337 CLK(NULL, "oscin", &ref_clk_oscin),
338 CLK(NULL, "ref_clk_mux", &ref_clk_mux),
342 CLK(NULL, "pll1", &pll1_clk), 339 CLK(NULL, "pll1", &pll1_clk),
340 CLK(NULL, "pll1_plldiv_clk_mux", &pll1_plldiv_clk_mux),
343 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
344 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 342 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
345 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 343 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
346 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), 344 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
347 CLK(NULL, "pll1_aux", &pll1_aux_clk), 345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
348 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), 346 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
349 CLK(NULL, "vpss_dac", &vpss_dac_clk), 347 CLK(NULL, "vpss_dac", &clk_vpss_dac),
350 CLK("vpss", "master", &vpss_master_clk), 348 CLK(NULL, "vpss_master", &clk_vpss_master),
351 CLK("vpss", "slave", &vpss_slave_clk), 349 CLK(NULL, "vpss_slave", &clk_vpss_slave),
352 CLK(NULL, "clkout1", &clkout1_clk),
353 CLK(NULL, "clkout2", &clkout2_clk),
354 CLK(NULL, "pll2", &pll2_clk), 350 CLK(NULL, "pll2", &pll2_clk),
351 CLK(NULL, "pll2_plldiv_clk_mux", &pll2_plldiv_clk_mux),
355 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), 352 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
356 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), 353 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
357 CLK(NULL, "clkout3", &clkout3_clk), 354 CLK(NULL, "arm", &clk_arm),
358 CLK(NULL, "arm", &arm_clk), 355 CLK(NULL, "mjcp", &clk_mjcp),
359 CLK(NULL, "mjcp", &mjcp_clk), 356 CLK(NULL, "uart0", &clk_uart0),
360 CLK(NULL, "uart0", &uart0_clk), 357 CLK(NULL, "uart1", &clk_uart1),
361 CLK(NULL, "uart1", &uart1_clk), 358 CLK(NULL, "uart2", &clk_uart2),
362 CLK(NULL, "uart2", &uart2_clk), 359 CLK("i2c_davinci.1", NULL, &clk_i2c),
363 CLK("i2c_davinci.1", NULL, &i2c_clk), 360 CLK("davinci-mcbsp.0", NULL, &clk_asp0),
364 CLK("davinci-mcbsp.0", NULL, &asp0_clk), 361 CLK("davinci-mcbsp.1", NULL, &clk_asp1),
365 CLK("davinci-mcbsp.1", NULL, &asp1_clk), 362 CLK("davinci_mmc.0", NULL, &clk_mmcsd0),
366 CLK("dm6441-mmc.0", NULL, &mmcsd0_clk), 363 CLK("davinci_mmc.1", NULL, &clk_mmcsd1),
367 CLK("dm6441-mmc.1", NULL, &mmcsd1_clk), 364 CLK("spi_davinci.0", NULL, &clk_spi0),
368 CLK("spi_davinci.0", NULL, &spi0_clk), 365 CLK("spi_davinci.1", NULL, &clk_spi1),
369 CLK("spi_davinci.1", NULL, &spi1_clk), 366 CLK("spi_davinci.2", NULL, &clk_spi2),
370 CLK("spi_davinci.2", NULL, &spi2_clk), 367 CLK(NULL, "gpio", &clk_gpio),
371 CLK(NULL, "gpio", &gpio_clk), 368 CLK(NULL, "aemif", &clk_aemif),
372 CLK(NULL, "aemif", &aemif_clk), 369 CLK(NULL, "pwm0", &clk_pwm0),
373 CLK(NULL, "pwm0", &pwm0_clk), 370 CLK(NULL, "pwm1", &clk_pwm1),
374 CLK(NULL, "pwm1", &pwm1_clk), 371 CLK(NULL, "pwm2", &clk_pwm2),
375 CLK(NULL, "pwm2", &pwm2_clk), 372 CLK(NULL, "pwm3", &clk_pwm3),
376 CLK(NULL, "pwm3", &pwm3_clk), 373 CLK(NULL, "timer0", &clk_timer0),
377 CLK(NULL, "timer0", &timer0_clk), 374 CLK(NULL, "timer1", &clk_timer1),
378 CLK(NULL, "timer1", &timer1_clk), 375 CLK("watchdog", NULL, &clk_timer2),
379 CLK("watchdog", NULL, &timer2_clk), 376 CLK(NULL, "timer3", &clk_timer3),
380 CLK(NULL, "timer3", &timer3_clk), 377 CLK(NULL, "rto", &clk_rto),
381 CLK(NULL, "rto", &rto_clk), 378 CLK(NULL, "usb", &clk_usb),
382 CLK(NULL, "usb", &usb_clk),
383 CLK(NULL, NULL, NULL), 379 CLK(NULL, NULL, NULL),
384}; 380};
385 381
@@ -960,6 +956,30 @@ static struct platform_device dm355_serial_device = {
960 }, 956 },
961}; 957};
962 958
959static struct clk_lookup vpss_master_lookups[] = {
960 { .dev_id = "dm355_ccdc", .con_id = "master", },
961};
962
963static struct clk_lookup vpss_slave_lookups[] = {
964 { .dev_id = "dm355_ccdc", .con_id = "slave", },
965};
966
967static struct davinci_dev_lookup dev_clk_lookups[] = {
968 {
969 .con_id = "vpss_master",
970 .num_devs = ARRAY_SIZE(vpss_master_lookups),
971 .lookups = vpss_master_lookups,
972 },
973 {
974 .con_id = "vpss_slave",
975 .num_devs = ARRAY_SIZE(vpss_slave_lookups),
976 .lookups = vpss_slave_lookups,
977 },
978 {
979 .con_id = NULL,
980 },
981};
982
963static struct davinci_soc_info davinci_soc_info_dm355 = { 983static struct davinci_soc_info davinci_soc_info_dm355 = {
964 .io_desc = dm355_io_desc, 984 .io_desc = dm355_io_desc,
965 .io_desc_num = ARRAY_SIZE(dm355_io_desc), 985 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
@@ -967,6 +987,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
967 .ids = dm355_ids, 987 .ids = dm355_ids,
968 .ids_num = ARRAY_SIZE(dm355_ids), 988 .ids_num = ARRAY_SIZE(dm355_ids),
969 .cpu_clks = dm355_clks, 989 .cpu_clks = dm355_clks,
990 .dev_clk_lookups = dev_clk_lookups,
970 .psc_bases = dm355_psc_bases, 991 .psc_bases = dm355_psc_bases,
971 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), 992 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
972 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 993 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
generated by cgit v1.2.3 (git 2.39.2)